( ESNUG 356 Item 1 ) --------------------------------------------- [8/03/00]

Subject: ( ESNUG 355 #13 )  2nd Plea For Help On Opposite-Input Tri-states

> In the "early" days of ESNUG there was a thread talking about a Synopsys
> bug concerning the usage of tri-state buffers that have 2 enable inputs
> that require opposite logic levels.  I just ran into the same problem
> and am trying to find a solution.  Was there a solution posted (that I
> didn't find)?
>
> I tried to use the 'pin_opposite' attribute in the library but Design
> Compiler failed to map the tri-state buffers.  I tried the 'x_function'
> with the same result.  I tried the 'contention_condition' with the result
> that Design Compiler mapped the tri-state buffers but tied one input to
> VCC (as it did without any special attribute).
>
> I think there must be someone who has solved this problem.
>
>     - Volker Rzehak
>       Texas Instruments Deutschland              Germany


From: Volker Rzehak <v-rzehak@ti.com>

John,

Unfortunately I didn't receive any feedback from my post on ESNUG and I'm
not able to solve the problem up to now.  I am quite stuck.  The only
solution I can think of at the moment is either to do it manually or use
tristate buffers with one input (and bigger area requirements).  Help!

    - Volker Rzehak
      Texas Instruments Deutschland              Germany


 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)