( ESNUG 355 Item 9 ) --------------------------------------------- [7/26/00]
From: London Jin <jinl@taec.toshiba.com>
Subject: Multiple Clocks -- Need Help Doing RTL MUXing For Scan Testing
Hi John,
My design is a multiple clock domain design. In scan mode, however, there
is only one clock: master_clock from chip pin. In order to balance the
clocks, I need to MUX all clocks including the master_clock.
wire scan_clk = scan_mode ? master_clk : master_clk;
Design Compiler recognizes that this is feedthrough logic, and thus no
MUXing logic is generated at all. I talked to Synopsys tech support, and
was told that there was no way to generate MUXing logic with the above
code. I seeks for designers' help.
- London Jin
Toshiba San Jose, CA
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