( ESNUG 355 Item 3 ) --------------------------------------------- [7/26/00]
From: Lou Villarosa <louv@paradyne.com>
Subject: ( ESNUG 331 #6 ) How Does Equivalence Checking Handle Scan FF's?
Hi, John,
I was considering using formal verification. However some questions came to
mind on how it actually works.
Internal scan and boundary scan were inserted into the design using Test
Compiler. At this point is it not true that the RTL and the gate netlist
are no longer functionally equivalent? Does formal verification handle this
effectivively. Also my ASIC vendor required that the ATPG vectors and a
subset of the functional vectors be simulated at gate level using estimated
pre-route delay for min and max conditions. So I had to spent a lot of CPU
time doing simulations anyway. Is top level design verification the proper
place for formal verification?
- Lou Villarosa, Jr.
Paradyne Corporation
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