( ESNUG 355 Item 2 ) --------------------------------------------- [7/26/00]
Subject: Synchronizers To Deal With Timing Problems Within Reset Trees
> I have a reset net in my design. I am using "set_ideal_net" command in
> Design Compiler, but I still see huge SN/RN to Q/QN delays in my SDF file
> for any FF connected to the reset net. My design is hierarchical. Does
> anyone know how to take care of this problem?
>
> - Hooman Dadrassan
From: johne@vcd.hp.com (John Eaton)
If you have an unfiltered async reset signal coming in a pad and going to
every flipflop in your design then you will run into trouble. As your
delays approach your clock period you become unable to bring the chip out
of reset on a known clock edge. State machines around the chip may come
out of reset on different clock edges. If your reset signal is asyncrous
to your clock, then they may not even come up in the right state.
You should filter your reset signal to ensure that transtions less than a
certain width do not propagate into your reset chain. The last thing you
want is a sub-nanosecond glitch coming in your reset pad and going to the
async reset of any flop.
You should use sync rather then async resets whenever possible. The only
difference to the flop is during the time period before the first clock
occurs. This will not effect the operation of the majority of flops in
your system. You will have a few that directly control pads that stil will
need an async reset.
Put a pulse stretcher on your reset so that your internal reset is several
cycles long. Then instead of buffering reset to every level you can resync
it using a flipflop. This will delay your reset by severl cycles but makes
it easy to ensure then every flop sees reset at the same clock.
- John Eaton
Hewlett-Packard Vancouver, Canada
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