( ESNUG 349 Item 10 ) -------------------------------------------- [4/18/00]
Subject: Methodology Details On The EmpowerTel MIPS PKS/Ambit RTL Tape-out
> For a detailed example, look at the recent hunk of FUD where Cadence is
> repackaging PKS and trying to say it's "new" and "improved" with their
> SP&R press announcement from last week. In it you have Jayan Ramankutty,
> the VP of engineering at EmpowerTel saying:
>
> "With PKS, we eliminated design iterations and got higher-performance
> results in a much shorter time. Adding routing to PKS and PKS to
> Silicon Ensemble will allow us to achieve correlation across tools
> and continue meeting our aggressive performance goals."
>
> Do some digging and you'll find Jayan Ramankutty was the same VP at Lara
> Technology in the Ambit press announcement a year earlier. Do some more
> digging and you find that EmpowerTEL and Lara Tech are the same company
> (they're just about to split) and they have 12 Cadence Verilog licenses,
> 5 Ambit licenses, 1 PKS license, and 1 complete Cadence Silicon Ensemble
> suit -- roughly about $1 million worth of software. Ramankutty's quote
> vaguely implies they used PKS in a big tape-out. (I'm sure that's what
> the Cadence sales force is saying to the customers and Wall Street.) It
> turns out that, yes, this is the first known PKS tape-out I've found,
> but PKS was only used on 50 kgates of MIPS core buried inside a 130 Mhz,
> 2.5 million gate design that had a lot of RAM. The role of PKS in this
> design at EmpowerTEL was trivial -- yet the Cadence press release was
> purposely written to *imply* much more. Classic FUD.
From: Anand Dharmaraj <ad@empowertel.com>
Hi John,
My name is Anand Dharmaraj. I am a design engineer at EmpowerTel Networks
and we have been using Ambit RTL & PKS tools for synthesis. My job was
synthesizing two versions of an embedded MIPs processor for usage in our
SOC. At this point we taped out our chip and are waiting for it to come
back from the fab.
There are a few things that I found that have helped us tapeout without
too much of a slip in schedules. One of them is the usage of the PKS
tool from Cadence.
Initially I was using the Ambit's RTL synthesis. We switched to PKS as
soon as it became available and started using both tools in parallel on the
MIPS processor. The results were so excellent that we dropped the Ambit
RTL synthesis runs in a matter of 1 week. PKS was extremely simple to set
up, all we needed was the source files, the scripts and constraints, and
floorplan DEF files (no wire load models needed). PKS synthesis time, from
scratch to getting a database that met frequency goals, was about 16-20 hrs.
On the other hand, just as a comparison, the Ambit RTL synthesis runs almost
always never completed, and the timing was off by 23 percent. We reached a
point of going with the timing that came out of the Ambit RTL synthesis run
because we were reaching a point of diminshing returns (area was increasing
and timing wasn't getting any better). That was when we started the PKS
runs. We did a lot of correlation work with respect to timing between the
Ambit RTL tools and Cadence Pearl, using wireload models, SDF, etc. The
numbers that came out of the PKS runs compared almost on the dot with the
Cadence Pearl timing numbers. The PKS run results in terms of violations
(i.e. slew time limits, long interconnects delays, large gate delays, etc.)
were almost none. We used a scan based architecture for our complete
design, requiring two rounds of synthesis, and we found that the design was
altered negatively after the separate runs.
I think PKS has been a extremely valuable addition to our design process.
- Anand Dharmaraj
EmpowerTel Networks San Jose, CA
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