( ESNUG 348 Item 14 ) -------------------------------------------- [3/30/00]
From: Chuck Wilde <cjwilde@lucent.com>
Subject: RESIZE Function In numeric_std.vhd Messes Up IKOS, ModelTech, DC
John,
We recently started using UNSIGNED instead of STD_LOGIC_VECTOR in our VHDL
code. This was done to conform to our internal coding standards. I was
using the IKOS FFX rtlcompiler tool on a design, and my VHDL code wouldn't
get through the analyze step. This same code had gone through Synopsys DC
and MTI's Modelsim. After some investigation, I found that the problem was
caused by the R.2 RESIZE function in numeric_std.vhd. The function
declaration is this:
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
There is a test in the code which checks the size of the UNSIGNED vector
against the desired NEW_SIZE
if (RESULT'LENGTH < ARG'LENGTH) then
...
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
...
end if;
The test assumes that the size of ARG is never equal to NEW_SIZE. If the
sizes are the same, the else condition gets evaluated as something like
this (for a vector of length 4):
RESULT(3 downto 4) := (others => '0');
and rtlcompile sees "3 downto 4" as a Fatal Error.
My fix was I changed the test of the sizes to
if (RESULT'LENGTH <= ARG'LENGTH)
changing "<" to "<=". That solved my problem.
I talked the problem over with some other members of my group, and we
decided that Synopsys DC and MTI must have built-in functions so they don't
actually use the RESIZE function found in numeric_std.vhd. I've looked at
source code from several places (IEEE, IKOS, MTI, Xilinx) and they all have
the same error. I fixed the code for my IKOS tool, but I don't know if
there is a common source supplied by IEEE which is then reused by all the
EDA vendors. I'm hoping your forum will get the word out.
- Chuck Wilde
Lucent Technologies
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