( ESNUG 343 Item 6 ) --------------------------------------------- [2/16/00]
Subject: ( ESNUG 341 #7 ) Hey! Use Synplicity Certify To FPGA Prototype!
> As part of the verification of our ASIC design, we plan to build an FPGA
> based prototype using Altera 20K Apex devices. Unfortunately we're having
> problems compiling our VHDL directly w/ Quartus (Altera's Apex software).
>
> - Justin Smith
> Atmosphere Networks Osborne Park, Western Australia
From: Chuck Seeley <cdseeley@micron.com>
Hi, John,
My name is Chuck Seeley and I work for Micron Technology. We currently are
developing a prototype board of an ASIC design out of Xilinx FPGAs. We are
currently in layout of our board and hope to power it on around March 1st.
I'm writing you to share my experience with a product from Synplicity called
Certify which is specifically for those who are using FPGAs to prototype
their ASIC design. While I'm not going to mention every feature of Certify,
I found it extremely valuable in partitioning our ASIC design into 10 Xilinx
XCV1000 FPGAs. As you know the two design constraints a designer faces when
trying to put a design into an FPGA is pin count and gate count. In our
case we implemented a Time Division Multiplexing (TDM) scheme to reduce our
pin count. However Certify does provide the designer with a couple of such
schemes as well as allowing the designer to implement his own scheme as we
did. One of the nicest Certify features is that it provides a GUI interface
which allows a designer to view a schematic of his design and provides the
ability to "drag and drop" modules into graphical representations of FPGAs.
Modules can be replicated several times if necessary in multiple FPGAs and
more importantly it provide the designer to select a module and do a "what
if" analysis of placing the module into any FPGA. As modules are placed
into the FPGAs the GUI provides two bars to indicate the pin count and gate
count usage to help keep track of these two important constraints. Another
nice feature is that when a module is selected there is a pin connection
matrix which allows the designer to readily see the number of pin
connections to other modules which aids in determining which FPGA the module
might best be placed to reduce pin count.
Let me close by saying that I've been an ASIC designer for over 10 years and
I emulated designs with Quickturn and IKOS emulation systems. I've also
spent time looking at the possibility of prototyping ASICs with FPGAs before
and this product is one of the better ones I've ever used.
- Chuck Seeley
Micron Technology
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From: Mona Chu <monac@el.nec.com>
Hi, John,
On "Altera Apex Is Flakey; How About Using FPGA Compiler II Instead?", we
are also building SOC-ASIC prototypes. We use Synplicity's Certify to
compile our designs in Verilog. Certify allows the user to partition his
design in various ways on FPGAs. This is important for a large design that
may not be able to fit into one FPGA.
I also encountered errors during compiling, but they were mainly syntax
errors, ambiguous design coding, and designs that can not be implemented
in FPGAs such as "bus holders" (which require weak/strong logic). With
modifications to the design, I don't have much problem using Synplicity's
Certify to finish my compile.
- Mona Chu
NEC
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From: Ivan-Pierre Batinic <ivan_batinic@3mts.com>
Dear John,
Synplicity offers a multi-FPGA target mapping package integrated into their
synthesis tool called "Certify", which maps a given Verilog/VHDL design
across 1 or more FPGAs. You can do an FPGA implementation of large ASIC
designs of block functional modeling with design validation. They also
offer a superset of tools integrating the Certify package with their
floor-planning tool called "Amplify'. Until recently, my experience with
Synplicity was solely w/ their original base synthesis package "Synplify".
To date, it still delivers the fastest synthesis, with the best accuracy
prior to partitioning for FPGAs.
We're newbie users of Certify. It's much more powerful than it may seem
at first glance. For example, it knows FPGA interconnection schemes
quite well -- which begs the question "What about intervening logic and/or
memory on the PCB?". We expected answers ranging from "limited to wires
only", "combinatorial logic only" to "FPGA embedded memory only", or
"handled manually as a post-map procedure" or even laughter. Instead, our
experience so far demonstrates that any intervening design realized in the
physical target proto-platform can be described in the platform's behavioral
model and merged. We can freely mix and match FPGAs, memories, and MSI
logic on our PCBs with Certify.
It's also good for design debugging. For example, assume your FPGA PCB
comes up short with its digital interconnect between two FPGAs for a given
synchronous transaction. (Let's say it was incurred by a significant design
change midstream in the validation phase, a functional block retargeted to
another FPGA for performance, or a reduction of FPGA I/O.) Certify
automatically inserts a time-multiplexed [n:m] transceiver on each FPGA, at
the available interconnection I/Os. Though it's a departure from the
original design, the intent of the design is maintained, by allowing the
PCB implementation to transparently operate normally (with respect to the
original target design's synchronous clock, the function is performed
without a hitch).
As for Synplicity's floor planner "Amplify", I have only seen demos.
- Ivan-Pierre Batinic
Third Millennium Test Solutions San Jose, CA
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From: [ One Day At A Time ]
John, keep me anonymous.
If your going to spend money on synthesis tools for you emulation project:
1. ($) Strongly recommend you try Synplify (www.synplicity.com) over FPGA
Compiler II. I don't know anyone who has actually run a real design
through both and chosen Synopsys. It works well w/ Quartus.
2. ($$$$) Have a look at Certify... from the same company. Integrates a
powerful partitioner (replication, TDM (Virtual wire) etc.)
If you don't want (or can't) spend anything:
1. You are correct that Altera synthesis doesn't support enough of the
VHDL language to be useful. If you decide you can restrict your coding
style to suit Apex (because you dont want to spend the $$) you would be
better off using Verilog. -- not recommended
2. Use DC w/ Synopsys w/ FPGA vendor libraries -- not recommended
Here is an excerpt of an email thread I had with someone wanting to know
about FPGA synthesis for emulation:
"If we get the Synopsys lib from the vendor for free, are you saying that
we can run DC directly -- and not use FPGA compiler II or FPGA express?"
Yes, but put it this way... The results are such that they are not
generally considered to be a competitor... But it's worth a try. Altera
has an app note on how to do it (i.e. the correct variables for the EDIF
writer etc.) but I think you need to ask for the library, you can't just
download it. If you can afford it, get Synplify now and amortize it over
your next few projects. (Consider the situation where on your next
project your gate count exceeds the capacity of your current FPGA w/ DC
but with Synplify it fits .... now its cheaper to buy Synplify than new
boards.)
"If we buy the tool from Synplicity, who provides the library -- is it
Synplicity or the vendor? Whats the approximate cost for Synplicity?"
There is no library per se., Synplicity writes their own mapper for each
target architecture, so you don't need one. Not sure on the price, if
you get a node locked Altera only license you are probably under 8k.
Thanks for keeping up the useful dialog on ESNUG, John.
- [ One Day At A Time ]
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