( ESNUG 339 Item 2 ) --------------------------------------------- [1/13/00]
Subject: ( ESNUG 335 #1 338 #1 ) Wall Street Curious About PKS & PhysOpt
> Anyway, I hope this info helps someone else who is out trying to make tool
> decisions. Despite my gripes, I really like the tool and plan on using it
> on all new projects. Although we haven't taped out anything with Chip
> Architect yet, "Curly" is on the fast track to go and is definitely moving
> faster than it would be without something like Chip Architect.
>
> - Jon Stahl, Principal Engineer
> Avici Systems N. Billerica, MA
From: Garo Toomajanian <gtoomajanian@dainrauscher.com>
To: Jon Stahl <jstahl@avici.com>
Jon,
I just read your ESNUG posting. I heard that you guys have started to use
Physical Compiler (PhysOpt) there at Avici in addition to Chip Architect (I
talked about this a little bit with Synopsys). Can you tell me what other
tools you looked at? Avant! Saturn? Cadence PKS? Any info regarding how
you arrived at your decision would be of interest to me.
- Garo Toomajanian, Analyst
Dain Rauscher Wessels
---- ---- ---- ---- ---- ---- ----
From: Jon Stahl <jstahl@avici.com>
To: Garo Toomajanian <gtoomajanian@dainrauscher.com>
Hi Garo,
Our decision was kind of involved.
We took a look at Cadence PKS, out at DAC, and at customer sites whom were
friends of ours, and were interested. However three things ruled Cadence
off of our list.
1.) We had a difficult time interacting with the Cadence salespeople
and pre-sales support engineers -- they had their own idea of
how the sales/eval process should go and we had ours.
2.) Cadence layout software is in flux, and doesn't currently have an
API (they got rid of SKILL and have something new coming out), or
a common database -- both of which we consider very important.
3.) It seemed unless you already owned the Cadence layout tools it was
impossible to get on the short list to look at PKS.
A final note: in it's current state PKS uses Ambit at the front end with the
Ambit Static Timing Analyzer, and Qplace at the back end with Pearl as the
Static Timing Analyzer, something we thought was a mishmash and certain to
cause timing correlation problems.
We purchased Avanti basically after eval'ing it on a few of our designs.
The Avanti routers seem to be especially efficient, but I can't tell you
much more since we haven't used it in depth yet.
I am sorry if my posting was a little confusing, but we haven't looked
at Physical Compiler yet -- only Chip Architect. We decided to purchase
Chip Architect in addition to Avanti for the reasons stated in the posting,
and due to the fact that it is easier for my designers to use than the
Avanti tools. It has more of the look and feel of DC. Avanti has a STEEP
learning curve.
I have been happy with Chip Architect except for - -as I talked about in
the posting -- the way it deals with physical/logical hierarchy (and it's
inability to write a logical netlist). I have run into more and more
problems because of it, and although I am banging on Synopsys to fix it,
I don't see a resolution in the short term.
- Jon Stahl, Principal Engineer
Avici Systems N. Billerica, MA
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