( ESNUG 337 Item 1 ) -------------------------------------------- [11/18/99]
Subject: ( ESNUG 331 #1 336 #1 ) Replies On The P&R Hierarchical/Flat War
> I've been doing P&R for years. Let me let you in on two foundry secrets.
> The first secret is that the average design today is 200 to 300 kgates.
> We tell our customers that our average design is 750 kgate to 1 million
> gates, because that's what our customers want to hear and what our
> Marketing department tells us to say. Reality is 200 to 300 kgates.
>
> - [ There's A Sucker Born Every Minute ]
From: "Gary Smith" <gary.smith@gartner.com>
Hi, John,
The hard data on this partially agrees w/ [ Sucker Born ]. Our 1999 survey
of hardware engineers in the U.S. market for ASIC design breaks out as:
24 % ######################## less than 100 k gates
22 % ###################### 100 to 249 k gates
4 % #### 250 to 499 k gates
16 % ################ 500 to 999 k gates
22 % ###################### 1,000 to 2,499 k gates
4 % #### 2,500 to 4,999 k gates
4 % #### 5,000 to 10,000 k gates
2 % ## 10,000 + k gates
Worldwide, there are about 10,000 ASIC design starts.
- Gary Smith, Senior EDA Analyst
Dataquest San Jose, CA
---- ---- ---- ---- ---- ---- ----
> Aart should give a big bonus to the slick Synopsys salesman who sold
> FlexRoute to SGI. They didn't need it.
>
> - [ There's A Sucker Born Every Minute ]
From: Pravin Madhani <pmadhani@synopsys.com>
Hi John:
I wanted to set the record straight that it was not some "slick Synopsys
salesman who sold FlexRoute" to SGI. As you know, FlexRoute technology
was developed at Everest Design Automation. SGI was a customer of Everest
*before* Everest was acquired by Synopsys and the product released at
what we now call FlexRoute. SGI was quite unhappy with their old solution
and looking for alternatives. They were very impressed with the Everest
technology and the team. Even though we were a small startup with a short
history, SGI decided to purchase and use our router. From the perspective
of Everest, as any start-up with hot technology to prove, we were also
looking to engage with design teams doing truly challenging designs. We
found that in Sam's team at SGI. I am thrilled that FlexRoute was able to
make such a difference as help "improve their transistor density by 25%".
I'll now return you to your previously scheduled technical discussion...
- Pravin Madhani, ex-CEO of Everest Design Automation, Inc.
Synopsys
---- ---- ---- ---- ---- ---- ----
> The second secret is Avanti easily does place & route on *FLAT* designs of
> 200 K instances in 24 hours. YOU DON'T HAVE TO DO ALL THAT HIERARCHICAL
> CRAP SYNOPSYS IS PUSHING!!! Sam could have intelligently partitioned his
> 750 K instance design into four parts by hand and Avanti could take it
> from there. No brainer. Kick off Avanti on 4 workstations with lots of
> CPU cycles and memory. Come back the next morning. Glue the 4 parts
> together. Your final detailed placement and routing is done. FlexRoute
> and its complicated hierarchical games are a waste of engineering time and
> money.
>
> - [ There's A Sucker Born Every Minute ]
From: "Sam Appleton" <sama@groovy.mti.sgi.com>
Hi John,
I certainly appreciate the comments, both good and bad, that ESNUG 331
generated. Most people seem to fall into two camps -- those who use
hierachial design and those who despise physical hierachy.
I'd like to respond to some of the comments made by [ There's A Sucker Born
Every Minute ]. I agree that for small 250k instance designs hierachy is
not necessary if there are no hard timing or signal integrity issues to
address. The tool (Cadence or Avanti) will cope with sizes that big, most
clock/extraction/delay calculation tools work with designs that size, and
it's generally a slam dunk. No real data management issues to contend with
either.
But as to doing flat layout on a 750k instance design - really? I am
mystified by a couple of statements
"Sam could have intelligently partitioned his 750 K instance design
into four parts by hand and Avanti could take it from there."
How do you "intelligently partition" a design into 4 pieces in the tool?
Does it magically fit together? Does Avanti support this? Cadence doesn't.
Do you arbitrary break the design along a global placement, or do you BREAK
THE DESIGN BY LOGICAL HIERACHY? If you break the design by logical
hierachy, then it certainly sounds like you're doing hierachial physical
design, and you'll have to do pin assignment, interconnect routing etc
between the pieces. Avanti must have some great magic in it. If you're
doing things by abutment, a host of other issues come up, like signals that
go between multiple blocks, signals that want to cross one partition to
get to another block, etc etc etc.
"Come back the next morning. Glue the 4 parts together. Your final
detailed placement and routing is done."
How is this magic performed? Glue the 4 parts together? How do you insert
a clock network over designs this size and then "glue" them together? How
do you deal with post-layout netlist issues (i.e. the tool modifies the
netlist for clock, scan and possibly IPO buffer insertion). How do you
deal with interconnection issues between the pieces?
I've asked people who use Avanti tools how this could be done -- they
are equally baffled.
With our experience, some things become impossible in flat designs:
o clock insertion -- do you really believe what CtGen or the equivalent
Avanti tools tell you about insertion delay and skew? They're
pre-routing results that don't mirror the actual layout results all
that well, and their parasitic estimates (which have HUGE impact on
skew) are always way off, since they're 2D estimates only. Try
extracting your clock net and SPICE'ing it -- you'll be surprised.
o signal integrity -- yes, we had buses that travelled 11mm. Cell-based
routers SUCK at routing these signals, plus you need specialized
width/spacing rules to deal with crosstalk-induced delay issues on
these lines. The meandering routes produced by cell routers on such
nets are unacceptable! They produce huge numbers of unnecessary layer
changes, and wire lengths that are far longer than the unrouted net
length. For signal integrity on the critical top trunks of the clock
net, these wires need to be routed on very wide wires over distances of
3-7mm, with special spacing characteristics to avoid signal integrity
and electromigration problems. Do cell-based routers do this at all
well? Absolutely not.
o extraction -- we could not extract a 750k instance design flat. Maybe
we weren't doing something right, or maybe we should have used
Report->SPF out of Silicon Ensemble's 2D extractor and used that? With
hierachy, we could start with a bunch of GDS2's and get to full-chip
SPF in a couple of days with a 2-1/2D extractor, incrementally change
parts of the design and re-extract in hours, and do hierachial delay
calculation. Flat layout would not allow that degree of performance at
the extraction end.
Yes, we were easily duped by the non-existent slick Everest salespeople that
called on us. They walked in, said "we have a top-level router that's
really nice, and it's for hierachial design". Instantly, we dropped all
our marbles and paid big bucks for a waste-of-money tool. We're _that_
gullible. No wonder Synopsys bought them.
> Tell Sam good review. Lots of details. Please ask him whose placement
> tools he used. He nixed Avanti and Cadence for routing, but said nothing
> about what he used for placement. Did he use Qplace, Avanti, or Chip
> Architect? Aristo? Anon. pls.
>
> - [ Party Like It's 1999 ]
Thanks for the comments from [ Party Like It's 1999 ]. For our block-level
tools, we used:
o Cadence Qplace for timing-driven placement
o Cadence Wroute for routing
Qplace and Wroute are fine for block-level stuff, mostly. Wroute doesn't
deal with wide wires or signal integrity on wires very well at all, at least
not in the incantation we used (5.1.xxx). I know Cadence/Avanti/Synopsys
all have new cell placement/IPO/placement-based-synthesis technology that
we'd really like to evaluate.
FlexRoute is a great tool if you're doing large designs and you're concerned
about things like route quality, chip density, timing convergence, and
clock/signal integrity. If your chip is small and these issues don't
concern you greatly, and it fits easily into the space of a P&R tools'
capacity, then flat is probably a better way to go.
- Sam Appleton
SGI Mountain View, CA
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