( ESNUG 329 Item 8 ) --------------------------------------------- [9/22/99]
From: "Paul Zimmer" <paul.zimmer@cerent.com>
Subject: ( ESNUG 315 #8 ) Screwy Some/All "*" In PrimeTime Timing Reports
John,
I just got bit AGAIN by this problem, so I want to blow off some steam by
complaining about it publicly AGAIN. Both DesignTime and PrimeTime use a
"*" in the timing report to indicate:
"some or all of the timing is backannotated"
The problem is, there's a HUGE difference between SOME of the timing being
backannotated and ALL the timing being backannotated.
After I read in the SDF, I expect ALL the timing to be backannotated, and I
want to *know* if something isn't. Why can't Synopsys use "*" for the
current "some or all", but use something like "+" for ALL.
The particular problem that tripped me up might interest ESNUG readers
as well. In the Verilog world, there exists a net that connects the
top level module ports (your pins) to the pad input/output/io pins.
I guess this corresponds physically to the bond wire.
Anyway, the timing on this net should be zero. Unfortunately, most vendor
SDF files don't annotate this net, so DT/PT will estimate the delay using
wireload models. If you do a report using report_timing without any special
switches, this delay will hide quietly inside the number reported for the
pad timing, and you'll never know. Since SOME of this number is from the
SDF (the timing through the pad), you'll see a nice, healthy-looking "*"
next to the number in the report, and you may spend ages trying to fix the
timing on a path that's actually OK.
If, however, you use the "-input_pins" switch, the two pieces will be
separated and you'll see the estimated timing of this net without the
"*" next to it.
Some ways around this problem:
1) Force the wireload model to be low or non-existent.
2) Do a "set_annotated_delay 0.0 -net..." across this net. This is what
I was doing, but it wasn't working correctly because there was a level
of hierarchy in the way.
3) Do "set_resistance 0.0" on this net, and maybe a set_load 0.0 as well.
4) Hack the SDF file (Perl to the rescue!) to put these paths in.
5) Beat on your vendor to fix their tools to put this number in the SDF.
6) Use some magic DesignTime/PrimeTime switch that I don't know about???
These workarounds are fine for the specific problem of hidden net delays on
input pins, but only Synopsys can fix the fundamental problem of unannotated
timing hiding behind annotated timing!
"Some or all" indeed!
- Paul Zimmer
Cerent (uh, I now mean "Cisco")
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