( ESNUG 316 Item 3 ) ----------------------------------------------- [4/8/99]
From: NUKALA RAVIKANTH <ravikanth@msemi.com>
Subject: Transmission Gates In Our Libs Ruin Our Fault coverage !!!
Hello, John,
We're facing a Design-For-Test problem.
In our library we have some MUXes made of transmission gates. We manually
instantiate these cells in our datapath for fast timing. For example, we
have a cell DSEL4, which has 4 i/ps, 4 selects and 1 output. We always have
a decoder in front of such MUXes for the select lines. (Actually in our
design, the selects for the MUXes are not decoded. So using a decoder, we
generate fully decoded selects which drive the pass gate selects.)
So we assure that, ONE and ONLY ONE of the selects is ON at any given time.
Now my problem is the stuck-at faults at the select pins of these pass gates
are untestable. So, can I do something to make them testable??? I would
also like to know the best way to model them in Synopsys. Right now they're
modelled as bufif.
We have many such cells in the design and the fault coverage reduction is
required is huge. So, we can't neglect them.
Please, help!!!
- Nukala Ravikanth
Meridian semiconductor
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