( ESNUG 261 Item 1 ) -------------------------------------------- [5/22/97]
From: rajen@jaxom.eng.pko.dec.com ( Rajen Ramchandani )
Subject: WARNING: Synopsys "bk" DesignWare Adders Are BROKEN!!!!
Hi John,
In the new release of Synopsys 1997.01, the designware foundation library has
new architectures for adders called "bk". I guess the synonym means Broken.
From an Implementation Report of the design:
===========================================================================
| | | Current | Set |
| Cell | Module | Implementation | Implementation |
===========================================================================
| FsDerivativeChannel_return/add_172 | DW01_add | bk | |
| FsDerivativeChannel_return/add_173 | DW01_add | bk | |
| U1494 | DW01_add | clf | |
===========================================================================
We found that these adders were not functioning as advertised and 4 MSB bits
of the 52 bit adder were producing incorrect output results. Actually
Chryalis symbolic verifier found this out for us. <*COMMERCIAL PLUG*>
Simulation also showed the BUG. Synopsys is aware of the problem and is
working on fixing it. In the meantime the workaround suggested by Synopsys
is not to use the parts.
So if you want to save your sanity include the following to your script
set_dont_use {dw01.sldb/DW01_*/bk}
Also if your design contains any of these bk adders then make sure you
verify the gate_level netlist thoroughly or formally verify the design.
To check if your design contains any of these parts do a
read -f db YOUR_DESIGN.db
report_resources
and check the implementations.
- Rajen Ramchandani
Digital Equipment Corporation
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