( ESNUG 239 Item 4 ) ---------------------------------------------- [4/11/96]
From: oren@waterloo.hp.com (Oren Rubinstein)
Subject: "write_timing -f sdf -con verilog" w/ "change_names" Doesn't Work!
Hello, John,
In order to accomodate some layout tools, we restrict the names to 32
characters, by running change_names. As a result of the truncation, some
cells and nets, that originally had different names, end up with the same
name. I did a "write -hier -f verilog -o filename" and Synopsys appends a
"_inst" to the cells that have the same name as nets. (For example, I get
"zippy" for the net and "zippy_inst" for the cell.)
But this is done by the write command, not by change_names, and as a
result, the names are not updated in the .db!!!
I do "write_timing -format sdf -context verilog" to generate back-annotation
delays. Because the delays are generated from the .db, I get mismatches in
the SDF file!!!
The workarond is to remove all the designs, read the Verilog netlist back in,
and generate the SDF from that -- but in the process I lose all sorts of
useful data that is present only in the .db (for instance, the wire load
model to be used for each sub-block.)
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
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