( Post 82 Item 2 ) --------------------------------------------------------
From: jaa@SU59D.ess.harris.com (John Auer)
Subject: RE: Synopsys does not understand invalid gate input states
>> jaa@mongoose.ess.harris.com (john auer) writes:
>>
>> Did Synopsys have any trouble making the synthetic library? (install_synlib)
>> In my experience, "unable to map" reflects an out-of-date synthetic library
>> (library.mod file). Just a thought...
> cindy@ca45.zoran.hellnet.org (Cindy Eisner) writes:
>
> sorry i did not make myself clear here. what i meant was that when i
> defined a tri-state buffer with inputs required to be opposite, using
> the pin_opposite attribute, i got the "unable to map" error message.
> otherwise, the tri-state buffers were mapped fine.
jaa@mongoose.ess.harris.com (john auer) writes:
Agreed, I was able to reproduce this behavior in VHDL. Something is
broken. I'll report this as a bug. In the final analysis, however,
this is a different bug than the one I originally reported. This "new"
bug is a breakdown in the synthesis process. The original bug concerned
Synopsys not understanding that certain inputs MUST always be opposites
of one another. This lack of knowledge on the tool's part causes a
breakdown in both the optimization and synthesis processes;
non-complimentary logic will be synthesized, and complimentary logic
(from non-HDL sources) is sometimes optimized into a non-complimentary
result.
Even when Synopsys fixes the "unable to map" bug, the original problem
will remain--complimentary logic will be synthesized, but optimization
will result in a non-complimentary result.
John Auer
Harris GASD
jaa@mongoose.ess.harris.com
OK to use name
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