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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2006"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Every year when I go to DAC a small army of people ask me the extremely
predictable questions of "What's hot at this year's DAC?" and "What are
you going to look at, John?". So instead of having to repeat this same
conversation over and over again while I'm at DAC for 5 days, I've decided
to share My Cheesy Must See List for DAC 2006 with the DeepChip readers.
(You might want to print out a hard copy of this to use as an unofficial
guide to the DAC floor next week.)
1.) Athena Design (booth 3033) will preview Milos, a new meta routing
optimization system not unlike the old PDoptimizer from ReShape.
Milos allows designers to incrementally "analyze-optimize-fix" on
the fly on multiple constraints. For example, using their own
parasitics, Milos automatically optimizes set-up and hold for
multiple corners and modes simultaneously. (Athena uses the
Parallax timing engine.) Milos is distributed multi-processing
with their own proprietary partitioning & tiling algorithms. It's
a "meta" tool; it runs Blast Fusion, NanoRoute, Astro, Pulsic,
Star-RC, Fire&Ice QX, PrimeTime, Design Compiler and even the olde
defunct SDS K-Route for you to converge timing. I know Toshiba is
using Milos. Ask for John Murphy. Freebie: kaleidoscope top
Magma (booth 4173), who bought the remains of ReShape, is showing
a similar tool called "Talus" with their unsubstantiated marketing
claim that Talus will "complete any chip in 2 days or less" on
"chips of 50 million gates". I know NEC is at least testing Talus.
Ask for Behrooz Zahiri. Freebie: a 5 way USB adaptor
2.) Some of the biggest news at this DAC is that Sierra DA (booth 2128)
added a router to its placer offering -- that is, it's no longer a
company looking to be bought out by Cadence, instead it just made
itself the next Magma. Of course, with the buzzwords du jour being
DFM, their Olympus OptRoute is a litho-aware detailed router that
cleans up jogs, notches, corner bridging & pinching yield gotchas.
With hooks into Calibre LFD, Olympus can read in and automatically
fix the hotspots it found. Sierra claims these fixes are timing
aware (setup, hold, MCMM, etc.) It's rumored ST, ATI, and TI are
using them. Ask for Sudhakar Jilla. Freebie: faux leather folder
3.) In the hunt for margin, I'll be looking at the STATISTICAL static
timing analysis tools from Extreme DA (booth 307). Don't get lost
in all the DFM bullshit in their pitch; cut through it and you'll
see that you get a LOT of free margin that plain olde STATIC timing
analysis pessimism leaves on the floor. Big news for Extreme DA is
that UMC said it'll make their SSTA actually work at 90 and 65 nm.
Ask for Mustafa Celik. Freebie: "We are too poor for freebies."
Synopsys (booth 3773) is the monopoly player in the olde static
timing analysis biz with PrimeTime, and last year they talked about
adding statistical in. This year, I've heard they actually have it
in production. What's unexpected was that they made Star-RCXT also
statistical to work with the new PrimeTime SSTA. I wouldn't be
surprized if it works only with IC Compiler and not Astro. Ask for
Robert Hoogenstryd. And, like last year, Magma (booth 4173) is
re-iterating its Mojave Quartz SSTA and has TSMC backing them at
65 nm. Ask for Jay Abraham. Oh, yea, and IBM (booth 3310) has
had SSTA for a while; but EinsTimer works only on IBM fabbed chips.
For libs, I'd see Altos DA (booth 2300) because their "Variety"
tool creates SSTA libs from your SPICE models and cell subcircuits.
Ask for Jim McCanny. Freebie: tins of Altoids mints. Also the old
Silicon Metrics guys at Magma (booth 4173) make SSTA libs. Ask for
Steven King. Freebie: a pen that lights up or a 5 way USB adaptor
4.) As some unfinished business from DAC 2005, this year I plan to
see Axiom DA (booth 1200) because of what Cliff Cummings had said:
"To me, Axiom was interesting because they have a distributed
simulator. They're the old @HDL. They're going up against
the big boys like VCS, NC-Sim, and ModelSim. It dices up your
run across eight 64-bit Opteron processors. The Axiom tool
automatically figures out where your simulation partitions
should be, spreads the runs across those 8 CPUs, and then
pulls it all back together. An end user has to do nothing
but watch his simulations run much faster."
- http://www.deepchip.com/gadfly/gad062905.html
Ask for Hamed Emami. Freebie: T-shirt. Mentor (booth 928) is
also showing its repackaged version of ModelSim plus 0-in which
they're now calling "Questa 6.2". It seems to have all sorts of
cheery features that Synopsys and Cadence also have. Ask for
Stephen Bailey. Synopsys (booth 3773) this year seems obsessed
with talking up how "hot, Hot, HOT!" System Verilog supposedly
is and they'll be pitching all the happy links VCS & Magellan
has to it. Ask for Tom Borgstrom. Freebie: 3-in-1 color pens
5.) I have a source who said Synopsys (booth 3773) will be showing for
DFM "Project Athena" (not to be confused w/ Athena Design.) Rumor
has that it's a standalone design yield analysis tool that mimics
CMP, CAA, and litho compliance for P&R and DRC/LVS guys. What's
funky is that you use it in a Magma, Cadence, or Mentor flow; it's
a standalone tool. The Synopsys upside is Project Athena has hooks
into IC Compiler so it can *automatically* repair the DFM gotchas
it found. Ask for Rahul Kapoor. Freebie: pen/laser pointer
6.) The big news for Mentor (booth 928) is its new Calibre nmDRC tool
which is the super faster flavor of Calibre. Mentor claims they
can get 1-to-2 hour runtimes for DRC checks that before used to
take overnight; because nmDRC can run on 40 CPU clusters. This
counters the false JarJar Binks threat Magma Mojave (booth 4173)
had posed to Calibre last year in ELSE 06 #17 and ELSE 06 #18.
For Calibre nmDRC, ask for Michael White or Tony Nicoli. For
Magma Mojave Quartz DRC/LVS, ask for Dwayne Burek.
On DAC Tuesday from 12:00 to 1:30 in Room 102 of Moscone Center,
the Mentor folks are sponsoring a lunch with Adam and Jamie of
MythBusters -- you know, those guys on the Discovery Channel who
are always building weird things to test urban legends? I hear
you have to go early to Mentor (booth 928) to get tickets.
7.) As a new product, I'll be at Apache (booth 1906) to see their new
Sahara-PTE which does power-electro-thermal analysis of chips to
measure the temperature impact on leakage, timing, reliability, and
voltage drop. It was hinted at in ESNUG 455 #9. (And I'm curious
how it differs from Gradient FireBolt in booth 2328.) At Apache
ask for Yukari Chin. At Gradient ask for Rajit Chandra.
8.) On the Cadence front (booth 1228), I heard they'll be pitching
their new Cadence Precision Router (CPR), the brainchild of the
semi-secretive Catena group. CPR is supposed to be the eventual
successor to CCT IC Craftsman a.k.a. Virtuoso CCAR. I've heard
that IBM is testing CPR along with the Cadence Chip Optimizer at
65 and 45 nm. Ask for Wilbur Luo or Craig Thompson.
Good old Joe Costello is giving the DAC Monday keynote from 2:00
to 3:00 in the Gateway Ballroom. Might as well shut down the rest
of the show for that 1 hour, cause everyone's going to be there!
9.) On a personal note, Richard Goering is interviewing me on video
about the best/worst DAC freebies. Since it's humanly impossible
for one man to go to all 254 booths easily, I've asked the EDA
vendors to bring 1 of their "common" freebies to the UMC exhibit
(booth 3339) at 4:30 on DAC Monday. If you want to see all of
this year's DAC swag, be at UMC booth 3339 at 4:30 Monday!
10.) The real fight I see in the much ballyhooed ESL niche boils down to
Forte SystemC vs. Mentor ANSI C. At Forte (booth 1428), they'll be
showing their Cynthesizer that now supposedly does "TLM synthesis"
which they claim is now TLM ANSI C => SystemC => RTL => gates. Ask
for Brett Cline. Freebie: weird computer monitor sweepers. At
Mentor (booth 928) their new Catapult SL does pure ANSI C++ => RTL
and it supposedly has some sort of new hierarchy "channels" in it.
Ask for Shawn McCloud or Anil Khanna. Freebie: one-armed backpack.
I'll also go to Summit Design (booth 1028) to check out their Vista
debugger for TLMs, SystemC and C/C++. They also have Panorama,
some sort of architectural ESL tool that Gary Smith is supposedly
all excited about. Ask for Zvika Amir or Emil Girczyc.
11.) After Synopsys aquired Virtio, I figure it's best to go check out
CoWare (booth 3173) to see their VPD tool -- I've heard from some
sources that it's very similar to what Virtio has. (Maybe there's
something to this SW virtual prototyping stuff, but I hope not.
I'm a chip designer, dammit!) Ask for Drew Taussig or Vinh Du.
12.) For low power, you should check out the gate optimization rivals
Zenasis (booth 3027) and Prolific (both 3563) -- they both have new
stuff targeting leakage power. Also see Golden Gate (booth 3332)
for its unusual "rewiring" fix and Azuro (booth 1928) for its clock
tweaking approach to reducing power. And don't forget to look at
the grand pappy of low power design, Sequence (booth 1614) with
it's psuedo-"new" PowerTheater 65.
These are all mostly backendish P&R types of power reducers; check
out ChipVision (booth 1314) and newbie ArchPro DA (booth 3072) if
you seek frontendish RTL "architectural" style power reduction.
13.) Because their CEOs were the first to clearly describe (in a non-
hype, no-self-serving-BS manner) the DFM landscape in ESNUG 453,
of course I'll be seeing the ClearShape and Aprio people at this
DAC. What's interesting is that since that ESNUG, ClearShape has
gone on to win quite a few DFM "victories". For 65 nm, TSMC chose
to endorse ClearShape and Ponte along with the usual Big 4. And
again, for 65 nm, IBM, Samsung, and Chartered all got together and
also endorsed ClearShape and Ponte along with the usual Big 4. To
top it off, ClearShape InShape had UMC and an anon user do the
first hands-on review of any DFM tool anywhere in ELSE 06 #22.
For Aprio, they'll show at this DAC the first results of its work
with KLA-Tencor; a version of Aprio's litho repair tool, Halo-Fix,
running on KLA's accelerated DesignScan platform. In addition,
it was just announced that Aprio Halo-Quest now has hooks into the
Pyxis DFM router. At ClearShape (booth 2311) ask for Atul Sharan.
At Ponte (booth 2204) ask for Nitin Deo. At Aprio (booth 3072)
ask for Mike Gianfagna. At Pyxis (booth 2323) ask for Naeem Zafar.
14.) Normally I wouldn't pay that much attention to the Fishtail vs.
Blue Pearl battle because of ELSE 06 #16, but since I've heard
that Cadence and Averant now have similar false-path/multi-cycle
path detectors, it might be a new game. The Cadence (booth 1228)
tool is called Conformal Constraint Designer; ask for Jason Ware.
The Averant (booth 1310) tool is SolidTC; ask for Larry Lapides.
The olde guard is FishTail (booth 4357); ask for Ajay Daga. And
Blue Pearl (booth 2306) was the tool with no known users; ask for
Ellis Smith. Ellis says this year "we will have a great DAC."
15.) One of my readers emailed to ask me if I was going to attend the
DAC Synopsys IC Compiler lunch on Monday 11:30 - 1:30 in "Salon 8"
of the Marriott. Seeing as I was not told about this lunch, it's
my guess there are some Synopsys employees still pissed at me for
calling IC Compiler a "Potemkin village" tool in SNUG 05 #14. If
you go to this lunch, please take lots of notes and send them to
me. I'm dying to know what Synopsys is trying to hide here. You
say you don't have a ticket? No problem! Here's one. :)
http://www.deepchip.com/images/snps_dac06_tix.html
P.S. And if you get caught, you don't know me & I don't know you!
16.) I also heard that Cadence (booth 1228) is showing some weird DFM
functionality they've put into Encounter Test. It supposedly uses
a set of diagnostics engines, a SQL database, statistical analysis
and a new physical design browser so users can examine physical
locations in failing die across multiple wafer lots to highlight
what cell type, net, metal layer or silicon structure is causing
the most yield loss. A "test" tool doing yield?! -- I didn't
see that coming! Ask for Mike Vachon. In that same vein, I'll be
pestering Dale Pollek of ChipMD (booth 3028) to see what he's done
since he's made so much hoohaw about "yield" the past few years.
17.) Recently a few users yarped about Knowlent (booth 3955) Opal in
ESNUG 456 #5. I'll probably give it a look-see to better grasp
what their Opal automatic electrical compliance is about. I'll
probably do the same at Rio DA (booth 3155) for their off-the-wall
tool which does chip/package co-design because of ESNUG 454 #6.
18.) For the Synplicity vs. Mentor FPGA wars, I'll see Andy Haines at
Synplicity (booth 3373) about his collection FPGA tools and
then I'll walk over to Mentor Precision (booth 928) to see what
Juergen Jaeger and Daniel Platzker have to compare. The Synplicity
freebie: t-shirts & mints; the Mentor Precision freebie: USB lamp
19.) Oddly, the bug hunter Jasper DA (1628) giving away its GamePlan
tool. Yup, its a free download. Not sure how one makes money that
way, but who am I to question them? The Real Intent (booth 706)
will be introducing "Conquest" and "Ascent", two new formal tools
which are supposed to do great paradoxical things. (What the Hell
that means, I haven't a clue.)
20.) For RTL synthesis, I'll obviously be at Synopsys (booth 3773) to
inquire about the supposedly "new" Topographical DC mentioned in
ESNUG 456 #12 and ESNUG 456 #13. I'll be harrassing Gal Hasson
over whether or not Topo DC is just repackaged PhysOpt. And at
Cadence (booth 1228), I'll be harassing Jack Marshall over how his
Get2chips RTL Compiler is trying to catch up with DC. :)
21.) For debug environments, I'll check out Novas (booth 3573) for its
Siloti "visibility enhancement" tool which apparently eliminates
the need to dump all but a small subset of a design's signals
during simulation and emulation. This means you don't need to do
full dumps or guess at the subset to dump; it figures that out for
you. "Siloti recreates the rest of the signal data on the fly
during debug and maps your gate-level signals to the RTL level."
Or so the Novas folks claim. Ask for Scott Sandler.
22.) In the Thankless Task Department, I'll be at IC Manage (booth 308)
to look at their Project Manager tool (based on the Perforce SCM
system) which does distributed design data management. It can do
single site or allow remote sites across distant networks to
collaborate in real time. What draws me to IC Mange is that they
know EDA -- and that they're a small start-up that believes in
FANATICAL support -- a big, BIG plus when you need it the most.
I've heard that Nvidia, ATI, Rambus, and National are using them.
Ask for Shiv Sikand or Dean Drako. Freebie: chocolate cars
23.) In analog/RF, I'll be at Berkeley DA (booth 1924) because I heard
that Paul "Pi" Estrada went there. He's one the people I watch in
EDA because of his track record. From what I've heard, Berkeley's
branching out from the tiny PLL noise market and is jumping into
the full SPICE biz (i.e. taking on Spectre and HSPICE.) Rumor has
it they're something like 0.0001% accurate, can converge big ass
1 million element circuits and supposedly ballparks 10x faster.
Ask for Pi Estrada. Freebie: cheap BDA pens for useless digital
folk; nice BDA polo shirts for the interesting analog folk.
Mentor (booth 928) will introduce a new fast-SPICE tool. They're
integrating ADiT, from its EverCAD acquisition, into their ADVance
MS mixed-signal tool. ADiT had an emphasis on AMS designs, with
improved partitioning and modeling algorithms. Ask for Dan Lee.
Also in the AMS game is the newbie Lynguent (booth 2214), which has
a GUI-based tool, ModLyng, which models AMS designs. You can read
in Verilog-A, Verilog-AMS, VHDL-AMS, or MAST and it converts it all
to graphics which you can tweak at will. It also appears to graph
the curves of the static analysis equations of your circuit. Ask
for Martin Vlach or Andrew Levy. Freebie: Czech spinning tops
The aptly named newbie Helic (booth 2115) will show its VeloceRF
spiral inductor synthesis and modeling tool (a plug-in to Cadence
Virtuoso.) The tool now features a fast RLCK extraction engine.
Ask for Nikolas Provatas. Freebie: yummy Greek food!
24.) Denali (booth 3851) -- yea, they have a monopoly on memory models.
Who cares? I'm there to pester Kevin Silver so I can get a ticket
to their infamous DAC party. "Come on, Kevin, pleeeease...."
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there and that's me! :)
- John Cooley
ESNUG/DeepChip.com Holliston, MA
P.S. And *after* DAC if you found this floor guide useful, please email me.
It's a LOT work at a VERY crazy time of year to put together.
-----
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
or (508) 429-4357.
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