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\ - / INDUSTRY GADFLY: "I Sense A Tremor In The Force"
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by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Like any web publisher, after I send out an email blast to the DeepChip
mailing list, I track how the technical letters (items) ranked against
each other within the same ESNUG post. (It's a great way to see what
readers are interested in and what they're not interested in.) Here below
ESNUG 476 is an excellent example of a typical ESNUG post with its items
ranked in decending order of reader pageviews:
( ESNUG 476 Subjects ) ---------------------------------- [10/29/08]
Item 1: Boatload of users talk up Mentor Sierra MCMM P&R
Item 6: How Apache slowly crushes Cadence VoltageStorm
Item 8: Mentor TestKompress and EDT kicks ass in China
Item 4: Magma Titan (Sabio) analog migration ain't 1 day
Item 2: Equivalance problem with DW02_tree in Formality
Item 5: We use an EVE ZeBu-XXL 8 along with Bluespec BSV
* - Item 9: George is wrong; SystemC/C/C++ tools play nicely
Item 10: Packing guy asks on wirebond to flip chip EDA tools
Item 7: IC Manage only one to pass this user ambush test
The item about Mentor Sierra got the most reader pageviews. The Apache vs.
Cadence item was the second most popular in reader pageviews, etc. Or, at
the bottom, the Packing guy's question and the IC Manage items had the
two lowest reader pageview counts.
Notice the "* -" above. That's the never-ending battle between Brett Cline
of Forte and George Harper of Bluespec have about SystemC/C/C++/Bluespec.
They've been at it for years, so the fact that they were 7th in reader
interest in ESNUG 476 back in October 2008 was quite normal.
Below are the top four items of the past 7 months of ESNUG's. Notice how
once that "first US-based C/C++ chip design" story broke, reader interest
in SystemC/C/C++/Bluespec (again marked with "* -") suddenly jumped!
( ESNUG 477 Subjects ) ---------------------------------- [11/20/08]
Item 6: We dumped PrimeTime (& Cadence ETS) for GoldTime
* - Item 3: The first US-based C/C++ chip design I've seen
* - Item 10: Bluespec is the "biggest lie in ESL space"
Item 2: Seven benchmarks of PrimeTime 2007.12 vs 2007.06
( ESNUG 478 Subjects ) ---------------------------------- [12/18/08]
Item 2: Cadence tweaks RTL Compiler Physical for better P&R
* - Item 8: Power Opto and Linting in CatapultC and Spyglass
* - Item 9: Using Calypto SLEC in a CatapultC design flow
Item 3: A user tutorial on how to use IC Manage on projects
( ESNUG 479 Subjects ) ---------------------------------- [02/05/09]
* - Item 4: "2 biggest reasons to use High Level Synthesis?"
Item 2: User Benchmark of PrimeTime vs. GoldTime for STA
Item 7: Synopsys ICC, Magma Talus, Sierra, Atoptech
Item 6: Magma Talus is a big step up from BlastFusion
( ESNUG 480 Subjects ) ---------------------------------- [04/02/09]
* - Item 2: Synfora PICO vs. CatapultC/Cynthesizer/CtoSilicon
Item 4: TSMC confirms Magma Titan 2nd chip is mins vs. weeks
* - Item 5: A user's first look at Cadence C-to-Silicon
* - Item 10: "Working with Bluespec is faster than with RTL"
( ESNUG 481 Subjects ) ---------------------------------- [05/08/09]
Item 6: Cadence Spectre vs Magma FineSim benchmark
* - Item 10: Mentor tells Synfora to get facts straight
Item 2: Jasper vs. Magellan, IFV, 0-In, RealIntent, IBM
* - Item 7: A 2nd US-based C synthesis design reports in
( ESNUG 482 Subjects ) ---------------------------------- [06/30/09]
* - Item 6: Wow! Microsoft uses AutoESL's C synthesis to speed SW
* - Item 4: A second customer looks at Cadence C-to-Silicon
Item 3: Calibre nmDRC benchmarks 6X faster than Hercules
Item 9: GlassBoxes, benchmarks, Talus Design (Blast Create II)
Wow! Talk about tipping points! From that one US hands-on CatapultC user
story, 12 out of the 24 most read items in the past 7 months worth of
ESNUGs were now about SystemC/C/C++/Bluespec.
Where it'd normally be Talus, Calibre, PrimeTime, Apache, Jasper, and EVE
Zebu dominating -- for 50% of my top items it's now Mentor CatapultC, Forte
Cynthesizer, Synfora PICO, Cadence C-to-Silicon, ANSI C vs. C++ vs. SystemC,
Bluespec, and wow-even-Microsoft-uses-AutoESL's-AutoPilot discussion.
---- ---- ---- ---- ---- ---- ----
I think it's important to know that this data is NOT pointing to a mass
movement towards C for general chip design -- what it is pointing to is that
chip designers are now very interested in C synthesis tools (i.e. EDA tools
that read in C/C++/SystemC source and synthesize out Verilog/VHDL RTL.)
Why? I don't know. Are designers now going off into the la-la land of
"higher levels of abstraction" in C? I don't know, but I doubt it. All
of these items are on the PRACTICAL aspects of synthesizing C/C++/SystemC
into Verilog/VHDL RTL only -- not that la-la fruity virtual protyping crap
nor vague architect's workbenches nor target compilers nor wackadoodle
co-simulators nor mystery model BS -- they're purely the nuts-and-bolts of
making C/C++/SystemC source code into RTL (C synthesis) AND NOTHING MORE!
The only other question that this data can answer is: "In the eyes of users
(and not EDA company marketeers) who are today's C synthesis players?"
That's easy. Let the users themselves answer.
As far back as the late 1990's, the trial balloon of using C synthesis for
non-experimental design had been repeatedly shot down by users until 2002,
when Forte finally wooed a few supporters from the large laughing crowd:
http://www.deepchip.com/items/dac02-03.html
and a year later user support for Forte had firmed up in:
http://www.deepchip.com/items/dac03-06.html
By DAC 2004, Mentor appeared equally with Forte on the user radar screen:
http://www.deepchip.com/items/dac04-03.html
http://www.deepchip.com/items/dac04-02.html
And they've been neck-and-neck ever since then:
http://www.deepchip.com/items/else06-06.html
http://www.deepchip.com/items/else06-07.html
http://www.deepchip.com/items/0475-01.html
Mind you, these Forte vs. Mentor letters were from a few early C synthesis
users and demo viewers sharing their impressions. When published, these
letters would garner some passing curiousity pageviews by the mainstream
designers -- but not much more than that.
---- ---- ---- ---- ---- ---- ----
But now over the past 7 months, I've read the following number of first-hand
detailed user reviews for the following C synthesis tools:
Mentor CatapultC : : ############ 4 confirmed users
Cadence C-to-Silicon : : ###### 2 confirmed users
AutoESL AutoPilot : : ### 1 confirmed user
Synfora PICO : : ### 1 confirmed user
More importantly these C synthesis user letters are now getting MAJOR repeat
interest from the mainstream designers that they didn't get before.
---- ---- ---- ---- ---- ---- ----
So long story short, this tremor I sense in the Force has four parts:
1.) For the past 7 months 50% of DeepChip's top pageviews show mainstream
users are now very curious about practical C synthesis tools.
2.) C synth is not just Forte Cynthesizer and Mentor CatapultC any more;
it's about Synfora, AutoESL, and Cadence C-to-Silicon, too.
3.) There's now some US companies using C synthesis for production; it's
not just experimental nor is it just Japan and Europe any more.
4.) And for some inexplicable reason, Synopsys, the dreaded Microsoft of
EDA, is nowhere to be seen in this space -- yet SNPS' core business
for the past 23 years has been (you guessed it!) synthesis! Huh?
How this tremor in the Force will play out for chip design in the long run,
I don't know. I just know that it's here now.
- John Cooley
DeepChip.com Holliston, MA
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John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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