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\ - / INDUSTRY GADFLY: "My post-DAC debriefing with Pallab and Cliff"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Over the past two weeks, Cliff Cummings, Pallab Chatterjee and I have been
comparing notes of what we saw at the recent DAC in Anaheim. On top of that,
I've been doing a little snooping on my own, too. Here's what we found.
1. Who'd of thunk DAC attendance numbers would be a source of intrigue in
the EDA industry? Well, it was. The Big Two (Cadence and Synopsys)
have made it no secret that they want to do their big customer pushes
at their user group meetings. And when both EEdesign.com and EDN.com
initially reported that DAC attendance was "light" this year, it made
the Big Two look good. The intrigue was that now, two weeks later, we
have the actual attendance numbers:
DAC 2004 DAC 2005 % change
Total Registered Attendees: 5,961 6,104 +2.4%
Total Exhibitor Staff: 4,419 4,189 -5.2%
There were a few less exhibitors there, but the number of buyers was
actually flat or slighty up. So why the DAC-is-Doomed stories?
The other bit of intrigue around this is that this year the Cadence
booth was the same size as the Aldec booth. No surprises there; this
was predicted. What's in question was that for a good part of DAC,
Cadence had a constant number of staff people on the 2nd floor of the
nearby Hilton holding "Cadence" signs next to the unloading escalators.
The rumor mill went nuts with claims that Cadence was siphoning
customers off the DAC floor (a big no-no!) for these Hilton meetings.
It might be that the DAC Exhibitor Staff was actually *up* this year,
but no one got to count the hidden Cadence Hilton crew in the stats!
"I don't understand why they were saying DAC attendance was light this
year," said Andrew Yang, CEO of Apache. "We had 357 customers come to
our suite demos, up 26% over last year. To us, this was a good DAC.
We're especially proud that 141 of them came to see our new PsiWinder
tool. It's our expansion of Redhawk into SI."
2. I found out Synopsys has a project code named "Mongoose" that targets
statistical timing for both PrimeTime and Star-RCXT. (Yes, they're
doing statistical extraction, too.) It's supposed to take effect in
65 nm and go mainstream in 45 nm. Sony, Samsung, ST, and AMCC saw it
at DAC. And don't be fooled by that "Variation Aware" bullshit; it's
just Synopsys marketingspeak for "statistical". I got a good chuckle
out of their Mongoose name, though. In India, the mongoose is the only
animal which can kill cobras. (You know, as in Magma Cobra.)
3. Cliff: "With Novas DeBussy vs. Veritools Undertow, each of them said
they're better than the other. Bob of Veritools says his Undertow runs
100,000 times faster and has 100,000 times more capacity than DeBussy
or VirSim. Novas wouldn't say anything bad about Veritools, though.
Brett Cline of Forte said their customers ask for DeBussy integration,
but never ask for Veritools integration."
4. Pallab: "There's an IP timebomb lurking in the DFM/DFY space. All
these new solutions heavily tweak your design to the point where
there's a good question of who now owns the IP and who's now
responsible for the IP. Who do you complain to when the IP isn't
working right? I talked to 46 EDA vendors who modify IP and not one
of them would address this issue."
5. On a personal note, after I wrote about Mike Fister, CEO of Cadence,
being the reclusive Howard Hughes of EDA, I had a lot of people at DAC
ask if I finally got to talk to him. You know, "What did Fister say to
you about your comments?" I never got to see him. Mike was a no-show
at the Gary Smith Dataquest DAC kickoff and again a no-show at the RBC
Capital DAC kick-off. It's weird. At his level, Mike's job is one
half to make the big decisions and the other half to promote his big
decisions. Even the Presidents of the United States do this. But
not our Mikey. At the airport I bumped into an IDM customer of Cadence
and he said they often get Ray Bingham and Ted Vucurevich visits, but
have never once had a Mike Fister visit. "That dog don't hunt."
[ CORRECTION: After reading that recent Forbes interview with Fister on
how he loves (I'm *not* making this up) Armani suits, very dry
Grey Goose martinis "with blue cheese olives if you got'em!", and
"I have a quite a collection of shoes, maybe 30 pairs. My
favorites are Italian -- I like Testoni and Ferragamo. They
could be wingtips or loafers, crocodile or alligator. I think
a man's shoes should match his outfits just like a woman's.
If you can't be good, at least you can look good!"
I realized my closing comment of "that dog don't hunt" was incorrect
here. It should have read "That poodle don't hunt." Sorry. - John ]
6. Now for a public confession. For all these years, I had always thought
of TenSilica as being a sad American knock-off of ARM, sort of a "me,
too" IP company. It was at this DAC where I finally fully grasped that
they are a *configurable* *customizable* microprocessor company. That
is, lets say you have C code for a 32-bit RISC processor which runs
and/or defines a printer or a DVD player or a Gameboy or whatever.
TenSilica takes that C code and builds a custom processor which is tuned
for that specific C code. (This differs from behavioral synthesis
because you're not stuck working with a synthesizable subset of C.) The
key here is that your TenSilica core is optimized for your C code; yea,
it'll still run any C code, but it's *optimized* for your C code. Also,
the TenSilica guys give you a C compiler, an assembler, a debugger, and
an instruction set simulator tailored to your custom core. They claim
that they can deliver the whole shooting match in under 2 hours. I
didn't quite get this until I saw them at this last DAC.
The TenSilica people happily reported that they had 1,555 visitors to
their DAC booth this year, up 58% over last year's 984 visitors.
7. On the subject of ARM, when I stumbled by the Synopsys booth this year,
I saw they had some sort of extra "partners" booth next door yarping
about how touchy-feely close Synopsys was with ARM and TSMC.
I ran into John Chilton, the Synopsys IP Grand Poohbah, and he claimed
that his "partners" booth had the most user demo-views of any booth in
DAC. Loving to burst false claims, I said: "If that's true, then you
obviously won't mind sharing your total foot traffic stats with me once
DAC's over." He agreed, but I honestly expected he wouldn't follow
through on this. To my surprise, a few days later, his people emailed
me: "We had 956 engineers go through a minimum of three (12-minute)
demos, for a total of 574 engineer-hours in our Partners booth."
One of my spies told me that ARM and Synopsys had an invitation-only
lunch on the Wednesday of DAC. In it they had a Toshiba guy yarping
about his 90 nm design getting 40% power reduction with multi-VT and
dynamic voltage/frequency scaling. In addition, the ARM and Synopsys
guys barked about their "low energy" flow, (energy = power X time =
battery life), which ARM Marketing calls "IEM". Their claim was they
got 60% lower energy.
8. I heard a fun bit of gossip that the Synopsys people were ordered by
Marc Swinnen in Marketing that if they were talking to a Magma employee
they were supposed to let slip that "yes, IC Compiler is really just a
wrapper around PhysOpt and Astro" as a purposeful piece of industry
deception. There's obviously some sort of spy vs. spy psychology going
on here, but I don't quite know exactly what it is...
9. Speaking of IC Compiler, a little bird told me that Synopsys had another
invitation-only lunch on DAC Tuesday focused on it. My source tells me
the lunch was over capacity because some people were turned away at the
door. How this event differed from the SNUG'05 launch of IC Compiler
was they added 3 more hands-on users vouching for the tool. That is,
they recycled the ST and the Agere reviews -- but TI and ARM were
missing this time around. Instead they added Freescale, Qualcomm, and
SGI. IC Compiler averaged 2X better TAT, 15% better Mhz, 5% better
area, and 8X TNS according to the users present. (And although this may
read like I love giving shit to Synopsys for not having TI and ARM
there, I must commend the fact that they have *hands-on* users reporting
hard numbers about IC Compiler. That is, Magma has made a lot of noise
about their Cobra release (yay for them) but I don't give them as
much credibilty until I actually see *hands-on* Cobra users talking
directly to me. I trust users speaking over press releases any day.)
10. A few people at DAC had commented to me about how online EDA news had
fundamentally changed. In the good olde days (say 4 months ago), we
all used to go to EEdesign.com daily because Richard Goering and Mike
Santarini kept it stocked with fresh EDA stories they had personally
researched. And every year, the entire EE Times staff would cover
DAC in detail, putting up 20+ stories of what went down. At that time
EDN was kind of sad because it didn't try to cover the news and its DAC
coverage was only a passing reference. EDAcafe.com, Electronicnews.com,
and SOCcentral.com were mostly just rehashed EDA vendor press releases
for their news coverage back then (as they still are now.)
Then everything changed.
Mike Santarini left EE Times and joined EDN. Suddenly EEdesign.com was
folded into the EEtimes.com website (!?), Richard Goering was taken off
to do more print coverage (!?) and what was left of EEdesign.com became
mostly short stories of rehashed vendor press releases (!!!!?). On top
of that, in a Shock and Awe campaign, a redesigned EDN.com hit on DAC
week plus the EDN/Electronicnews staff all got together to put up 20+
news stories covering DAC in detail -- just like EE Times! Whoa!
"Mike was the steal of the century," said John Dodge, Editor-in-Chief
of EDN. "Our goal is to do deep technical pieces along with EDA news
coverage on the web. Our industry could use more Mike Santarini's."
11. Gradient, the first EDA company to do thermal analysis on a chip, got
a lot of attention this year. This was their first DAC. Their tool,
FireBolt, does static thermal analysis to measure temperature gradients
in an IC substrate (useful for tracking leakage currents.) At EDN,
Santarini wrote about them in detail on-line. Goering gave them 1.5
pages in the DAC hard copy issue of EE Times. "That publicity paid off
well for us," said Rajit Chandra, CEO of Gradient. "We gave 43 suite
demos to 198 leads from 55 companies. Many of them were reruns;
engineers sat through our demo, went away, and later came back again
with their managers in tow to see our demo. To us, that's success."
12. On the EDA blogger front, two days before DAC, Gabe Moretti kicked off
his new http://www.GabeOnEDA.com web site. Feisty, in-your-face, and
with a long personal history in EDA marketing, Gabe's a welcome new
voice. And speaking of in-your-face, Peggy Aycinena's recent column
in http://www.Aycinena.com has people talking. "In my mind the question
is not *if* TSMC will buy Cadence, the question is *when* will TSMC buy
Cadence," writes Peggy.
13. At the DAC Interop breakfast, Synopsys announced that they've changed
the library format in PrimeTime to something they're calling CCS
(which stands for "Composite Current Source"). Basically the old
PrimeTime format was running out of steam below 90 nm and this new
format (according to TSMC) keeps PrimeTime within 3% of HSPICE.
14. Pallab and I had quite a lively discussion on DFM/DFY tools, this DAC
being The Year Of Yield. I purposefully chose to walk over to the
Mentor booth to see about its Calibre DFM tool.
My gut told me Mentor would be the realistic leaders in DFM because of
their many years of RET/OPC/DRC/ERC experience. That also meant I had
to talk to Joe Sawicki. He's the bigwig at Mentor who owns Calibre DFM.
He also owns Calibre; which left me in a bind.
I like Joe. He's a fun guy & a good story teller. The problem is that
Joe hates me. Last year on a Magma panel I publically said "all these
yield guys are lying to you just to get your money" -- and Joe was the
next speaker after me pitching his yield solution. Talk about furious.
And then in ESNUG 445 #12 published right before DAC, a user made his
Calibre (not his Calibre DFM, but his vanilla Calibre) look really,
really bad in a benchmark vs. Mojave. So needless to say, Joe's not
too happy with me -- yet I'm the guy who's saying Calibre DFM is real
and the one to watch in the yield space.
The other funny thing is that Pallab agrees with me on Calibre DFM.
Pallab: "DFM/DFY is split into two approaches:
1) Fix it in polygons that go to mask. Companies that do this are
Mentor, AWR, ChipMD, Berkeley, Xpedion, and Sagantec. The people
in the polygon world all have tapeouts they can talk about and
the mask people know them. These solutions like Calibre DFM
actually work.
2) Fix it in P&R or in abstracts. Companies that do this are Nannor,
Aprio, Ponte, Magma, Synopsys, Silicon Design Systems, and
Manhattan Routing. All the guys in this approach are unknowns to
the mask people. They don't have tapeouts nor is there any direct
correlation between their approach and real silicon. It's all
vaporware. Looks nice, but they don't count for anything.
Blaze DFM, Clear Shape, and Sigma-C were all extremely vague at this
DAC, so I suspect they're just vaporware, too, until they come out with
real products."
And in the irony of ironies, as I was writing this part of my column,
John Ferguson of Mentor phoned me to chew me out. (No, I'm not making
this up. He really did call just then!) "Joe Sawicki told me to
'correct' you on your mistaken ESNUG post," said Ferguson. "You said
it was a benchmark; it wasn't. This was no apples-to-apples eval; it
was a sad comparision of Calibre on a *single* machine vs. Mojave
distributed on 20 machines. If your user had used Calibre MTflex
instead, only then it would've been a fair distributed vs. distributed
benchmark. In that case, extrapolating from the data we've seen, we'd
have probably won that benchmark."
15. In the world of interesting "me, too" tools, Silicon Dimensions was
showing what appears to be a First Encounter knock off but it does SDC
analysis (so logic designers can us it work on timing constraints),
DRC/ERC checking for stuff like gated clocks and counting logic levels,
floorplanning with auto macro placement plus it has a standard cell
placer, too. It also has a checking router that does virtual routing
and statistical congestion analysis, cone tracing, custom wireload
models and dynamic power density analysis. Chip2Nite outputs both
Verilog and DEF. It inputs LEF, DEF, Liberty, SDC, SAIF, Verilog; but
no plib nor PDEF yet. They're also trying to weave in a yield aspect
to their tool, but I think they're just riding the DAC bandwagon on
this. I'll believe it when I see it. "Last year we got 137 leads
at DAC," said Mike Naum, SiDi CEO. "This year we got 530 leads. We
had 3 demo suites constantly running and standing room only. We're
hitting the weak spot in both the DC-Astro and Encounter flows;
otherwise we wouldn't have been so busy."
16. The new kid on the block in bug hunters this year was Calypto. They
have two tools: one does SystemC/C++ to Verilog/VHDL RTL equivalence
checking. The other tool does RTL-to-RTL comparisions of designs where
their state machines have changed drastically. Yup, it determines if
the two different state machines are functionally equivalence.
Powerful stuff! (The Calypto folk were also gushing they had scanned
1,973 customer badges in their booth this year. I didn't have the
heart to tell them that they're in the honeymoon period of being the
new verification tool du jour. Enjoy it while you can; the numbers
next year won't be so astronomical.)
In sustainable terms, the Jasper people gleefully reported having 915
suite visitors, up 44% from the prior year. The other bragging point
they had was that Chris Malachowsky of Nvidia had publically endorsed
both their JasperGold and Synopsys Magellan on a DAC panel. Congrats.
And in the category of weird DAC firsts, Jasper had the first 2 floor
DAC booth this year. (I guess DAC floor space is really expensive!)
I must say that a lot of the talk I heard about bug hunters this year
was of the Calypto/Jasper/0-in/Magellan variety. It was as if these
were now the Big Four leaders in this niche. That is, I wasn't hearing
people discussing Real Intent, Avery, Axiom (@HDL), Jeda, nor Stelar.
And the Big Four didn't seem to see them as a threat either.
Of course, the moment I told Cliff this, he had to make me look wrong.
Cliff: "To me, Axiom was interesting because they have a distributed
simulator. They're the old @HDL. They're going up against the big
boys like VCS, NC-Sim, and ModelSim. It dices up your run across eight
64-bit Opteron processors. The Axiom tool automatically figures out
where your simulation partitions should be, spreads the runs across
those 8 CPUs, and then pulls it all back together. An end user has to
do nothing but watch his simulations run much faster."
"I wasn't terribly impressed with Avery's verification IP. They
said their IP was correct because all the other IP providers gave them
positive feedback on their verification IP. That's great, but how
do you know you're covering the full spec? I don't buy it."
"Real Intent and Stelar had clock domain crossing tools. Real Intent
tries to be in the Jasper formal verification space but they claim to
be much faster," continued Cliff. "The Stelar tool identifies the
clocks in your design at the RTL level and figures out which signals
need to be synchronized into a new clock domain and then inserts the
synchronizers."
17. This year I positively must give the Biggest Brass Balls Award to Rajeev
Madhavan, CEO of Magma, for his sense of humor before the Wall Street
crowd. Normally, EDA people get all nervous and jittery around the
financial analysts. Why do you think the DAC CEO Panels are so dull?
They don't want Wall Street downgrading EDA stocks! It also means
everyone's super *safe* and on good behavior in front of the analysts.
So how did Rajeev title his pitch in front of the investment community?
"Magma: A Lot More Than Litigation Going On" -- hence the award.
To no big surprise, in the suites John Lee of Magma Mojave later told
me he got a lot of requests from users at DAC asking for Quartz DRC
demos after ESNUG 445 #12 was posted.
In addition, Magma demoed their statistical timing analysis at DAC to
counter the IBM EinsTimer announcement this year. On Tuesday afternoon,
Magma did a joint DAC sponsored tutorial with CoWare, Virage, and MIPS
on going from CoWare C to Magma Structured ASIC.
In response to Synopsys DC 2005 getting rid of wireload models, Yatin
Trivedi of Magma cheekily said: "My guess is that their 90 nm customers
have been pestering Synopsys about this. We've been free of wireload
models for 7 years. I'm flattered that Synopsys is playing catch up to
us in the RTL synthesis market."
For their power demos, leakage tweaking and power grid synthesis were
their main focus of this year. Their Cobra demos centered around a
something they called "interconnect synthesis". As best as I can
figure, this is their way of saying they're doing logic restructuring
at the routing level.
18. Concerning Structured ASICs, the Synplicity folks reported that this
year their booth traffic was up 30% to 1,126 badge swipes. There were
two things they were yarping about at this DAC: Structured ASICs (of
course) and their new graph-based physical synthesis thingy for FPGAs.
"This year we're seeing people going onto their second designs using
Structured ASICs," said Gary Meyers, CEO of Synplicity. "The NEC, LSI,
and Fujitsu people were happy to team up with us on this."
One of my contacts at Synplicity said that they also had a lot of
interest in their Identify (RTL FPGA debugger) product; they had to
take down one of their general purpose demo stations to replace it
with a specially configured Identify demo.
19. The Mathworks booth caught my eye this year because they were barking
about their Simulink having a design flow into Xilinx and Altera FPGAs.
The Xilinx tool is blandly named "System Generator for DSP" and the
Altera tool is better named "DSP Builder". (If you haven't figured it
out by now, these are targeting DSP designs.) Don't be fooled, these
aren't synthesis tools -- they're more like high level schematic
mappers of Simulink blocks into Xilinx/Altera IP cores. For example,
in Simulink you can specify 3 fully parallel, 8-bit, binary point at
bit 6, 2 cycle latency, negative symmetric FIR filters and DSP Builder
will grab the specific Altera core with these paramaters and slap it
into a Stratix II EP2S60 for you. Neat.
20. For the 5th year in a row, Gary Smith and Daya Nadamuni made a laughing
stock of themselves in their pre-DAC Gartner/Dataquest event by (once
again) predicting that this is the year ESL tools will really take off.
"Honest, folks, there's gunna be a reeeeeeal big boom in these system
level tools that work on the high, architectural level in C on stuff
like behavioral synthesis and such," I thought I heard either Gary or
Daya say. (Not sure which said this; the free beer at their event may
have muddled this quote.) I do remember laughing at that ESL graph that
went from $150 million in 2004 to $1.6 billion in 2009 revenues.
Laughing aside, the EPA should give Gary and Daya some sort of award for
recycling the exact same ESL prediction for 5 years in a row. Woodsy
the Owl would be proud. "Give a hoot, don't pollute!"
21. Cliff: "Gary made ESL the buzzword for this year's DAC, but the only
company I saw at DAC that was truely ESL was CoWare. They seem to be
the only company focused at the software engineer who is targeting
hardware. It seemed to be a high speed architectural exploration tool
whose output feeds into Forte's SystemC behavioral synthesis."
"If there was a tool flow I'd be looking at after this year's DAC, it
would be CoWare to Forte to Design Compiler to P&R of your choice.
The irony here is that I'm a known System Verilog bigot, yet I'm most
interested in this SystemC flow," concluded Cliff.
The CoWare people reported that they got 635 leads at this DAC, up 69%
over last year. "That Dataquest kickoff with ESL being hot was a great
start for us at DAC," said Alan Naumann, CEO of CoWare. "However, at
the end of the show, what got us excited was that our conversations with
customers shifted from technical discussions to talks with their senior
management on how we could work together."
22. In terms of customer interest, the Mentor Catapult C people would not
share their DAC suite attendance numbers, while the Forte people were
quite happy to brag about how their suite stats being up 23% this year
at DAC to 465 leads.
"The interesting thing was that last year we spent a lot of our suite
time with existing customers. This year our existing customers said
'we see you all the time' and just asked us for a booth T-shirt,"
said Brett Cline of Forte. "So most of those 465 were new prospects.
Last year lots of the prospects came in questioning the viability of
SystemC synthesis. This year they were more it-looks-like-it-works,
-so-why-should-I-use-it? types."
23. Cliff: "Bluespec caught my eye. They're behavioral synthesis. You
start with a stylized System Verilog and you compile down to Synopsys
synthesizable RTL. They differ from Forte because Forte only does
SystemC. Bluespec says they do datapath and control synthesis; they
Forte does only datapath."
24. Pallab: "The coolest product I saw on the DAC floor this year was
Xoomsys. They pre-announced a tool that speeds up SPICE, AMS, and
Verilog simulation; it partitions your runtime threads so it'll run on
a Linux farm *even if* you don't have a distributed simulator. Unlike
LSF, Xoomsys actually works with your design data instead of your
licensing scheme. If it works, it'll be the first product at DAC in
3 years that actually reduces your time to market."
Cliff: "That sounds simular. The AccelChip people also have a tool
that does behavioral synthesis from Matlab to synthesizable RTL. They
seemed very focused on the DSP niche market instead of being a general
behavioral synthesis solution like Forte or Bluespec."
25. Pallab: "Silicon Canvas, Pulsic, Silvaco, and Ciranova tools have
evolved to the point where they're actually complete. They've become
an effective alternative to the Cadence monopolies of Analog Artist
and Virtuoso. These rivals all significantly outperform Virtuoso.
Tanner also seems to be matching Cadence in this domain, but at 20% of
Cadence's price. Cadence used to always have some sort of edge in
this space because they kept adding knobs; but roughly 2 years ago
they stopped adding knobs and their rivals have caught up. If I were
Cadence I'd be on guard."
26. Pallab: "In the transistor simulation world, there are two schools:
1) high accuracy -- HSPICE, Silvaco, Eldo, Spectre. The 2nd tier
guys in high accuracy are Legend, Tanner, Berkeley, AWR, and
EverCAD. This market has essentially remained unchanged in
the last 2 years.
2) high capacity -- the undisputed leader here is Synopsys/Nassda.
They have something like 88% to 92% of the world market share.
Cadence UltraSim, Apache NSPICE, Mentor Eldo-AMS, EverCAD Diamond,
Legend Turbo-MSIM, and Silvco Harmony are all fairly compatable
with Nassda HSIM. Their market strategy is to poach people who
don't want Synopsys as a supplier.
All the benchmarks in the high capacity niche are with 5% of each
other (i.e. a wash.)"
27. Now it was my turn. "I was suprised. Cadence Open Access seemed to
be gaining some acceptance," said Pallab. "Silicon Navigator was
getting lots of attention from the IDMs at this year's DAC."
What Pallab didn't know at the time was that Synopsys had joined Si2
*only* on the analog side; Synopsys has no intention of bailing on
its Milkyway database but they'll gleefully go after anything they
can get in the Cadence monopoly of analog design tools. They're
only half in on Open Access.
28. In package design, a little bird told me that Optimal PakSi-E had
kicked out Ansoft Q3D Extractor on the Cadence Allegro Package Designer
contract 2 years ago. Birdy also said Optimal sales were $2 million
last year and looks like it'll be $4 million this year. Life is good.
29. I finally got to see the Golden Gate stuff this year. (In prior years
their marketing guy was against getting publicity for his tools. This
year I found out Golden Gate not only got a new marketing guy, they
also got a new CEO!) Turns out they have two power opto tools. The
first tool shrinks your clock tree and moves your top 20% power-hungry
wires to the upper layers. The second tool creates multiple voltage
islands on your power grid. "Thanks for the visibility this year,"
said Dennis Heller, CEO of Golden Gate. They reported getting 358
customer leads at DAC this year, up from 239 last year -- a 50% gain.
30. On the personal integrity front, I was beaten up by the CEO of VeriEZ
for being an anti-Vera bigot. (Ouch!) VeriEZ has a tool which ports
Vera to System Verilog. In my pre-DAC Must See list, I mentioned
Cadence Verisity Specman "e" in my #3 item, but made absolutely no
reference at all to its technical rival, Vera. My bad.
31. In other news, GlaxoSmithKline has filed a lawsuit in U.S. Federal
Court against the DAC Executive Committee. To quote the filings, the
DAC people "did maliciously and with aforethought willfully craft a
multimedia production to cause economic and irrefutable harm such that
GlaxoSmithKline must seek injunctive relief."
In layman's terms, Glaxo is furious at the DAC committee for putting
a publically accessable video of this year's CEO Panel up on the web.
That panel was so safe, so dull, and so content-free, Glaxo knows it'll
hurt the sales of their Nytol and Sominex nighttime sleeping pills.
In closing, I'd like to say that you should keep your eye out in September
on DeepChip.com for the DAC videos Cliff, Pallab, and I did. These weren't
your usual look-Ma-I-have-a-camera interviews with easy softball questions;
instead, it was the three of us grilling the EDA vendors from a user's
perspective on why we should (or should not) use their tool. The idea was
to capture the real EDA tool user's DAC experience on tape. Fun!
- John Cooley
ESNUG/DeepChip.com
P.S. And, yes, I'll still be doing a DAC Trip Report survey later to get
everyone else's thoughts on this year's crop of EDA tools! :)
-----
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
or (508) 429-4357.
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