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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2018"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
My unofficial guide to the San Francisco DAC'18 exhibit floor. Enjoy!
EDA IN THE CLOUD
1.) Cadence Cloud HDS is Anirudh announcing all CDNS SW is now available
on the Amazon AWS and Microsoft Azure clouds. It's all his Cadence
simulators Incisive, Xcelium, Spectre -- plus also now all his design
tools like Genus RTL, Innovus, Tempus, Voltus, Virtuoso, ADE, Liberate,
Quantus QRC, Stratus HLS, etc. available on the two clouds, too.
Back in 2008, Cadence gave small chip start-ups a web portal they
called "Hosted Design Solutions" (HDS) that gave users access to the
specific CDNS tools that they had already bought with yearly licenses.
It was essentially Cadence taking over all the IT and EDA tool support
tasks for the start-ups for a fee. It was limited to under 10 servers
per customer and never caught on beyond a few small chip start-ups.
What's different with Cloud HDS is users can now access all CDNS tools
either through Cadence, or through their own do-it-yourself AWS/Azure
account, to do elastic compute stuff. "For example, a customer can
buy a base set of 10 Xcelium licenses for a year for his daily needs.
Then during crunch time he can rent 1,000 Xceliums for 3 weeks. The
pricing is the same as if you had the tools on your own servers. With
your CDNS EDA Card you buy our SW per week, per month, per quarter, or
per year. On the AWS/Azure clouds it's the exact same pricing model."
And those rival non-Cadence tools? "Cloud HDS is a secure environment
for customer IP and 3rd party IP. They can bring in DesignWare or VCS
or Calibre or Questa or Catapult or AFS -- we don't care. We don't
qualify, nor restrict in any way, what outside SW or IP a user wants
to bring in. It's the user's environment. We're just adding all of
our Cadence tools to run with all those AWS elastic compute servers."
(booth 1308) Ask Carl Siva. Freebie: Denali party tix
Mentor Veloce Cloud (as per my scoop earlier this month ESNUG 583 #4)
is where Jean-Marie gloats about having the 1st emulator anywhere on
*any* cloud, this being the Amazon AWS Cloud. "Sorry, Palladium!"
(booth 2621) Ask for Jean-Marie Brunet. Freebie: 3D Viewer
Although now in 2nd place, Cadence will announce Palladium Cloud that
runs in both Amazon AWS and Microsoft Azure clouds. "Sorry, Veloce!"
(booth 1308) Ask Frank Schirrmeister. Freebie: Denali party tix
IC Manage PeerCache Holodeck does "hybrid cloud bursting and extreme
file I/O performance". It's software and compatible with your local
NFS. Run your existing EDA tool workflows in the cloud without all
the required painful cloud-related IT and upload tweaking. "I can run
my 5,000 BDA AFS regressions overnight on AWS now!" PeerCache Holodeck
dynamically determines exact data needed by that job. ESNUG 582 #8.
(booths 2618 & 1240) Ask for Shiv Sikand. Freebie: chocolates
Expanding Synopsys DesignSphere 3 to include DC, ICC2, CC, etc. is
rumored, but since it failed in 2000 and in 2011, some in SNPS are
very hesitant on it. "Third time's the charm!" Roadmap stage now.
(booth 1609) Ask for David Hsu. Freebie: prayer beads
Look for other cloud mentions throughout the Cheesy list this year.
PORTABLE STIMULUS
2.) In the Portable Stimulus (PSS) wars, Accellera PSWG voted 9 to 5
against the Breker "graph the paths between resources" way and for
the Cadence/Mentor "resources infer the paths between them" way.
In short, Breker has to rewrite a ton of its tool code now???
Anyway, PSS promises UVM reuse from HW all the SW developers.
UVM Simulation ==> HW/SW Emulation ==> final post-Silicon
For a good detailed tech primer on PSS, see ESNUG 578 #1, #2, #3.
Breker Trek5 -- since its beginning in 2008, Breker has been a
graph based tool focusing on C++ output. Now Trek5 has new visual
editor GUI, test map, graph viewers. Also has "unique graph-based
model configuration" for scenario path constraints and HW/SW layer.
It takes in PSS 1.0 "declared" stuff, and in graph form synthesizes
gens multi-threaded, multi-processor, multi-memory C tests for cache
coherency and uP-memory workload perf. Power management, ARMv8 app,
Verdi debug. Users Huawei, Broadcom, IBM, Nvidia, Altera/Intel.
Cavium used it for 3-chip 144 mixed cores in silicon bring-up lab.
Breker was #2 behind CDNS Perspec in "Best of 2017" (See DAC'17 #1b)
This year Breker is adding DSL input, and better synthesis to UVM.
Breker's strength is it's output is easy to make into testbenches.
(booth 1419) Ask for Adnan Hamid. Freebie: cable thingys
Cadence Perspec is on the not-C++ but DSL side. It's a multi-core
ARM verification library/tool for cache coherency, distributed virtual
memory, low power. "We're swimming in ARM cores, John!!! Swimming!"
Dropping own CDNS SLN input to be 100% PSS 1.0. This year Perspec
output now can be easily made into runnable UVM testbenches. Perspec
voted #1 by users ahead of Breker in "Best of 2017". (See DAC'17 #1a)
Qualcomm, Samsung, Mediatek, Renesas, ST, TI, Infineon are users.
(booth 1308) Ask for Mike Stellfox. Freebie: Denali party tickets
Mentor Questa InFact "achieves System Verilog coverage 25X faster
than old school constrained random test." Imports SV constraints and
generates SV IP level tests & system level C/C++ tests. Dropped
proprietary input to be 100% PSS 1.0. Pre-PSS, InFact users like as
coverage space pruner getting 30X sim speed-up. (ESNUG 581 #3.)
Users are Qualcomm, Applied Micro, Ciena, Microsoft, Microsemi.
(booth 2621) Ask for Mark Olen. Freebie: 3D viewer
Synopsys isn't showing a PSS tool. Rumor is they're looking at
acquiring Breker to fill that hole.
IR-DROP / NOISE / THERMAL / POWER
3.) NEW! -- Cadence Project Virtus is Anirudh's surprise attack on both
John Lee's Redhawk IR-drop along with Aart's Primetime STA empire.
Because high local resistance at 7nm fundamentally change how wire
delay calcs need to be done, Project Virtus is Anirudh's R&D welding
together his Voltus (IR-drop) with his Tempus (STA) into one new
timing tool. (See ESNUG 584 #3) Cadence R&D can do this because in
2012 all CDNS digital R&D SW moved onto one db and one datamodel;
making merging two tools *much* easier to do. Unlike RedHawk, Virtus
does switching instead vectorless IR-drop. "Machine Learning, too!"
(booth 1308) Ask for Marc Swinnen. Freebie: Denali party tix
Primetime SIG is where John Lee will announce the "official" super
tight integration between his RedHawk-SC within Primetime-SI that's
to work inside Aart's IC Compiler II -- plus have the Gear SeaScape
Big Data stuff thrown in, too! (Now how two rival EDA vendors can
get 4 different db's and 4 different datamodels to work together is
another question -- but I'm sure they'll say "it's 100% seamless!")
(booth 1637) Ask for John "Jolly" Lee. Freebie: stuffed animal
Ansys Gear SeaScape is the machine learning that guides RedHawk for
best QoR. Claims reduce die size by 5%. Problem is SeaScape/RedHawk
got inconsistant results. (ESNUG 563 #10 and 583 #5) Fixed now?
Ansys Apache RedHawk is full-chip/3d-IC power integrity analysis and
sign-off, transients, simultaneous switching noise package/PCB with
distributed processing. Scalable to 16-32 machines (128-256 cores).
"500M insts with 8B resistors while keeping flat simulation accuracy"
Vector-based and vectorless. Clock jitter. TSMC 16/10/7nm FinFET.
RedHawk-SC claims "IR-drop in 6 hours on a 1 billion gate chip on a
16G machine" and "does 1000 scenarios overnight". 16/14/10/7nm.
(booth 1637) Ask for John "Jolly" Lee. Freebie: stuffed animal
Cadence Voltus does full-chip signoff, IR-drop, Power-Grid-Views.
This year massively parallel. "Runs up to 10X faster and scales
up to 1,024 CPUs" 1B insts over 100s of compute CPUs. Does ECO's.
Works with Tempus and Sigrity chip/package/board and Innovus PnR.
Early Voltus user cut runtime 9 days to 1 day on a large ARM design.
Now in TSMC 7nm ref flow. HiSilicon, Juniper, TI, ARM, Nvidia, NXP,
TSMC, GF, Samsung, STM, ON Semi, Spreadtrum, Mellanox, Renesas, ADI.
Voltus-Fi does transistor-level noise/power signoff with Quantus QRC
and MMSIM inside Virtuoso. Both Voltus & Voltus-Fi are TSMC 10/7nm.
Apache Totem and Synopsys HSim-PWRA both compete against Voltus-Fi.
(booth 1308) Ask for Jerry Zhao. Freebie: Denali party tickets
Silvaco InVar does super quick IR checks on FinFETs using only your
layout data. Snoops out high IR-drop, high current density related
EM issues, etc. Does "point-to-point interactive resistance checks,
pin resistance mapping, and very fast What-If analysis iterations."
Competes against Ansys Totem and Cadence Voltus. Toshiba uses InVar.
(booth 2429) Ask for Alex Samoylov. Freebie: water bottles
Magwel ESDi also does ESD analysis just like Apache Pathfinder ESD.
Checks all possible shunt paths during event; fewer false positives.
It can now handle chips as big as 10x10 mm^2 on up to 1000 pins.
Magwel PTM-TR uses a 3D field solver to do fast-but-accurate transient
Spectre simulation of power transistor circuits. Used for switching
power loss, check current crowding, device reliability.
(booth 2423) Ask for Dundar Dumlugol. Freebie: none
NEW! -- ICEE Ceatus does static checks from power leakages to basic
circuit integrity, which Spice/Spectre/Verilog netlists misses. Does
Formal power intent signoff for AMS designs, complementary to UPF.
(booth 2123) Ask for Henry Cao. Freebie: webcam covers
Silicon Frontline P2P-XL does IR-drop with multiple FSDB files for
activity concurrently and perform pre-LVS clean analysis. No need
for vector creation. Do IR-drop at any stage during design.
(booth 2363) Ask for Yuri Feinberg. Freebie: none
Teklatech used to compete here, but isn't showing at DAC this year.
DIGITAL P&R
4.) My true #4 "Must See" is about two people, and not an EDA tool.
SCOOP! -- Avatar (Atoptech) Aprisa is back from the dead! After
the Synopsys lawsuit, from what I've heard a non-EDA Chinese company
bought out the non-legally-offending assets, and put ex-CDNS digital
PnR R&D bigwig Chip-Ping Hsu and ex-CDNS sales bigwig Charlie Huang
in as the two new leaders of Avatar.
Technically, since Avatar still has Samsung, Broadcom, Xilinx, Inphi,
Mellanox, Cypress, and eSilicon as current users, it wasn't "dead" as
much as "hibernating". So it's now "awake" (and lawsuit-proof from
Aart) and ready to take on the CDNS and SNPS 16/14/10/7nm PnR rivals.
(booth 1645) Ask for Chi-Ping or Charlie. Freebie: flying monkeys
Cadence Innovus -- launched by Anirudh in 2015, it's taken over at
16/14/10nm and "preferred choice for design starts at the 7nm node".
Innovus was the only PnR tool used in the world's first 5nm tapeout
(ESNUG 554 #3) and 3nm tapeout (ESNUG 582 #4). It gets consistantly
better PPA on ARM cores than ICC2. For 7nm, Innovus-Voltus being
uber tight with each other got #7 "Best of" with users in DAC'16 #7;
(Innovus + Voltus did ECOs with 93% less victims) which is a direct
threat to the Synopsys/Redhawk 7nm IR-drop patch in ESNUG 584 #3.
The other pain point for Aart is digital Innovus is uber tight with
full custom Virtuoso. Meaning lots of A/d, D/a chips he's missing.
So no surprise that Qualcomm, Nvidia, ST, Faraday, GF, HiSilicon,
Broadcom, Toshiba, Freescale, Juniper, Renesas, ARM, Maxlinear,
Spreadtrum, Silicon Labs, AltaSens, Cypress, ImgTec, Realtek, NXP
(and two very big and very quiet "others") are all Innovus users.
I'm sure by now Aart regrets letting Anirudh go after the LAVA buyout.
This year -- like everyone else -- Innovus is yarping up its Machine
Learning features "that we've had for years now!" -- plus the bigger
news that Innovus is on the Amazon AWS and Microsoft Azure clouds.
(booth 1308) Ask for Vinay Patwardhan. Freebie: Denali party tickets
Synopsys IC Compiler II had (all or most) of its leaders replaced and
its R&D gutted last year:
"I don't know what the exact numbers are, but Synopsys laid off
200 people between 55-60 years old. So, they cleaned house of
everybody in the prior generation.
So, how long does it take that new IC Compiler II generation to
get on their feet and start being productive and potentially
challenge Anirudh for the lead?
In my experience, writing a place and route system takes 3 to 4
years. We're not going to know if Synopsys has a good team or
not for 3 or 4 years."
- Jim Hogan in DAC'17 Troublemakers Panel
Then right after DAC'17, Aart hired PnR veteran Shankar Krishnamoorthy
(ex-Sierra) out of Mentor to do all the deep tech leadership of this
massive 3 to 4 year ICC2 rewrite. Right now ICC2 "works", but it's
getting painfully trounced by Anirudh's Innovus at Tier 1 accounts.
(booth 1609) Ask for Shankar Krishnamoorthy. Freebie: promises
NEW SCHOOL RTL SIMULATORS
5.) SCOOP! -- Montana (Joe Costello's start-up) is merging with Metrics
to have their Montana Verification Processing Unit's (VPU's) on
the Google Cloud. Their VPU is right now implemented on Altera
Stratix 10's -- but it's not yet another emulator on FPGA's; so it
does NOT have the HAPS/Zebu/Protium super long compile time issue.
Instead it's a uP custom tuned to a System Verilog IEEE 1800-2012
simulator. "One of my Montana VPUs can take 100 M gates and run them
5X to 20X faster than Cadence Rocketick or Synopsys Cheetah VCS. At
total capacity of 4 Billion gates, it goes even faster", says Joe.
(booth 1244) Ask for Joe Costello. Freebie: paper notebooks
Cadence Xcelium (Rocketick RocketSim) is parallelized System Verilog
across 100's of Intel CPUs. Benched 23X faster vs. VCS, Incisive,
Questa. Does gate and RTL sims. Compiles 1 B gates in 2 hours.
Got #3 User's Best of in 2016. (DAC'16 #3) "It's in AWS and
Azure clouds now!" Xcelium comes in 1K cloud packs at a discount.
SystemC, e/Specman, VHDL, low power. Customers Intel & Nvidia.
ARM sees 5X speed-up for RTL/gate; STmicro at 8X for DFT simulation.
(booth 1308) Ask for Uri Tal. Freebie: Denali party tix
Synopsys VCS FGP used to be called Cheetah. It's Aart's home grown
answer to Lip-Bu's 2016 Rocketick acquistion, also based on X86 CPUs.
Fine-grained parallelism. RTL 8X speed-up on 20 cores. Gates 12X
speed up on 20 cores. X-prop. Low power. Verdi integration.
(booth 1609) Ask for David Hsu. Freebie: pens
FPGA STUFF
6.) Plunify InTime optimizes and closes timing on FPGA designs. Does
machine learning for best build parameters for each design, such
as synthesis options, place & route options, placement locations,
pipelining stages. Launch inside Xilinx Vivado or Altera Quartus.
20% to 80% faster clock frequency in your FPGA design. "Get results
in days, not weeks." Runs in AWS cloud on hourly licensing model.
Plunify Kabuto is machine learning to give RTL fixes for FPGA designs
based on timing path/RTL analysis -- e.g. you need to pipeline a
design, it suggests code needed to ensure dependencies are checked
properly. Not linting tool; it fixes bad RTL timing paths.
(booth 2124) Ask for Kirvy Teo. Freebie: fidget spinners
Mentor Certus does silicon debug for FPGAs, FPGA Prototypes and ASICs.
It rivals Xilinx ChipScope, Altera SignalTap, Synopsys Identify.
"Traced 500 AXI bus signals of a Linux boot sequence (180 seconds)"
(booth 2621) Ask for Doug Amos. Freebie: 3D viewer
Blue Pearl VV Suite lets FPGA engineers visually verify by way of
graphical FSMs, CDC and false path viewers with cross probing to RTL,
with forward and reverse tracing, and linting message filtering.
Upgraded its simultaneous clock and reset domain analysis CDC stuff.
NEW! -- HDL Creator is an editor with 2000 real-time checks to fix
issues as you code, such as compilation and missing dependencies.
Raytheon, GE, Harris, BAE, Parker Hannifin, Lockheed, L3, Ricoh.
(booth 1457) Ask for Ellis Smith. Freebie: water bottles
NEW! -- Arcas Tech AveMC does ABV on FPGA designs in the AWS cloud.
(booth 2135) Ask for Jun Yuan. Freebie: pens
Menta eFPGA Origami is a unique tool that lets ASIC/SoC designers
create their own TSMC 28HPC+ or GF 14LPP embedded custom FPGA IP blocks.
(booth 2329) Ask for Yoan Dupret. Freebie: ment candy
Mentor Precision Hi-Rel does synthesis-based automated single event
effect mitigation methods such as triple modular redundancy (TMR),
fault-detect and fault-tolerant FSM encoding in FPGA's. ISO 26262,
DO-254, and IEC 61508. Competes against Synopsys Synplify Premier.
New this year is a LEC flow for datapath-centric FPGA designs.
(booth 2621) Ask for Badru Agarwala. Freebie: 3D Viewer
OneSpin 360 EC-FPGA does equivalency checking RTL vs. post-synthesis
netlists for FPGA's. (booth 2611) Ask for Raik Brinkmann.
BUGHUNTERS
7.) Cadence JasperGold has 14 formal Apps. 2X capacity and 10X speed
in last 12 months. "Our Superlint and CDC apps kick ass!" Jasper
finds bugs 1000's of cycles deep. Tight with Xcelium and vManager.
Samsung, HiSilicon, Nvidia, Qualcomm, TI, Broadcom, Marvell, ARM.
(booth 1308) Ask for Pete Hardee. Freebie: Denali party tickets
OneSpin is very ISO 26262 this year. 360 Verify does property
checking with coverage. 360 Quantify does a full formal coverage
of your code and SVAs. Their 360-Safety injects faults into device
code to see if it recovers from an operational fault in the field,
and still works. "ISO 26262, baby!" Their 360 EC-FPGA equivalency
checks RTL vs. post-synthesis netlists for FPGA's. "ISO 26262!"
Renesas, Nokia, Infineon, Xilinx, Western Digital, Bosch, Maxsim.
(booth 2611) Ask for Raik Brinkmann. Freebie: cellphone grip
Mentor Questa Formal has 11 formal Apps. X-checking, RTL checks,
coverage, assertion checks, property generation, connectivity checks,
post-Silicon, register checks, CDC -- plus SLEC for safety-critical
designs. "ISO 26262, baby!" Has GUI with web and mobile clients.
Samsung, Cypress, Microsoft, Microsemi, Mediatek, AMD, and Rambus.
(booth 2621) Ask for Joe Hupcey. Freebie: 3D Viewer
Amiq Verissimo is like a Spyglass linter but just for System Verilog
testbench code. "100+ new checks in assertions, dead code, language
pitfalls, code maintainability, and UVM methodology guidelines."
Samsung, Cisco, Qualcomm, Xilinx, Toshiba, Broadcom, Nvidea, NXP.
(booth 1414) Ask for Cristian Amitroaie. Freebie: chocolates
Synopsys Atrenta Spyglass plays heavily in killer linters, but I
don't know if they got space in the Synopsys booth this year.
Real Intent Verix CDC does MCMM signoff "for true multi-mode CDC RTL
analysis." Single set-up. All modes single run, no iterations.
Static intent verification finds non-operational clock modes.
Verix CDC vs. Spyglass CDC or Questa CDC save 3.3x CPU time and
5x engineering time per iteration. See ESNUG 574 #2.
(booth 1431) Ask Vikas Sachdeva. Freebie: LED pens
NEW! -- Verix PhyCDC goes complete gate-level netlist CDC sign-off
with glitch checking. Uses SDC constraints and RTL CDC results for
fast incremental sign-off of all pathways. See ESNUG 584 #2.
500M+ gate designs get fast throughput from parallel processing.
(booth 1431) Ask Prakash Narain. Freebie: LED pens
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. 500 M inst with 1000 clocks in
8 hours. GUI user does full tracing. Handles flop duplication,
retiming and merging. Qualcomm, Nvidia, Broadcom, Mediatek, ARM
(booth 2310) Ask for Sam Appleton. Freebie: teddy bears
Mentor Questa CDC "fast CDC, highest QoR." ISO 26262 certified.
Has gate-level stuff for FPGAs. Mediatek, Continental, AMD, HP.
(Booth 2621). Ask for Joe Hupcey. Freebie: 3D Viewer
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 2628) Ask for Stanley Hyduke. Freebie: pens
NEW! -- Excellicon ConTree in pre-CTS phase analyzes your clocking
structure to define proper clock skew groups, automatic creation
of anchor buffers and creation of CTS file. In post-CTS phase, it
verifies CTS for lowered clock latency and skew.
NEW! -- Excellicon ConMan Ultra formally synthesizes RTL or gates
timing constraints. No prior design knowledge required. Does
automatic clocks & mode discovery. Auto synthesis of case_analysis
values. Generates complete SDC's for multiple modes and any
hierarchy. Merging of unlimited modes. LG, ST, Maxim, Xilinx.
NEW! -- ConCert InSync lets you load pre- and post-optimized designs
along with the SDC's and verify the correctness of the design timing.
Excellicon ConCert Steroid verifies timing intent & structural
exceptions using SVA+/formal. SDC, CTS, demotion, equiv checking.
ConMan formally crafts hierarchical constraints for multi/merged mode
SDC, promotion, clocking analysis. 500+ M inst. Users are LG,
Samsung, Marvell, Renesas, Qualcomm, Western Digital, Maxim, ST.
(booth 2662) Ask for Himanshu Bhatnagar. Freebie: baseball caps
Real Intent Meridian RDC finds messy reset metastability and glitch
problems. Optimized data models. Rivals SpyGlass RDC, Questa RDC
Did 200M gate full chip RDC analysis in 9 hrs with ~160 G memory.
(booth 1431) Ask Oren Katzir. Freebie: LED pens
FishTail Confirm verifies if your asynchronous resets are glitch
safe using formal and AVB. Requires just SDC & RTL. SDC EC verifies
if constraints are correctly moved up/down design hierarchy. Runs
40M gate design in 7 hrs. FishTail Focus SDC constraints cut PnR
runtimes by 3x. Mediatek, Invecas, Qualcomm, Xilinx, Infinera,
(booth 2648) Ask for Ajay Daga. Freebie: an iPhone X ?
NEW! -- Ausdia Timevision SOC Budgeter handles the SDC time budgetting
across hierarchical boundaries. Uses SDFs, timing reports and physical
data (LEF/DEF) to produce and manage accurate timing budgets for the
blocks used in hierarchical implementation flows.
Timevision SdcCheck does 200 checks. "your SDC + checking it's intent."
MMMC constraints, Verilog/SystemVerilog/VHDL, IEEE P.1735 encrypted RTL.
Precise file/line backtracking pinpoint in your source RTL/SDC issues.
(booth 2310) Ask for Sam Appleton. Freebie: teddy bears
Real Intent Meridian CDC does single mode signoff. On 300M gate
chip with 103 clock domains, the hierarchical CDC runtime cut by
5X and memory use cut by 4X.
Arcadia Innovation TimeHawk Constraints finds SDC patches that used
to be found during placement and CTS iterations. Claims saves 3 to
4 weeks of design iterations. Also does full chip SDC debug.
Claims 10+ million inst designs are "run in a couple of minutes."
(booth 1662) Ask for Joey Lin. Freebie: pens
NEW! -- Real Intent Verix SimFix does X-pessimism correction for
accurate gate-level simulations (GLS) because random initialization
or synthesis switches can mess up your GLS. X-accurate simulation
runs are 2.2X faster on ~350M gate design. Supports a hierarchical
flow to enable SoC-scale gate level simulations. (ESNUG 583 #2)
(booth 1431) Ask Lisa Piper. Freebie: LED pens
Avery SimXACT automatically find X bugs in RTL and eliminates false
X's in gate-level simulation. Has gated clock X pessimism analysis
and auto generated fix deposits. Verdi, SimVision, Questa SIM Wave.
"Gate simulation bring-up productivity is more than fixing false Xs!"
Also Avery is doing a joint demo with Metrics/Montana at this DAC.
Broadcom, Qualcomm, Nvidia, Western Digital, HPE, Cavium, MediaTek.
(booth 1508) Ask for Chris Browy. Freebie: cellphone mount
Cadence Conformal LEC does both gates-gates and RTL-gate logical
equivalence checking. The #1 selling LEC in Synopsys design flows
because it's wise to have a checker from outside your flow. Now has
does adaptive proofs, 4X average TAT with 4 CPUs, 20X with more CPUs.
Intel, Xilinx, Broadcom, LG, Qualcomm, ARM, Samsung, NXP, HiSilicon
(booth 1308) Ask for Avinash Palepu. Freebie: Denali party tickets
Mentor Visualizer Debug is Wally's debug answer to Cadence SimVision
Debug Analyzer and Synopsys DVE/Verdi. Visualizer debugs RTL, gates
and testbenches, automatic tracing to "pinpoint cause of errors".
(booth 2621) Ask for Mark Olen. Freebie: 3D viewer
Cadence Indago is Lip-Bu's answer to Aart's Verdi3 empire. Indago
debug works by adding Big Data Capture to Root Cause Analysis -- in
order to data mine your CDNS tool run logs -- to "highlight causality"
and correlations causing your bug in the first place. Does HW/SW bug
hunting. Analog Devices, TI, Bosch, Broadcom, Renesas, Siemens, ST.
(booth 1308) Ask Larry Melling. Freebie: Denali tix
CALIBRE, STAR-RC, & RIVALS
8.) NEW! -- Helic Pharos does EM risk-analysis. It analyzes EM isolation
between selected victim nets and all potential aggressors; does up to
100 billion pairs. Pharos does 2,000 ports vs. HFSS 30 ports. Gives
EM isolation "heat maps" with GHz frequency sweeps. Nothing like it
before. With Star-RC, Quantus QRC, Calibre-xACT. See ESNUG 584 #4.
(booth 1352) Ask Yorgos Koutsoyiannopoulos. Freebies: squeeze ball
Calibre nmDRC is the industry's DRC/LVS king with all 7nm tapeouts
today using Calibre for sign-off and they're developing 5nm. It
scales to 2K CPUs for designs and 10K CPUs for manufacturing. (See
ESNUG 577 #2 for this data.) TSMC, Samsung, GlobalFoundries, SMIC,
UMC, TowerJazz all use Calibre in vast, vast numbers of licenses.
Calibre Pattern Matching replaces text-based design rules with visual
geometry capture and compare. SRAM checking for TSMC 7nm are based
on it. Removes design patterns that are "yield detractors." Aimed
at 10/7/5nm designs. Also core to Samsung's Closed Loop DFM for
faster yield ramps. TSMC, Samsung, GlobalFoundries, SMIC, UMC.
(booth 2621) Ask for Michael White. Freebie: 3D Viewer
Cadence Pegasus DRC "massively parallel DRC engine" runs 900 CPUs.
Claims 8X/12X faster than old Calibre. For Innovus PnR, Pegasus does
signoff DRC, incrental DRCs, signoff metal fill, incremental metal
fill, timing-aware metal fill, and MPT decomposition for FinFETs.
This year it's "Cloud ready!" and "elastic and flexible computing!"
with both Amazon AWS and Microsoft Azure. For Virtuoso, Pegasus
does on-the-fly DRC and metal fill work, with no memory streaming.
Still uses olde factory certified Cadence PVS decks. Pegasus might
threaten Calibre when TSMC *finally* certifies the Pegasus decks.
Until then, not so much. Texas Instruments and Microsemi users.
(booth 1308) Ask for Manoj Chacko. Freebie: Denali party tix
Cadence Quantus QRC competes with Star-RCXT and Calibre-xACT. Does
multi-corner/statistical/inductance RLCK extraction, 16/14/10/7nm
Modeling, distributed processing, netlist reduction, SNA. Double
patterning, 3D-IC. 41 FinFET customers and 3 FD-SOI. Reliability.
Constraint validation. Works "in-design" in Innovus and Virtuoso.
This year Quantus is in Amazon AWS and Microsoft Azure clouds.
(booth 1308) Ask for Hitendra Divecha. Freebie: Denali party tix
Mentor Calibre-xACT does massively parallel full chip RLC parasitic
extraction without tiling. Processes entire net on a dedicated CPU.
No boundary and halo effects. "Attofarad accuracy with multi-million
instance digital or custom designs." Hybrid MOL/BEOL solver good to
7nm. Multi-patterning. Decks from TSMC, Samsung, GF available.
(booth 2621) Ask for Carey Robertson. Freebie: 3D viewer
Helic Exalto does 3D electro-magnetic (EM) crosstalk analysis and
signoff. Has killer capacity/speed/accuracy. 12 Ghz chip with EM
coupling through PWR/GND. 2.8mm X 700u, with AP, M12-M7. Extracted
in 36 hours on 20 cores. Exalto is the only EM sign-off tool that
can handle designs with 2,000 ports doing full RLCK extraction in
40 hrs with 16 CPUs and 150GB of RAM. With 32 CPUs, under 1 day.
Exalto works *with* Star-RC, Quantus, Calibre-xACT. Rivals Ansys
HFSS. Exalto users HiSilicon/Huawei, NXP, Nvidia, AMD, Qualcomm.
(booth 1352) Ask Yorgos Koutsoyiannopoulos. Freebies: squeeze ball
Synopsys Star-RC competes in extraction; unknown if showing at DAC'18.
Lorentz PeakView does 3D EM extraction and modeling. New vertical
inductance, multi-sheet extraction, and chip-package EM co-simulation.
Competes with Ansys HFSS. Users are Qualcomm, TI, TSMC, GF, Samsung.
(booth 1563) Ask for Jinsong Zhao. Freebie: mugs
Silvaco (Infiniscale) TechModeler takes IV curves from silicon or 3D
parasitic extraction and uses a neural network to make very accurate
behavioral Verilog-A models from a small sample size that can be
simulated in SPICE. It competes with Keysight's NeuroFET.
(booth 2429) Ask for Firas Mohamed. Freebie: water bottles
Silvaco Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
(booth 2429) Ask for Jean-Pierre Goujon. Freebie: water bottles
Mentor Calibre DESIGNrev is a fast GDSII & OASIS viewer/editor with
tight with Calibre. "Filemerge" to merge layouts for chip assembly.
(booth 2621) Ask for Joseph Davis. Freebie: 3D viewer
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. 22nm - 5nm.
(booth 1616) Ask for Coby Zelnik. Freebie: pens
Mentor Calibre YieldEnhancer fills both low nodes and complex analog
blocks. Now has push button ECO Fill solution. Synopsys IC Validator
and Cadence PVS competitors. ("Cadence Pegasus fill is not supported
by any foundry.") TSMC, Samsung, GlobalFoundries, SMIC, UMC are users.
(booth 2621) Ask for Jeff Wilson. Freebie: 3D viewer
Mentor Calibre PERC does circuit reliability verification, and is in
cell, block, and full-chip 3rd party sign-off flows to check for
common electrical failures such as Electrostatic Discharge (ESD),
Latch-Up, and Electrical Overstress (EOS). New extensions to
Calibre YieldEnhancer for net-aware and orientation-aware metal fill.
PERC end users are Xilinx, Broadcom, ST, ARM, Silicon labs. Foundries
that support PERC are TSMC, GlobalFoundries, Samsung, TowerJazz, UMC.
(booth 2621) Ask for Matt Hogan. Freebie: 3D viewer
Silicon Frontline R3D-DDM automatically generates a distributed model
of power devices for transient analysis. Rivals Star-RC, Quantus QRC
(booth 2363) Ask for Yuri Feinberg. Freebie: none
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process in 3-D. Virtual fabrication. To test
fab effects. It rivals Synopsys Sentaurus and Silvaco Victory.
Has new "Big Data" analytics. GlobalFoundries, Micron, IBM, Imec
Coventor MP creates finite element & reduced order models for MEMS
to go into MatLab, Simulink, Virtuoso, or Verilog-A SPICE.
(booth 1319) Ask for Stuart Truax. Freebie: laser pointer
EMULATION / ACCELERATION / PROTOTYPING
9.) Emulators in the Cloud is big this year for Veloce and Palladium.
Cadence Palladium Z1 is now the 2nd commercial emulator to be on
the Amazon AWS cloud, behind Mentor Veloce (ESNUG 583 #4), but
it's the first to also be on the Microsoft Azure cloud. Also new
this year is a faster Build-Allocate-Run-Debug loop, 2X faster
downloads, parallel partitioning compiles 3X faster with incremental
synthesis now incremental and parallel on up to 64 cores. Can do
offline debug for 100s of SW developers. Scales to 9.2B ASIC gates
for 2,304 simultaneous users in data center, water or air cooled.
Cavium, Fujitsu, Huawei/HiSilicon, ARM, Innovium, Marvell, Mellanox,
MicroSemi, MobileEye, Nvidia, Renesas, Socionext, Xilinx, Realtek.
(booth 1308) Ask Frank Schirrmeister. Freebie: Denali party tix
Mentor Veloce Strato claims whopping 15 billion gates capacity from
its new Crystal3 chip. (ESNUG 567 #1, 567 #3) 64 users. 50 kW.
This year's Sarokal buy adds emulation muscle in Automotive. It's
baby brother, StratoT, does 40 M to 1.25 B gates, 32 users, 17 kW.
Mentor Veloce 2 does 50+ MHz embedded SW execution with Warpcore and
Codelink. VirtuaLAB peripherals: 256-port Ethernet, PCIe Gen3, USB-3,
SATA, SAS, VJTAG. RTL-waveform debugger. Does ICE and Virtual.
Jean-Marie gloats Veloce 2 is 1st emulator on Cloud. (ESNUG 583 #4)
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon use Veloce 2.
Mentor Veloce Apps are tight with Ansys Apache PowerArtist. Its RTL
power reduction analysis is 4.5X faster. There 8 other Veloce Apps:
Coverage, Assertion, Deterministic ICE, ICE, Power, SW Debug, DFT,
and Ixia Virtual Network App. ST, Broadcom, Mitsubishi, HiSilicon.
(booth 2621) Ask for Jean-Marie Brunet. Freebie: 3D Viewer
NEW! -- after a 3 year wait, Synopsys EVE ZeBu-4 now being launched
claiming 2X faster than legacy Palladium and Veloce boxes. It's based
on same 20nm Xilinx Vertex UltraScale VU440 that Cadence Protium-S1
uses. Zebu Server 4 claims 19 billion gate capacity. Samsung users.
TLMs, power-aware, sim acceleration, ICE, synthesizable testbench.
Rumor is Intel swapped all of its Veloce boxes for Zebu Server 4's.
So far, no Zebu anything is known to be on any cloud this year.
(booth 1609) Ask for Manoj Gandhi. Freebie: pens
Cadence Protium-S1 FPGA-based SoC prototyper. Lip-bu's answer
to SNPS HAPS. Auto ASIC-to-FPGA memory conversion, automatic clock
synchronization to avoid hold-time violations and FPGA-specific
limitations, pre-P&R model validation. "quick bring up in 1-2 weeks
instead of 3-4 months." SCE-MI based transaction interface, memory
backdoors, start-stop-clock control and scripting for SW developers.
Protium-S1 can take in Palladium Z1 qtdb database to run 3X faster.
Nvidia, Mellanox, Microsemi, Marvell, Sony, NXP, Medtronic, Xilinx.
(booth 1308) Ask for Juergen Jaeger. Freebie: Denali party tix
Aldec HES-DVM is the poor man's HAPS. Uses UltraScale U440's. Claims
633 M gates. Auto partitioning, ASIC-to-FPGA clock conversion,
static/dynamic probes, memory viewer, HW breakpoints. Ethernet, USB,
USB-OTG, HDMI, I2C, SPI, RS232, GPIO, ARM Debug & JTAG. Users are
Qualcomm, Samsung, Fuji-Xerox. Now HES-DVM Cloud does does System
Verilog DPI-C TLM's, virtual SW, and ICE in the Amazon AWS cloud.
(booth 2628) Ask for Stanley Hyduke. Freebie: pens
ProDesign proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Stratix 10. 600 M ASIC gates.
20 Gbps. In 5 years ProDesign shipped 1251 units to 121 customers.
(booth 2428) Ask for Gunnar Scholl. Freebie: USB chargers
S2C Prodigy used to compete here, but S2C's not showing at this DAC.
Synopsys HAPS-80 and ProtoCompiler claims 1.6 billion ASIC gates
at 100 Mhz speeds from 64 total Xilinx Virtex UltraScale VU440's.
(booth 1609) Ask for Joachim Kunkel. Freebie: pens
Dini Group DNVUF4A -- ASIC prototype 4 Virtex UltraScale XCVU440's,
each with capacity of 116 million ASIC gates. Seamless stack 8 or
more of these boards to prototype 1 billion ASIC gates. 2,892 BGA.
16 GbE with no external Phy needed. GEN3 PCIe, SATA III, USB 3.0.
Dini Group DN_ReadBacker lets you read back the complete status
of your FPGA registers for debug. "No one else does this, John!!!"
(booth 2112) Ask for Mike Dini. Freebie: grumpy Mike sayings
MARGINs & ECOs
10.) NEW! -- Easy-Logic ECO Surgery does a new rewiring based functional
ECO's that super crazy small. "Minimized patching!" and "new ECO
patches sized just 1/100 to 1/1000 of manual". These guys won the
ICCAD CAD Contest three years in a row (2012, 2013, 2014) on this.
(booth 2155) Ask for David Wu or Sean Wei. Freebie: candies
Dorado Tweaker is a family of physically-aware ECO tools:
Dorado Tweaker-T1 vs. PrimeTime-ECO vs. Cadence Tempus-ECO
Dorado Tweaker-F1 vs. Cadence Conformal ECO
Static/dynamic power ECO's. 50 M inst. 16/14/10/7nm FinFET. Now
hierachical/timing/CPU/IR-drop ECO flows. Intel/GF/Samsung/TSMC
Broadcom, Qualcomm, LG, TSMC, Mediatek, Samsung, Xilinx users.
(booth 2417) Ask for JJ Hsiao. Freebie: magic LED ball
Empyrean ICExplorer-XTop physical MCMM timing ECO tool. PBA timing
fixes, route-based timing fix. 16/14/10/7nm 100M inst. 5X faster.
ClockExplorer does CTS clock analysis and constraint generation.
It helps cuts clock insertion delay. Marvell, HiSilicon users.
(booth 1449) Ask for Jason Xing. Freebie: cellphone kickstands
Cadence Conformal ECO Designer generates "congestion-aware ECO"
for "last-minute difficult ECO areas" for pre- and post-mask layout.
Users Broadcom, Qualcomm, ST, Samsung, Toshiba, AMD, Mediatek
(booth 1308) Ask Avinash Palepu. Freebie: Denali party tix
Synopsys PrimeTime ADV is all about distributed MCMM timing ECO's.
(booth 1609) Ask for Robert Hoogenstryd. Freebie: pens
PRIMETIME & RIVALS
11.) Cadence Tempus has new auto-partitioning of STA runs it calls DSTA.
"Does concurrent MMMC just like a regular Tempus STA run." Has been
used on 800 M inst production chips. "Does biggest STA jobs on lots
regular machines with normal memory limits" and "Cloud, too!" Again
5x faster than Primetime. ECO's, SI/crosstalk, too. 500+ tapeouts.
HiSilicon, ARM, TI, Inphi, NXP, Maxlinear, Lattice, Cypress, LG,
TSMC, GlobalFoundries, Intel, Analog Devices, Marvell, Qualcomm.
(booth 1308) Ask for Marc Swinnen. Freebie: Denali party tix
Synopsys PrimeTime-AI is hyped up Machine Learning, which it's calling
artificial intelligence now just to be "special". 5X faster overall
and power ECOs are 4X faster. Renesas on 40nm chips. PrimeTime-ADV
does physically-aware ECO's for timing, DRC, power recovery, POCV.
PrimeTime-SI claims killer crosstalk delay analysis and it's now "best
buddies forever" with Ansys RedHawk/SeaScape for IR-drop at PT-SIG.
(booth 1609) Ask for Robert Hoogenstryd. Freebie: PT dinner tickets
Arcadia TimeHawk STA last year claimed was first commercial timer to
bring artificial intelligence to timing signoff. Tool does timing
ECOs, 1+ M inst per minute, 2 billion capacity, SI/crosstalk effects.
(booth 1662) Ask for Joey Lin. Freebie: pens
SPICE / AMS / CHARACTERIZATION
12.) MENT BDA AFS was 5x-10x faster vs CDNS Spectre in ESNUG 495 #4 and 2x
faster than SNPS FineSim Pro in ESNUG 535 #3. 20+ M elements. TSMC
7nm certified. 2X faster. Now with Solido, has 10x faster throughput
for OCV vs. other SPICEs. BDA ACE for analog characterization runs.
AFS Mega does SPICE of 100+ M element mega arrays like memories.
Samsung, MediaTek, Intel, Broadcom, Qualcomm, NXP, Magnachip, SiLabs,
Fujitsu, ADI, Sony, LG, Magnachip, Panasonic, Skyworks are users.
(booth 2621) Ask for Giuseppe Oliva. Freebie: 3D viewer
Cadence Spectre-XPS is Lip-bu's comeback FastSPICE tool for memories.
Benchmarked 3-4X faster throughput than SNPS HSPICE in ESNUG 547 #3.
Has clever fast-or-accurate partitioning based on need. Multi-core.
(booth 1308) Ask for Tom Beckley. Freebie: Denali party tickets
Silvaco SmartSpice Pro is Dave Dutton's push into the memory
fastSPICE market. Claims "true SPICE behavior but with much faster
generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
designs with better waveform overlay results than other simulators."
Does 28/16/14/10/7nm. SmartSpice (golden), SmartSpice HPP (parallel).
Samsung, LG, Oracle use it. SmartSpice PRO for SRAM simulation.
(booth 2429) Ask for Colin Shaw. Freebie: tote bag
Empyrean (ICScape) ALPS claims "on average 2-5X speedup vs. 3 other
true SPICE simulators" which I guess are MENT BDA AFS, Spectre APS,
HSPICE. 3 million transistors and 30 million RCs. (ESNUG 572 #6)
HiSilicon, Kilopass, Monolithic Power Systems, Ricoh, Toshiba
(booth 1449) Ask for Jason Xing. Freebie: cellphone kickstand
ProPlus NanoSpice Giga big ass capacity parallel SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. Does 1+ B elements for 16/14/10/7nm FinFET or 28nm
FD-SOI. 10X faster vs. parallel SPICE. Samsung, Micron, eSilicon
(booth 2439) Ask for Lianfeng Yang. Freebie: cell phone clip
Solido ML Characterization Generator uses machine learning to cut
characterization time by 30-70% by generating Liberty models at new
conditions from prior Liberty data at different PVT conditions, Vt
families, supplies, channel lengths, model revs. NLDM, CCS, CCSN,
waveforms, ECSM, AOCV, LVF.
NEW! -- Solido PVTMC Verifier uses machine learning to simulate across
full combinatorial of process variation and operating conditions
together, at 100X speed, for interactions statistical variation & PVTs
interactions, ensuring full variation-aware design coverage.
NEW! -- Solido ML Characterization Analytics uses machine learning
to validate .libs, finding and visualizing trends in characterized
libraries. (booth 1344) Ask for Amit Gupta.
NEW! -- Cadence Legato Memory is a one-stop shop for all memory
design, verification, and characterization needs at advanced nodes.
Machine Learning, variation, yield, Monte Carlo, power network, LVF
(booth 1308) Ask for Joy Han. Freebie: Denali party tickets
NEW! -- Cadence DDR5 Prototyper does DDR5 controllers and PHY. JEDEC
to release DDR5 spec later this year. This is Cadence getting a jump
on that market. It works well with Micron's DDR5 prototype DRAMs.
(booth 1308) Ask for Marc Greenberg. Freebie: Denali party tickets
NEW! -- LibTech TurboChar competes against SiliconSmart and Liberate
to do std cell, IO, and SRAM characterization and modeling. Has
"massive parallelism", fast LVF/AOCV, improved auto-configuration.
Claims it improves linearly with more CPS, "does not level off like
queueing methods". (booth 1331) Ask for Mehmet Cirit.
NEW! -- Paripath Guna does std cells and IP characterization on
the Amazon AWS cloud. Did "20k cells characterization in an hour"
(booth 1612) Ask for Rohit Sharma. Freebie: trial license
ProPlus ME-Pro lets you benchmark fab processes and devices.
Compare multiple foundries/multi-processes down to 7nm. No scripts
nor SPICE licenses needed to do 100's of comparisons! Qualcomm
(booth 2439) Ask for Lianfeng Yang. Freebie: cell phone clip
Silvaco Jivaro does netlist reduction for SPICE sim acceleration.
Multithreaded for DSPF/SPF netlists. Speeds up Spectre by 3X. More
accuracy. OA DM5 is now supported. Silvaco Viso does quick analysis
of interconnect parasitics. Tight with Virtuoso. Silvaco Belledonne
does extracted netlist comparison -- for PDK optimization.
(booth 2429) Ask for Jean-Pierre Goujon. Freebie: water bottles
Solido Variation Designer does variation-aware design for PVT corners,
3 to 9-sigma Monte Carlo, hierarchical and sensitivity analysis.
Big thing is it cuts waaaaaaaay down on how many SPICE runs you need.
Good for memory, standard cell, analog/RF, custom digital. TSMC,
Broadcom, Nvidia, Huawei, Cypress, ARM, IBM. Solido was acquired by
Mentor, but still has their own booth! (booth 1344) Ask Amit Gupta.
Silvaco VarMan does Monte Carlo 3 to 8 sigma. Supports non-Gaussian.
Batch mode characteration of 100's of cells for you. 28nm FDSOI,
40 cells, 100 corners, Monte Carlo at each corner, 100's of measures,
took 173 mins using brute force MC and only 19 mins on VarMan. It
increases linearly to 6 sigma while claims Solido explodes hundreds
of times more to 6 sigma. ST Micro, Faraday, and Dolphin Integration.
(booth 2439) Ask for Prashant Singh. Freebie: water bottles
MunEDA WiCkeD analyzes SRAM cell/column/array, std cell, and analog
circuits for local variation to 9-sigma. Hierarchical and WCA.
FinFET, Bulk, Bipolar, BiCMOS. ST Micro and MunEDA published
silicon & bit cell analysis of 14nm FDSOI statistical BTI effects.
Samsung, SK Hynix, Infineon, Sanyo, Toshiba, and Altera users.
(booth 1463) Ask for Andreas Ripp. Freebie: tote bags
ProPlus NanoYield is variation analysis on yield vs. PPA trade-off.
It does High Sigma Monte Carlo. Licensed from IBM nine years ago.
Can handle 10,000+ variables and does up to 7-sigma. Used by SMIC.
(booth 2439) Ask for Lianfeng Yang. Freebie: cell phone clip
Empyrean (ICScape) XTime uses Big Data analysis to do "much faster
accurate Monte Carlo silicon timing sign-off." Does critical
path, sensitivity, and low power analysis. Design margin recovery.
(booth 1433) Ask for Jason Xing. Freebie: cellphone kickstand
VIRTUOSO & RIVALS
13.) Virtuoso 18.1 is a 2nd revamp. At CDNlive'16 Tom Beckley launched
his first revamp that where ADE Explorer was the old ADE-L, but had
nominal/corners/sweeps/monte carlo/spec comparison are in one tool.
ADE Assembler had multiple tests/statistical (from GXL). Problem
was his ADE Verifier -- Beckley was trying to get circuit designers
to do planning and design against design goals in analog/custom
design -- something they do NOT trust! (See ESNUG 560 #1)
Now with this 2nd revamp launched at CDNlive'18, his Virtuoso 18.1
"has new automation technologies with simulation-driven layout" and
"now does 5nm". Beckley really is pushing this design-against-goals
approach to the circuit designers yet again this year. Bosch user.
Beckley is now throwing in Sigrity into Virtuoso 18.1 to woo the
chip/package/PCB design flow guys -- an "It Does Everything" sale.
(booth 1308) Ask for Yuval Shay. Freebie: Denali party tix
Virtuoso + Innovus integration is a strong CDNS selling point against
Aart and Wally for those doing analog plus digital designs. Digital
on top / Analog on top approaches. "Both analog & digital in 5nm!"
(booth 1308) Ask for Yuval Shay. Freebie: Denali party tix
Mentor Calibre RealTime Custom does instantaneous sign-off DRC checks
and fixes inside Virtuoso, Laker3, Custom Compiler. Same deck, same
results as batch Calibre. 2-5X productivity improvement when fixing
DRCs in 180-7nm nodes. Double/triple patterning, preferred metal
direction, density checks, pattern matching and voltage-aware DRC.
Has cells/blocks-to-macros DRCs to automatically launching batch
Calibre jobs. Rivals Cadence iPVS. Qualcomm, Broadcom, SiLabs.
(booth 2621) Ask for Srinivas Velivala. Freebie: 3D viewer
NEW! -- Mentor Calibre RealTime Digital does instantaneous sign-off
DRC checking and fixing inside Innovus and ICC2. Same deck, same
engine and same results as batch Calibre. Like CDNS PVS (or Pegasus)
Interactive and SNPS ICV, but it's 40% to 85% faster. ESNUG 584 #1.
(booth 2621) Ask for Srinivas Velivala. Freebie: 3D viewer
Austemper KaleidoScope does mixed signal fault injection as functional
safety tool. It's ISO26262 automotive stuff working with OneSpin.
Just got acquired by Mentor. (booth 1420) Ask for Arun Gogineni.
Synopsys Custom Compiler is Aart's 2nd attempt on Lip-Bu's Virtuoso
monopoly. The 1st try was Custom Designer (which flopped.) CC runs
the old Laker3 router plus the Ciranova Helix plus some "assistant
features" to generate many different layouts of one circuit.
(booth 1609) Ask for Dave Reed. Freebie: pens
Silvaco Expert is a hierarchical IC layout editor. Schmatic driven.
10 Gig GDSII loads in "minutes". Uses Calibre Interactive for DRC
"on the fly". Rapid pan/zoom. Equal Resistance Router. OA and
interop PDKs (iPDK) makes design migration easier. And WTF???!!
Silicon Creations uses it for 10nm FinFET? Silvaco doing 10nm?!?
Also Silvaco Clever 3D RC field solver BEOL/MEOL parasitic extract.
(booth 2429) Ask Dave Dutton. Freebie: tote bags
Pulsic has tools in this niche, but is not showing at DAC this year.
Mentor Tanner is OA-based S-Edit schematic capture, L-Edit custom
layout, and T-Spice SPICE. Founded 1988. "Cost effective" prices.
The old HiPer Verify DRC was replaced by Calibre DRC. Pyxis in it,
too. They target MEMS designers like Obsidian, Microgen, Innotime,
Lewyn Consulting, Velankani, Eesy IC, Microdul AG, PragmatIC
(booth 2621) Ask for John Stabenow. Freebie: 3D Viewer
Silvaco NanGate Cello fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 16/14/10/5nm.
Also does coloring, self aligned MOL, template based cell creation.
(booth 2429) Ask for Jens Michelsen. Freebie: water bottles
LibTech LibChar does std cell, IO, SRAM characterization & modeling.
Now does PLLs. (booth 1331) Ask for Mehmet Cirit.
SCOOP! -- Movellus PLL/DLL/LDO Generator is kind of weird because it
creates *digital* versions of *analog* IP. In this case, it's PLL's,
DLL's, and LDO's. Why? Because then you can use *digital* synthesis,
STA, PnR on your PLL/DLL/LDO -- making them portable across nodes, and
you can do scan/ATPG/DFT on your PLL/DLL/LDO, too! (See ESNUG 582 #2)
So far at TSMC 16nm and Mo is working on 7nm. Intel Capital funded.
(booth 2120) Ask for Mo Faisal. Freebie: chocolates
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Work with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Intel, Broadcom, Qualcomm, Infineon, Bosch, Marvell, Toshiba, TSMC.
(booth 1322) Ask for Ranjit Adhikary. Freebie: yo-yo's
MunEDA WiCked CMT converts analog/mixed-signal/RF circuits across
different foundries/processes. Transistor resizing, optimization,
and verification for best performance, area, low-power/low-voltage,
robustness against process variation and mismatch. Qualified for
FinFET, Bulk, Bipolar, BiCMOS, and FDSOI. New GUI for migration
and yield optimizer, faster PVT corner runs and MC sampling.
WiCked Circuit Suite does transitor resizing for PPA, too. Users
ST, GF, SMIC, Novatek, Infineon, Fraunhofer, Chipus, Perceptia.
(booth 1463) Ask for Michael Pronath. Freebie: none
Empyrean (IC Scape) Skipper does super fast layout review, analysis,
debug, layout IP protection. 1TB GDSII. Marvel, Hisilicon, Sandisk.
(booth 1449) Ask for Jason Xing. Freebie: cellphone kickstand
Keysight ADS and GoldenGate is for silicon RFIC design & simulation
New iPDK PyCell & TSMC iRCX support, more intuitive layout, does
electro-thermal on windows, harmonic balance & circuit envelope
converges faster. Qorvo, Skyworks, Broadcom/Avago, Qualcomm users.
(booth 1623) Ask for Nilesh Kamdar. Freebie: tote bags
ClioSoft SOS ADS does design data management for RF engineers using
Keysight Agilent ADS. Northrop, IDT, Quorvo, Rohde & Schwarz, Inphi
(booth 1322) Ask for Ranjit Adhikary. Freebie: yo-yo's
Intento ID-Xplore resizing/biasing/migration of analog/AMS circuits.
(booth 2341) Ask for Ramy Iskander. Freebie: stickers
DESIGN COMPILER & RIVALS
14.) Mentor Oasys-RTL does crazy fast RTL synthesis floorplanning, design
space exploration from "place first methodology". 3-hour runtimes
synth to floorplan a 2M inst chip 4G of machine memory. Synth-ed
and floorplanned 14nm 3M inst in 8 hours. 3.8M 28nm in 12 hours.
Designers can look at different views (logical, physical, timing).
New built-in memory exploration cockpit to find the best mem config
in your chip. New integrated SQL dd to root-cause faulty RTL revs.
TI, Broadcom, Juniper, Qualcomm use Oasys. Xilinx Vivado is Oasys.
(booth 2621) Ask for Badru Agarwala. Freebie: 3D viewer
Cadence Genus RTL is an attack on Aart's 30 year Design Compiler
franchise. It's Anirudh's home-grown, massively parallel RTL and
physical synthesis tool that's "5X faster" than Design Compiler,
"1/2 iterations between unit and block/chip-level synthesis".
Genus got #4 "Best of 2017" with users in DAC'17 #4 and won a
user benchmark vs. DC-Graphical in ESNUG 582 #1. Broadcom, Texas
Instruments, Cienna, MaxLinear, Broadcom, Cisco, ImgTec are users.
"Hey, everyone! Genus RTL is on AWS and Azure clouds now, too!"
(booth 1308) Ask for Kam Kittrell. Freebie: Denali party tix
Synopsys demoing both Design Compiler Graphical and DC Ultra.
"Physical guidance to IC Compiler tightens correlation of timing,
area, and power to within 5% and speeds placement by 1.5X."
(booth 1609) Ask for Gal Hasson. Freebie: pens
RTL & GATE POWER
15.) Calypto PowerPro does RTL power optimization. Users see 9% to 12%
general Verilog RTL power savings. 37% cut in sequential logic power
saving in ESNUG 535 #2. Chatting up their "What If" ability with
to quickly understand power effects of potential mode, operating
environment or design changes "saving hours of turn-around-time".
PowerPro is only tool that's tight with Calypto SLEC-Pro sequential
EC. Verifies low power RTL tweaks are equivalent to original RTL.
Users gush about Calypto PowerPro, but quiet about Ansys PowerArtist,
or Synopsys SpyGlass Low Power, or Cadence Joules in DAC'16 #9.
Has ~85% correlation against gate-level. 16/14/10nm FinFET.
Qualcomm, TI, Samsung, ARM, HiSilicon, Google, Freescale users.
(booth 2621) Ask for Badru Agarwala. Freebie: 3D viewer
Apache PowerArtist users saw 3% to 10% reductions. Does automatic
and guided. Sequential and combinational clock-gating constructs,
memory light/deep sleep modes, and wasted power in datapath logic.
RTL power accuracy within 15% of sign-off. 10 M gates in an hour.
16/14/10/7nm. Handles 100M+ instances. Hooks with RedHawk for
power grid integrity. Also peak power & thermal hotspot analysis.
Has tight hooks into MENT Veloce emulation and Power App. Activity
streaming 10X faster vs. old slow FSDB for millisecs of activity.
Users are Broadcom, Nvidia, Samsung, ST, NXP, Toshiba, ARM, Ciena.
(booth 1637) Ask for Vic Kulkarni. Freebie: stuffed animal
Synopsys Atrenta Spyglass Power users got 9% to 16% power cut on
Verilog RTL. RTL, gate-level, or post-layout. FSDB, VCD, SAIF
and vectorless. Does ECO's, CPF, UPF, mem in sleep mode. ERC
checks on P/G netlist. Power modeling and coarse clock gating.
(booth 1609) Ask for Piyush Sancheti. Freebie: pens
Cadence Joules is an RTL power calculator. Estimates power at RTL
to 15% of signoff power, time-based power up to 20X faster. It has
as "power scrubbers". Joules works with Genus RTL and Palladium.
"Hey, everyone! Joules is on AWS and Azure clouds now, too!"
ARM, Broadcom, TI, Socionext, Renesas, Microsemi, Analog Devices
(booth 1308) Ask Rob Knoth. Freebie: Denali party tix
NEW! -- Innergy PAP does power modeling and fast 'what-if' power
exploration. Automatically builds characterized TLM power models
using tech library, RTL and simulation data. Cisco uses it.
(booth 2127) Ask for Ninad Huilgol. Freebie: baseball cap
Baum PowerBaum does static & dynamic RTL power analysis that's up to
"100X to 200X faster" vs. PowerPro/PowerArtist/Spyglass. "We couldn't
find a fast/accurate tool to do this, so we built one of our own!"
(booth 2454) Ask for Andy Ladd. Freebie: none
CDNS JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks to
see any issues the after the insertion of power management circuitry.
(booth 1308) Ask Pete Hardee. Freebie: Denali party tickets
RTL ENVIRONMENTS/SIMULATORS/TOOLS
16.) NEW! -- Metrics MCS is a System Verilog simulator written from the
ground up to be run in the cloud. It's fully compliant to the
IEEE 2012 SV spec, too. First user review at ESNUG 580 #2. These
hockey loving Canadians are pioneering the 4-cents-a-minute SaaS price
model in EDA. Theirs is the only known EDA tool on the Google Cloud.
(booth 1244) Ask for Doug Letcher. Freebie: paper notebooks
Synopsys Verdi3 is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 1609) Ask for Thomas Li. Freebie: pens
Verifyter PinDown auto debugs regression failures by IDing the
commits that cause the test failures and automatically assigns bug
reports to the engineers who made these commits. PinDown debugs
down to the exact line of code. Now instantly detect high-risk
code changes without any simulation. Samsung, Broadcom, Synopsys.
(booth 2355) Ask for Daniel Hansson. Freebie: chocolate kisses
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 1358) Ask for Chouki Aktouf. Freebie: candy
MENT Questa Platform bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, formal in one big smudgy bundle.
ISO 26262 certification, real number modeling, P1735 encryption.
(booth 2621) Ask for Gordon Allan. Freebie: 3D viewer
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
The Plot Viewer does simple/polar/vector graph and image/color map.
Python support using Cocotb GPI. This enables terse, readable,
maintainable code while providing easy Python abstraction to RTL.
(booth 2628) Ask for Stanley Hyduke. Freebie: pens
Amiq Eclipse DVT IDE is an add-on to VCS/Questa/Incisive that lets
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta like Visual C stuff.
Samsung, Intel, Broadcom, Qualcomm, Toshiba, SK Hynix, Micron.
(booth 1414) Ask for Cristian Amitroaie. Freebie: chocolates
Sigasi Studio is much like Amiq DVT. System Verilog & VHDL support.
This year added Visual respresentation and GUIs for documentation.
NXP, UTC, ASML, Thales Group, Thales Alenia Space, Airbus, Philips,
Rohde & Schwarz, Bosch, Siemens, Facebook, MacLaren, Easics, Harris,
Prodrive, Johnson & Johnson, SCD, ABB, Saab, BAE, EPSON, GE, Dolby
Laboratories, CERN, Fraunhofer Institute, Heidenhain uses it.
(booth 2352) Ask for Bart Brosens. Freebie: Belgian chocolates
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for registers/sequences into UVM/RTL. NASA, Intrinsix,
HGST, Icron, Conexant, Wipro, Conexant, John Deere, CERN uses Agnisys.
(booth 1345) Ask for Sameer Rahurkar. Freebie: stress balls
SystemC/C/C++/TLM STUFF
17.) Badru, Man with a Vision -- he's the MENT Calypto guy who's making
all that noise about his "C-based design Vision". (ESNUG 572 #5)
Mentor Catapult HLS synthesizes C++/SystemC into Verilog/VHDL to
target either FPGA or ASIC. Kicks ass at developing designs that
accelerate machine vision or do machine learning. Does top-down
and bottom up, cuts project times in half and verification costs by
80%. C->RTL visualizer. New libs and I/O for Xilinx and Altera
to crank clock frequency, plus hooks into Mentor Oasys-RTL.
Catapult Checker & Coverage does formal/lint checks on synthesizable
SystemC and C++ to prevent ambiguous or bad logic mistakes. Coverage
covers C statement, branch, toggle, expression, and array indexing; all
done hundreds of times faster than RTL simulation coverage. Qualcomm,
Nvidia, ST, Google, FotoNation, SeeCubic, Bosch, Fujitsu, Toshiba.
(booth 2621) Ask for Badru Agarwala. Freebie: 3D Viewer
OneSpin 360-SystemC auto checks array overflow, underflows, array
bound errors, uninitialized variables, divide-by-zero, illegal shifts.
(booth 2611) Ask for Raik Brinkmann. Freebie: cellphone grip
Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
RTL that Design Compiler or CDNS Genus can easily digest. Can do both
control logic and datapaths. Claims better accuracy than Catapult.
Hooks into CDNS Genus RTL synth, Joules low power, and Innovus PnR.
Supposedly can see PnR congestion issues in your SystemC/C/C++ source.
HiSilicon, NXP, Bosch, Samsung, LG, Realtek, Toshiba, Fujitsu, Ricoh
At one time Brett owned the C synth space, but Badru stole his crown.
(booth 1308) Ask for Brett Cline. Freebie: Denali party tix
NEC CyberWorkBench -- these Japan guys have been doing C/C++/SystemC
to Verilog/VHDL RTL synthesis since the beginning of time. Has an
ARM bus I/F generator and a Memory Mapped Register generator.
Mitsubishi, Renesas, Panasonic, Toshiba, Hitachi, Fujitsu, JVC users.
(booth 1437b) Ask for Kazutoshi Wakabayashi. Freebie: puzzle
Synopsys Synphony C plays here but probably not showing at this DAC.
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Rivals Synopsys Hector and Jasper EC.
Runs "bottom up" partitions. LSF support. Nvidia, Google, ARM users
(booth 2621) Ask for Badru Agarwala. Freebie: 3D Viewer
Fraunhofer COSIDE is a system level tool based on SystemC as well
as on SystemC AMS 2.0. Competes vs. Matlab Simulink or MENT Vista.
(booth 2412) Ask for Karsten Einwich. Freebie: cookies
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. It competes against Cadence
Virtual, Synopsys Virtualizer, Mentor Vista, and Wind River Simics.
NoCs. Fault injection. Linux, FreeRTOS, OpenRTOS, uC/OS, MQX, eCoS.
Now Imperas OVP has 40 EPKs, 170 CPU models of ARM, MIPS, RISC-V.
Users are ImgTec, Renesas, Recore, Altera, Audi, AMD, Nagravision.
(booth 2638) Ask for Larry Lapides. Freebie: USB charger
VERIFICATION IP
18.) Mentor Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet (400G, 100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I3C, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); FLASH Family (SDCard4.2,
SDIO4.1, eMMc5.1, ONFI4.0, Toggle, UFS, Parallel NOR, Serial NOR);
Display (CDC, DisplayPort, eDP, V-by-One, HDMI 2.1, HDMI 2.0,
HDMI 1.4, HDCP 1.4); HyperBus (Hyperram, Hyperflash); Auto (CAN,
CAN-FD, LIN); Mil-Aero (Spacewire, 1553b, PCI); 5G (JESD204B,
CPRI); Storage Family (SATA); NVMe over Fabric, Interlaken, I3C.
Oddly this is the exact same list from DAC 2017, so they've added
*nothing* new since the Siemens takeover???
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, Marvell, ST users.
"Oh, don't forget we have 1700 combinations of memory models, too!"
(booth 2621) Ask for Mark Olen. Freebie: 3D Viewer
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2, Ethernet 25G/50G, HBM, HMC,
MIPI DSI-2, WiFi MAC, CCIX, BLE5, DDR5" -- plus new "PCIe 5, HBM2,
LPDDR5, MVMe 1.3, CHI-B, UFS 3, USB 3.2, USB Type-C, DSI 2.0, I3C."
Denali-style API, all simulated VIP runs on VCS, Questa and Incisive.
"VCS or Questa customers do not need Specman e". TripleCheck.
Broadcom, HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung.
(booth 1308) Ask Moshik Rubin. Freebie: Denali party tix
Avery Verification IP (VIP) for PCIe Gen4, DDR4 LRDIMM/RCD2/DB2 and
3DS, MIPI CSI and DSI for C-PHY/D-PHY, eMMC 5.1, NVMe 1.2, USB 3.1
(Gen2) Superspeed+ and Power Delivery and xHCI 1.1, Unipro 1.6,
Soundwire, HBM, Toggle Flash, Automotive CAN, LIN, FlexRay.
NEW! -- DDR5, NVDIMM-P, CCIX, PCIe 4.0, AMBA 5 CHI, NVMe over Fabric,
HDMI, DP/eDP, I3C, SAS 24G -- plus new PCIe 5.0, Ethernet 400G, CCIX,
Gen-Z, UFS 3.0, I3C. "It runs on Cloud, too!" and "Use all 59 VIPs
with one license!" HiSilicon, Samsung, Broadcom, Xilinx, Marvell.
(booth 1508) Ask for Chris Browy. Freebie: cellphone mount
SmartDV VIP claims "many VIP and sim acceleration IPs." (booth 2313)
Oski sold VIP last year, but apparently not this year. (booth 2319)
HARD & SOFT IP
19.) ARM is showing a new Cortex-A76 CPU, Mail-G76 GPU plus its 32/64-bit
RISC CPUs, memory IPs, Artisan std cell libs, plus ARM Socrates
for IP configuration & SoC assembly, plus ARM Coresight/CoreLink
"Hey! You engineers! STOP looking at those damn RISC-V cores!"
(booth 1628) Ask for Simon Segars. Freebie: pens
SCOOP! -- scroll up to "Virtuoso & Rivals" section of this list to
see the Movellus PLL Generator, DLL Generator, LDO Generator tools.
Synopsys is showing its Virage DW ARC 600 & 700 cores, plus its
mem IP, plus std cell libs; that all directly compete against ARM.
DW ARC HS4x and HS4xD processors. 6000 DMIPS per core. Security.
ARC now has 226 customers. DW ARC comes in low power and audio.
"Hey! You engineers! STOP looking at those damn RISC-V cores!"
(booth 1609) Ask for Mike Thompson. Freebie: pens
NEW! -- RISC-V Foundation is showing all players in the grassroots
revolution to make CPU cores on a free open system architecture.
(booth 2638) Ask for Krste Asanovic. Freebie: RISC-V itself
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
This year says it has new fully verified/certified PCIe 5.0 rev 0.7.
(booth 1308) Ask for Rishi Chugh. Freebie: Denali party tix
Silvaco Xena scans a chip-level database to list all detected IP and
versions of that IP. Works for embedded SW, too. It scores the
extent to which IP exists in the chip, from its entirety to fragments.
(booth 2429) Ask for Warren Savage. Freebie: water bottles
Silvaco NanGate IoT Std Cell Libs are "IoT optimized" full custom
libraries. 9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm silicon
proven. Cut area by 8-14%. "Our 8T 28nm GF lib got 55% higher raw
gate density." (booth 2429) Ask for Jens Michelsen.
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precisionv clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 1652) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 encoders, JPEG IP. New Geon "secure" uP, J2716, MIL-STD 1553.
(booth 1509) Ask Nikos Zervas. Freebie: stylus pen
Omni Design sells ADCs, DACs, bandgaps, oscillators, LDOs, temp
sensors. 28nm to 180nm. For IoT. (booth 2450) Ask Denis Daly
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". Now multiple proven 7nm PLLs this year.
Avago, TSMC, SMIC, UMC, GlobalFoundries, Samsung, ARM, DongBu, Toshiba
(booth 2325) Ask for Andrew Cole. Freebie: USB car chargers
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 16FF+. (booth 1425) As for John Maneatis.
BIG DATA & ANALYTICS
20.) IC Manage Envision is a tapeout predictor based on Big Data. It was
the #1 Cheesy Tool of DAC'15. After data mining 2 years company-wide
man-hours and 28nm EDA tool run logs, Xilinx used Envision to predict
their Zynq 20nm migration tapeout to within +/- 1 week. ESNUG 550 #1.
Verification Dashboard of job submissions to LSF, with real-time job
monitoring, results parsing, historical analysis, aggregated
analytics. Dynamic Graphs, custom field expansion.
NEW! -- Envision Analytics uses big data for real-time analytics for
multi-vendor verification environments. It's like Cadence Indago but
it lets you add in non-CDNS tools, too. 10-100X speed up. Visual,
interactive reporting for regressions, bugs, and coverage. Results
linked to relevant design activity to help ID & resolve bottlenecks.
(Booth 2618) Ask for Steve Klass. Freebie: chocolates
TEST/SCAN/BIST/JTAG/FAULTS
21.) Here's why Wally's test brainiacs beat out Aart in ATPG/scan test.
Mentor TestKompress does hierarchical ATPG. Patterns are generated
independently for each core. Can be retargeted at chip top-level.
10x faster generate time and 1/10th CPU time of Synopsys TetraMAX.
Pattern count is 1/2, so less test time. Also this core-level ATPG
means no wait for whole design to be done before ATPG generation.
TestKompress does end-to-end hierarchical, which takes DFT out
of the critical path, reduces ATPG and diagnosis runtime by 10X,
and pattern count by another 2X. Users are Broadcom, NXP, Renesas,
On Semi, Intel, NXP, Mediatek, Spreadtrum, and Annapurna Labs.
Mentor Tessent ScanPro places test points in netlist for compression.
Adding 1%-2% area for a 3X to 4X reduction in ATPG test patterns.
If 100X compression with Synopsys TestKompress, Mentor ScanPro gets
300X to 400X. New VersaPoints for hybrid ATPG/BIST coverage. OCC
insertion, X-bounding for logic BIST. Improves logic BIST coverage
by 2%-4% and gets to 90% coverage 8x faster. ISO 26262 likes this.
(booth 2621) Ask for Steve Pateras. Freebie: 3D viewer
Cadence Modus Test does scan insertion, compression, ATPG,
logic and memory BIST. Physically aware 2D elastic compression
that cuts test logic wirelength by 2.6X. Compression ratios of
400X. Takes 1/3rd tester time. Works with CDNS Genus RTL synth.
PMBIST. Soft programmable test for FinFET SRAMs and automotive.
Higher coverage with shorter test time and because of hooks into
Innovus/Genus it has lower routing congestion, fast yield ramp.
Texas Instruments, GlobalFoundries, Microsemi, Sequans users.
(booth 1308) Ask for Rob Knoth. Freebie: Denali party tix
Mentor Tessent MissionMode does hardware functional safety stuff by
system-level low latency access to on-chip test resources for on-
line test and diagnosis. Non-destrictive memory tests, too. Works
with Tessent LogicBIST and MemoryBIST or other IJTAG test IP.
Mentor Tessent DefectSim does transistor-level fault simulation for
analog, mixed-signal, and non-scan digital circuits when test quality
must be measured, or improved, or maintained while test cost is cut.
It automatically calculates all necessary ISO 26262 hardware safety
metrics like SPFM, LFM, DC and PMHF. Users are On Semi, AMS AG.
(booth 2621) Ask for Matthew Knowles. Freebie: 3D viewer
Mentor Tessent Diagnosis and YieldInsight uses failing test data to
find logic & physical layout yield problems "in days, not months."
Spots systematic yield issues at transistor level. Samsung, Cypress.
Mentor SiliconInsight ATPG used to be memory/logic BIST diagnosis
through a JTAG port. Now uses $100 USB port to access 100 pins.
Find which scan cells failed or co-ordinates of defects. Debug
ATPG, MBIST, LBIST and IJTAG issues without valuable ATE time.
(booth 2621) Ask for Matthew Knowles. Freebie: 3D viewer
Synopsys SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
(booth 1609) Ask Kiran Vittal. Freebie: pens
Synopsys (WinterLogic) Z01X Safety does fault injection and simulation
(DC, AC, transient faults) for ISO 26262 and IEC 61508 compliance.
Works with SNPS Certitude and rivals CDNS Verifault-XL. User Denso.
(booth 1609) Ask for Debashis Chowdhury. Freebie: pens
ROLL-YOUR-OWN EDA SOFTWARE STUFF
22.) Verific sells System Verilog, VHDL, UPF parsers with C++ interfaces
to EDA developers. Perl and python APIs. Synopsys, Cadence,
Mentor, Ansys, Xilinx, Altera, AMD, Nvidia, Infineon, Samsung users.
Now rolling out Invio, a collection of high-level Python APIs that
make it easier to interface with their core Verific parsers.
(booth 2311) Ask for Michiel Ligthart. Freebie: stuffed giraffe
Mirabilis Collaborator generates docs and javascript for executing
models within a web browser. Used as specification or a customer
demonstration tool. Does parameter/algorithmic/topology changes.
Has ARM Cortex A76 sim model "even before Synopsys or ARM itself!"
(booth 2110) Ask for Deepak Shankar. Freebie: smiles
OneSpin 360 LaunchPad lets companies with no formal tools develop
and deliver formal-based apps inside their own in-house EDA SW.
(booth 2611) Ask for Raik Brinkmann. Freebie: cellphone grip
WORKSPACE, DESIGN DATA MANAGMENT, & IP TOOLS
23.) OpenText (Hummingbird) ETX gives you secure remote access to UNIX or
Windows apps in the datacenter. Competes against VNC, RDP. ETX has
20-50% faster response time than VNC for most UNIX apps. Can handle
high latency access (up to 165 msec) pain free for the EDA tool user.
Support for Nvidia GRID-optimized virtual desktop infrastructure.
(booth 1424) Ask for Mark Wevers. Freebie: cellphone kickstands
ClioSoft designHUB is a data management tool where project engineers
can create and upload IPs, browse, search, and compare available IPs,
easily track the IP lineage, issues, defects and their resolutions.
"A one-stop-shop for all designs within your company immaterial of
where the design data is physically located." Claims SOS, Perforce,
Git, SubVersion "or any network storage." Skyworks uses designHUB.
(booth 1322) Ask Ranjit Adhikary. Freebie: yo-yo's
IC Manage GDP design & IP data management system lets digital/custom
designers find, modify, release & track design data through tapeout.
Bug interdependency management. Multi-tier web stuff. Samsung, AMD,
Intel, Xilinx, Nvidia, Nokia, Northrop Grumman, Viasat, Qualcomm.
NEW! -- IC Manage GDP XL-Git takes GDP design & IP data management
system into hybrid version control with Git API. Combines best of
central & distributed version control. 10x speedup. (ESNUG 582 #3)
(booth 2618) Ask for Alex Tumanov. Freebie: chocolates
ClioSoft SOS7 does HW configuration management and rev control for
Virtuoso, Laker, Pyxis, Custom Compiler, Keysight ADS. Built-in IP
management and reuse. Does soft integrations with in-house flows.
Better security, improved IP traceability, Jenkins integrations.
"SOS7 now supports the cloud, too!" Hooks to JIRA, Trac, Bugzilla.
Huawei, Google, Analog Devices, Infineon, Toshiba, Marvell, TSMC
(booth 1322) Ask for Ranjit Adhikary. Freebie: yo-yo's
NEW! -- Circuit Devs CDT does secure Amazon AWS cloud based data
design manament. "Enables small chip design companies and startups
to enjoy the benefits of DDM without the CapEX and OpEx of DDM."
(booth 2133) Ask for Marius-Paul Dumitrean. Freebie: USB dongle
Mentor Questa VRM is verification run management system that combines
coverage metrics from formal, CDC, simulation, and emulation engines.
Accellera UCIS standard, and Jenkins regressions. Nokia & Micron.
(booth 2621) Ask for Mark Olen. Freebie: 3D viewer
Cadence vManager is just like Questa VRM, but has an API bug systems,
source systems, or agile development systems. Very verificationy.
Deep hooks with Cadence Incisive, Palladium, Xcelium, and JasperGold.
Fujitsu, Analog Devices, ST, Qualcomm, Allegro, Infineon, Teradyne.
"Hey, everyone! vManager is on both AWS and Azure clouds now, too!"
(booth 1308) Ask for Larry Melling. Freebie: Denali party tickets
Methodics Percipient is a "new graph database providing customers 5X
performance improvement in IP data management and analytics." It
also does "issue and defect management and requirements management".
Samsung, Micron, Silicon Labs, Cirrus Logic all use Percipient.
(booth 1653) Ask for Simon Butler. Freebie: live jazz music
Fractal Crossfire does format consistency checks on hard IP? Huh?
(booth 2333) Ask for Felipe Schneider, Freebie: none
Empyrean (ICScape) Qualib also does format consistency checks on hard
IP? But whatever it is, Marvell, SMIC, and HiSilicon use Qualib.
(booth 1449) Ask for Jason Xing. Freebie: cellphone kickstand
SUSE OpenStack Cloud and SUSE Manager manages server farms running
CPU-hungry Calibre and VCS runs. (booth 1237) Ask Eric Jaeger.
Univa Grid Engine does data center resource management like LSF. Has
a licence orchestrator built-in, too. (booth 1255) Ask Neil Bendov.
Amazon AWS is easily the #1 lead host for EDA tools. (booth 1239)
Microsoft Azure is now the #2 host for EDA, but not showing at DAC.
Google Cloud is a distant #3 host for EDA tools. (booth 1251)
IBM Cloud is very distant #4 mostly for IBM tools. (booth 1252)
Alibaba Cloud only in China and is unknown in EDA. (booth 1248)
Anyway, I hope this helps! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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