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\ - / INDUSTRY GADFLY: "The Top 3 of my Cheesy Must See List for DAC 2024"
_] [_ by John Cooley of DeepChip.com
EDITOR'S NOTE: Here's the Top 3 of what I'll be checking out at DAC'24.
I'll put up the entire Cheesy Must See List on DAC Monday. - John
NEW SCHOOL RTL SIMULATORS
1.) Metrics DSim Cloud Simulator -- when Joe Costello told me his Metrics DSim was on
par with Xcelium/VCS/Questa, I was skeptical. So, I asked a buddy who has access
to currect revs of those Verilog simulators to benchmark Metrics DSim against them:
open source Metrics Cadence Synopsys Siemens
design DSim Xcelium VCS Questa
--------- ------- -------- -------- --------
Ethmac 0:40 sec 0:14 sec 0:51 sec 0:29 sec
Pci 1:17 0:39 0:57 0:48
vga_lcd 5:52 3:39 6:00 6:12
Notice how DSim's runtimes are on par with VCS and Questa, and it's only 1/2 speed
of Xcelium -- that is, DSim is comparable to a Big Three EDA simulator.
Why this is #1 on my Must See List this year is that Metrics is handing out their
desktop DSim simulator for free. Yup, instead of shelling out $20K to $30K for a
single license for a year -- like with CDNS/SNPS/SIEM -- you can download & run DSim
on your on-prem machine at no cost. No hidden gotchas, no expiration dates. And
it's not limited by # of lines of Verilog, nor gate count, nor your machine size.
You only pay if/when you decide to run DSim in the cloud for extra oomph. It's push
button and costs only 1.5 cents/minute/server. The numbers: running DSim 24/7/365
in the cloud for a whole year sets you back only $7,884. But the BIG payoff is when
you want to use the cloud run your regressions FAST.
Plus, because of distributed jobs "cloud magic" -- running 1 Verilog simulation on
DSim on 1 Azure server for 10 hours costs the same as 100 Azure server for 1 hour.
1.5 cents X 1 server X 10 hours == 1.5 cents X 100 servers X 1 hour == $90.00
But the real benchmark: my same user buddy who ran the original benchmarks tested
this out. He gets even faster (~80X) runtime speed-up in the Azure cloud because
of, again, that distributed jobs "cloud magic":
wall clock time DSim cost
--------------- ---------
1,500 test cases on 1 on-prem server 10 hours free
1,500 test cases in the cloud 7 minutes $8.90
He'd have to pay $$$$ millions for 1,500 licenses to do this with the Big 3 vendors.
I asked Joe: "But why free??". His answer: "Metrics is flipping the EDA business
model on its head. No more choking on license fees. Making a license free removes
our barrier to entry. No purchase orders, no red tape. For chip designers at
small to mid-sized companies, FPGA designers, and students, my free DSim is an
immediate gift for their daily HDL coding, debugging, and small designs. Everyone
can try it, love it -- and then get hooked on the cloud's unlimited fast and cheap
compute power -- free from the usual Big 3 EDA license stranglehold."
"Bottom line, using my DSim saves everyone a ton of time and money," added Joe.
(booth 2548) Ask for Joe Costello. Freebie: a free Verilog simulator
BUGHUNTERS
2.) NEW! -- Real Intent Sentry is a totally new static (rules based) signoff tool for
hardware security. It looks for "holes" in your design where malicious code could
sneak in, be executed, and do bad things. Sentry rivals the full formal tools
like the CDNS Jasper Security Path App and SNPS VC Formal FSV and DPV.
The Big-Bang-For-The-Buck here is the runtime and expertise differences between
these 3 tools. The full formal tools from CDNS & SNPS need 12 months to formally
evaluate 100 million gates with a Herr Doctor Formal PhD at the customer driving
it to correctly "mathematically prove" your design with 100% accuracy.
In contrast, Real Intent Sentry's static analysis of 100 million gates is 5 hours;
but static analysis is noisy with false positives -- so it'll take an added 3 weeks
of a regular engineer doing reviews and waivers.
So 3 weeks + 1 normal engineer vs. 12 months + Dr. Formal's time? 3 weeks wins!
I asked Prakash why can't Cadence and Synopsys just have their own RnD create their
own static analysis tools. "It took us 15 years to develop our level of static
analysis expertise; I don't think they [CDNS/SNPS] could duplicate it easily."
(booth 2625) Ask for Pratik Mahajan. Freebie: LED pens
SILICON LIFECYCLE MANAGEMENT
it will be new 3.)
X.) Synopsys Silicon Lifecycle Management (SLM) is SW plus embedded DW IPs to do
SLM of your chip. SLM In-Chip Monitor IP tracks your chip's analytics on every phase
of the silicon lifecycle -- from initial design, to manufacturing, to in-field data.
It does pre- and post-silicon analytics, plus hooks with Synopsys TestMAX. Users
are Intel, Marvell, Microsoft, Qualcomm, ST, Alibaba, ARM, Google, Amazon, MediaTek,
Cisco, ST, Socionext, Marvell, Bosch, Arbe Robotics, Denso. The Synopsys SLM rivals
are Siemens Tessent, Proteantecs, and PDF Solutions Exensio/Cimetrix. (Not sure but
it looks like much of Synopsys SLM is a deep rebranding of Synopsys SiliconMAX.)
NEW! -- Synopsys SLM HSAT IP takes PCIe and USB interfaces to be re-used for high-
bandwidth production scan test. Also manufacturing scans in-system. Also later
in-field scans, to find structural degradation during the device's lifetime.
NEW! -- Synopsys SLM SHS IP automatically creates a hierarchical IEEE 1500 network
to access and control all IP/cores at the SoC level. It's a network for all SLM IPs
on-chip like PVT monitors, sensors, clock delay monitors plus XLBIST -- plus SMS as
well as chiplet interconnects like IEEE 1838. ST, Socionext, Marvell, Bosch users.
(booth 2441) Ask for Ash Patel. Freebie: LED pens & coffee
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens Tessent SLM is also SW plus embedded IP to track reliability/performance of
your silicon/package/PCB as it goes through its full lifecycle -- you know, SLM stuff.
Siemens Streaming Scan Network (SSN) is an embedded "test data super highway" IP inside
your chip. "All SLM starts with test -- and our SSN is the backbone that drives
packetized 100% payload scan data to your chiplet or multi-die design." DFT planning
is decoupled from design for faster TAT. SSN cuts your power profile by reducing
IR-drop. It tests identical cores with on-chip compare. Lets you tune your clock
timing for fast silicon bring-up. SSN is a beginning-of-life SLM tool. It's about
catching defects and scan testing early -- also while trying to suss out early
manufacturing & aging defects, too. Intel, Amazon, Broadcom, Qualcomm, Samsung, ARM
Siemens Tessent MissionMode is on-chip infrastructure to enable chips to test and
diagnose themselves at any point during functional operation and throughout their
silicon lifecycle. It has system-software based access to any test (and diagnosis)
within an SoC. Makes ISO 26262 possible. Does long-term reliability requirements
for many types of devices beyond just automobles like 5G base stations, satellites,
and aircraft cockpit electronics. Tessent MissionMode is a late-in-life SLM tool.
Siemens Tessent Embedded Analytics is also a bucket of monitor IP plus software that
"non-intrusively observes if your SoC functionally performs as it was meant to."
Full visibility in HW/SW interactions in deployed systems. Tessent EA is about
answering functional HW/SW questions like "why is new version of my SW now running
so slow?" or "why did my system hang in reboot?" Tessent EA is the quintessential
definition of a late-in-life SLM tool. Seagate, Kalray, Picocom users.
(booth 2521) Ask for Lee Harrison. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
MAYBE? -- I got very specific hints that a Cadence SLM was coming from slides at
CadenceLive'24 -- in the middle of all that buzz about "Digital Twin" ...
"Digital Twin" is the stealth hot-new-thing at CDNS and SNPS this year
... but don't know if Anirudh will be stealth chatting Cadence SLM at DAC'24 or not.
(booth 1511) Ask for Anirudh Devgan. Freebie: CDNS SLM rumors (maybe?)
EDITOR'S NOTE: Again my full Cheesy Must See List is up on DAC Monday. - John
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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