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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2005"
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by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Every year when I go to DAC a small army of people ask me the extremely
predictable questions of "What's hot at this year's DAC?" and "What are
you going to look at, John?". So instead of having to repeat this same
conversation over and over again while I'm at DAC for 5 days, I've decided
to share My Cheesy Must See List for DAC 2005 with the DeepChip readers.
(You might want to print out a hard copy of this to use as an unofficial
guide to the DAC floor next week.)
1.) Sierra Pinnacle OCV (booth 101) -- The big noise Sierra is making
this year at DAC is their "Pinnacle OCV" tool. It's not really
a tool; they just added OCV to Pinnacle. In a nutshell, Sierra
says that Synopsys IC Compiler works by doing repeat runs for each
PVT mode; Pinnacle OCV has an internal database that lets it run
for lots of modes *simultaneously* -- so while IC Compiler may
take days to run all these individual modes; Pinnacle OCV can do
it in hours. At the Sierra booth ask for Shankar Krishnamoorthy
or Pravin Madhani. While at the Synopsys booth, ask for Jafar
Safdar or Mark Bollar for questions about IC Compiler.
2.) IBM (booth 1990) -- the wonderkids at IBM have added *statistical*
timing analysis to EinsTimer claiming to get up to 15% better
performance over PrimeTime's *static* timing analysis. (Too bad
EinsTimer is only for IBM fab chips.) Ask for Dale Hoffman.
Blade (booth 845) is a bunch of ex-Barcelona guys offering StatTime
beta for 90 & 65 nm designs. Ask for Khanh Le or Stefan Gradinaru.
Extreme DA (booth 578) is a small 4-man Lucio Lanza backed start-up
that has an interesting statistical timer, too. It's called "XT"
and it's focused on OCV and yield. Ask for Mustafa Celik.
Once I've done these 3, I'd go to Synopsys (booth 1088), hunt down
Rajiv Maheshwary and ask him: "Hey, why doesn't PrimeTime do any
*statistical* timing analysis yet? These 3 others have it."
3.) Cadence (booths 1308 & 172) -- In gossip mode, I've heard it said
that Cadence is backing off of DAC. The idea is Corporate Marketing
wants to funnel the customers into their new "CDN Live" conference
so users aren't distracted from a 100% Cadence-centric message; sort
of like Intel's "Intel Developer Forum" where you don't see any of
those pesky AMD Opterons ruining things. Rumor has it Cadence
bailed on their DAC booth 172, only keeping booth 1308. Either way
it'll be more of a question of *which* of the *many* Cadence tools
you *won't* be shown at DAC this year.
Anyway, the first thing I'd do in the Cadence booth is to hunt
down Yoav Hollander, the father of Specman "e", and ask him about
the Cadence future of "e", SystemC, System Verilog, the old
Verisity verification libraries, etc. If anyone knows, he does.
After that, I'd hunt down Mike Vachon and Mick Tegethoff to ask
them about the neat IBM test stuff incorporated in Test Encounter.
(At SNUG'05, a user who I respect a lot said the Cadence Test stuff
was more interesting than the Mentor and Synopsys test suites.)
4.) Magma Cobra (booth 2250) -- this is the new release of Magma's Blast
family of tools. They've been yarping about it since April, but this
is the first time I can see it demoed. Magma claims to have a 65 nm
customer tape-out, but won't say who. Cobra consists of 11 different
sub-products covering everything from P&R to scan to extraction to
yield to OCV to statistical timing analysis. Ask for Samir Patel.
5.) Blue Pearl (booth 148) vs. FishTail (booth 2152) -- Yea, I know the
FishTail Focus story about how they automatically find your design's
golden RTL timing contraints, yada, yada, yada... FishTail's been
telling this story for years. What's new is Blue Perl is now also
singing very that same song, too. Ask for Ajay Daga at the FishTail
booth. Don't know who to ask for at the Blue Pearl booth.
6.) Forte (booth 1317) vs. Mentor Catapult C (booth 1800) -- All this
SystemC stuff is a bunch of hooey if it doesn't translate to gates.
Yes, I have a chip *design* bias here, so I'm naturally curious
about Forte Cynthesizer, which has the passion and the history,
vs. Catapult C, which has Mentor big bucks backing. At Forte, I'd
talk to Brett Cline; at Mentor, I'd talk to Shawn McCloud.
7.) Prolific (booth 934) and Zenasis (booth 1390) -- both of these
have fairly mature tools that cleverly speed up slow paths in
your standard cell designs. Neat stuff. At Prolific it's called
"ProTiming" and I'd ask for Paul de Dood about it. Also see
ESNUG 445 #3. At Zenasis it's called "ZenTime" and I'd ask for
Sunil Mudunuri about it. Also see ESNUG 441 #9.
8.) Magma Mojave (booth 2250) vs. Mentor Calibre (booth 1880) -- ever
since Magma Mojave Quartz DRC pummeled Mentor Calibre in that user
benchmark in ESNUG 445 #12, #13, #14, I've known I'd want to see
the Mojave demo and then the Mentor Calibre reply. At Mojave, I'd
see Jonathan White; at Mentor I'd see Tony Nicoli.
9.) Mike Fister, CEO of Cadence (maybe in booth 1308?) -- fabulously
wealthy, immensely powerful, and weirdly hermit-like, Fister is
the Howard Hughes of EDA. For the Cadence olde guard EDA veterans,
he's a terror because he's replacing them with Intel loyalists.
And why is the guy such an infamous no-show at EDA public events?
Is it his whim? Or are his handlers hiding something? If I had
my wish, I'd love to do an on-camera interview of Mike Fister at
DAC (like I did with Mike Santarini) but I know it ain't gonna
happen. Heck, his handlers won't even let me see him off-camera!
They say that Howard Hughes liked to watch the 1968 movie "Ice
Station Zebra" hundreds of times, over and over again. Maybe I
should FedEx a copy of it on DVD to Fister as a goodwill gesture.
10.) Gigascale InCyte (booth 1821) -- They've been boasting that they've
gone from 6 users to 1,400 users in the 4 months. I have my doubts
about this since Monterey, AmmoCore, and Synopsys Chip Architect
failed miserably in the floorplanner/estimator market. But, then
again, First Encounter is said to be The-Product-That-Saved Cadence.
So maybe there might be something to this Giga boast. I'd talk to
Adam Traidman at Giga to find out what's up here.
11.) Synopsys (booths 1088 and 700) -- I'd first go to booth 1088 to
see what all this broohaha is about how they killed off wireload
models in DC 2005 and backdoored in PhysOpt lite. Then I'd go
to booth 700 (which is really the old Nassda booth) to see who
won: homegrown Synopsys NanoSim or not-invented-here Nassda HSIM?
I've also heard that Synopsys (like Cadence) will be backing down
from it's DAC presence this year; it'll be fun to see what products
Synopsys de-emphasizes by no-showing them at DAC this time around.
"Hey, I noticed you're not demoing XYZ this year? Does this mean
you've decided to end-of-life XYZ now?" Try it! It's fun!
12.) Mentor Calibre DFM (booth 1800) and Ponte (booth 111) -- Because of
its size and Calibre history, I feel that Mentor will be a very
serious force in the DFM/DFY business. I could be wrong, but my
gut says I should look to these guys for this. I'd ask for David
Abercrombie about Calibre DFM. I'm also keeping an eye on Ponte
Solutions in DFM/DFY because Nitin Deo went there. Nitin has an
excellent track record of joining successful start-ups.
13.) All the other DFM/DFY vendors -- there's a fruit cocktail of mostly
newbie "yield" guys here: Aprio (booth 2040), Pyxis (booth 1157),
Blaze DFM (booth 2229), Clear Shape (booth 558), Nannor (booth 166),
Sigma-C (booth 1841), and ChipMD (booth 471). Even good olde BIST
LogicVision (booth 540) is trying to re-invent itself as a Yield
house. (And this being the Year of Yield, I was surprized to see
HPL was a no-show at this year's DAC.) Magma (booth 2250) has a
yield demo under NDA. It's rumored to have a lot of Mojave and
PDF Solutions stuff in it -- ask for Samir Patel.
14.) Apache PsiWinder (booth 409) -- is a Spice-based (vs. static timing
analysis based) critical path timing and clock tree analysis tool.
They claim it considers both crosstalk, dynamic voltage drop, and
ground bounce noise concurrently. It appears to be an interesting
alternative to PrimeTime-SI and CeltIC. Ask for Yukari Chin.
15.) Structured ASIC/FPGA -- Synplicity (booth 371) has some interesting
physical synthesis that Ken McElvain himself has been working on,
while ViASIC (booth 136) does his P&R. See Kiyosi Isihara of ViASIC.
Magma (booth 2250) also claims to have physical synthesis, but they
can P&R their own output. Ask for Behrooz Zahiri at Magma.
16.) Semantic Design (booth 501) -- Their Thicket source code obfuscator
reads in Verilog, VHDL, System Verilog and/or SystemC and scrambles
the contents yet it's still executable and synthesizable. ARM, ARC,
LSI Logic, Synplicity, Telia, Zoran, and Mercury Computer all use
Thicket to encrypt their stuff. Ask for Mark O'Brien.
17.) Peggy Aycinena -- opinionated, connected, insightful, and hyper;
she's the EDA world's speed-talking female version of a Mark Twain
who has downed too many cups of expresso. If you talk to her in
person you have to bring a tape recorder, record what she says, and
then play it back at 1/2 speed. "DidYouKnowThatMikeFisterMakes
$10MillionAYear? TheAveragePriceOfAPairOfWomen'sShoesIs$100. MyGod!
DoTheMath. ItMeansMikeFisterGets100,00PairsOfWomen'sShoesEveryYear!
WhatIsAManLikeHimDoingWith100,000PairsOfWomen'sShoesEveryYear?!"
(Joking aside, EDA Peggy is a "must read" industry commentator.)
18.) Silicon Design Systems (booth 125) -- claims to be a next generation
router. It's called K-Route and I'm not sure what distinguishes it
from its rivals. I do know that SDS is going to have all sorts of
customer confusion problems with the IP company, Silicon Design
Solutions, though. Two SDS's? Not a good idea.
Tera Route (booth 1827) -- newbie this year at DAC. Appears to be
yet another router company, except theirs is a shape based router.
Athena (booth 2253) -- newbie this year at DAC. Appears to be
yet another router company, except theirs runs distributed across
a Linux farm. Ask for John Murphy. He used to be the Chief of
Staff to Ray Bingham, Chairman of Cadence. "Do you take milk or
sugar with your coffee, sir?"
19.) Calypto (booth 1818) -- this year's newbie bug hunter at DAC.
Their poorly named "SLEC" tool can do some sort of equivalence
checking of changes in state machines. Ask for Mitch Dale.
Jasper (booth 419) -- Yea, they're announcing their JasperGold 4.0
with its PSL assertions support, but I'll go by this booth just to
say "hi" to Kathryn Kranen. No dummie, she knows how to put
together a good EDA technology team and make stuff that customers
want. She's the next up-and-coming Penny Hersher.
Mentor 0-in (booth 1880) -- Hey, if Mentor paid $50 million for
this company, there must be something under the hood here that I
should check out. And what the hell is this Questa stuff anyway?
Are they just trying to repackage 0-in? Ask for Neil Hand.
20.) Silicon Canvas (booth 1600) and Pulsic (booth 1091) -- These are
the two players I know of who have a possiblity of taking a nasty
bite out of the Cadence Virtuoso monopoly in full custom layout.
Users gushed about Pulsic Lyric in DAC 04 #28, but Silicon Canvas
Laker was identified as the biggest threat to Virtuoso when they
were bumped from the Cadence Connection Program in ESNUG 443 #5.
At Pulsic, ask for Jeremy Birch; SiCanvas, ask for Hau-Yung Chen.
21.) Mentor ModelSim (booth 1800) vs. Aldec (booth 1023) -- normally I
didn't pay that much attention to Aldec because I thought they were
just serving the cheap seats in the Verilog/VHDL simulation market.
That changed in ESNUG 445 #7 when a bunch of Aldec users spoke up
saying how much they liked it better than ModelSim. I figure I
should check this out by talking to Aldec's David Rinehart. On the
flip side, it'd be fun to hassle Mentor's Stephen Bailey to see how
he defends ModelSim. And what the hell is this QuestaSim? Is it
just warmed over ModelSim?
23.) Jay Vleeschhouwer and Erach Desai -- the yin & yang twin brothers of
the EDA financial analyst world.
Jay is the respectable Good-Housekeeping-Seal-of-Approval one who
works at the nationally recognized Merrill Lynch. All the CEOs and
CFOs in EDA bend over backwards to keep Jay happy. You'll often
see Jay welcome on lots of EDA industry panels and such.
Erach is the evil twin Doom-and-Gloom naysayer of EDA and who works
at the obscure AmTech Research. The CEOs call him "Shiva" -- as in
"I am become Shiva, the destroyer of EDA market caps...". You won't
see Erach on many EDA industry panels.
To get a balanced view of how the financial world honestly sees EDA,
I would suggest you make it point to talk to both Jay and Erach.
24.) Tharas (booth 1001) -- the primary reason I'd be at the Tharas
booth is pure curiousity. Two years ago, I read that Synopsys had
invested in Tharas. This surprized me. Back in 1995, Synopsys
had bought Arkos for $9.3 million. By July 1997, Synopsys had
sold (at a firesale price) Arkos to Quickturn. It was a disaster.
Then there was that failed bid on Ikos that Synopsys tried in
2002. So I'd be asking Richard Curtin of Tharas: "What does
Synopsys see in Tharas?" -- after which I'd see what the Mentor
Vstation guy, Neil Songcuan, has to say about it. And then I'd
see Henry Pechar about the Cadence Palladium perspective on this.
Carbon Design (booth 2240) -- they have an all-software emulator that
could be interesting. How does it stack up vs. the old LMC hardware
models or Mentor Seamless? At the Carbon booth I'd ask Steve Butler.
25.) Golden Gate (booth 1050) -- they've had a power optimizer for a
few years, but to be honest, I've never looked at it because their
marketing guy was (I'm not making this up) against getting publicity.
I've heard they got a new marketing guy, Dennis Heller, so it's
now time to check Golden Gate out.
Azuro (booth 112) -- a newbie power optimizer that claims to do
magical stuff to your design's clock to get 20% power reduction.
26.) Denali (booth 1073) -- yea, they have a monopoly on memory models.
Who cares? I'm there to pester Kevin Silver so I can get a ticket
to their infamous DAC party. "Come on, Kevin, pleeeease...."
Also, if you're at DAC on Tuesday at noon, go to Forte (booth 1317) because
a gentlemen's bet is going to be settled then. In ESNUG 441 #12, you will
see Brett Cline and I arguing about SystemC adoption. Long story short,
if more than 50% of my upcoming DVcon'05 Trip Report survey respondants
said they'll be using SystemC seriously on their project within the next
6 months, I'll be wearing a chicken suit. If the number is less than 50%,
Brett will be wearing the chicken suit. Be sure to get there at noon,
because by 12:02 we'll be done. That's Tuesday at Forte at noon. :)
See you at DAC!
- John Cooley
ESNUG/DeepChip.com
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John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
or (508) 429-4357.
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