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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2008"
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by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this to use as an unofficial guide
to the Anaheim DAC exhibit floor next week.
1.) As Virtuoso killer #1, I recommend you look at Magma's new Titan.
It reads/writes OA. Plus it's agile. In ESNUG 472 #1, it read in
6 Gbytes, 24 M transistor in GDSII in less than a minute. Titan's
big claim is automated chip finishing & automated analog migration.
Titan embeds Talus, so you can do true mixed signal design in it.
(booth 2349) Ask for Ashutosh Mauskar. Freebie: sunglasses clip
As Virtuoso killer #2, I recommend you look at Synopsys "Orion".
It also reads/rights OA, but natively, no API, no Milkyway. They
also claim its agile, but I have zero users (so far) confirming it.
Orion has the look-and-feel of Virtuoso plus more. Wiretap 080604.
(booth 1349) Ask for Graham Etchells. Freebie: Starbucks card
I'd suggest SiCanvas Laker as #3, but (along with Novas) they merged
back into SpringSoft in Taiwan. Too much chaos for me right now.
As Virtuoso killer #4, I hesitantly recommend Analog Rails. Focused
on analog automation (sizing and layout). Mixed signal simulations.
Schematic driven layout. Built-in diff Pcells. Layout of an A/D
converter in 1 hour. Problem? CEO is notoriously cocky and cheap!
(booth 1534) Ask for Cliff Wiener. Freebie: a surly attitude
For Virtuoso killer libs, try Ciranova PyCell Studio as a way around
the Cadence Pcell SKILL monopoly. PyCells are Pcells written Python.
(booth 2841) Ask for Michael Ma. Freebie: 2 GB memory sticks
For Virtuoso killer PDKs, try IPL. OA-based and open, unlike CBDA,
SKILL, etc. Works in "Orion", Laker, Calibre. Even TSMC has joined.
(booth 1541) Ask for Jingwen Yuan. Freebie: USB car chargers
2.) Extreme GoldTime does both static and statistical timing analysis,
plus MCMM and SI but with monster capacity. Nvidia says "50M+ cell
design in under 6 hours." TI, NEC, PMC-Sierra, Samsung, ST users.
(booth 1364) Ask for Guy Maor. Freebie: LED flashlight/pointer
CLK Amber FX also does STA and SSTA but claims "near-SPICE accuracy
for delay and variance combined with threaded performance" plus
"its new FX transistor model is supported in TSMC 9.0 for 40-nm."
(booth 2667) Ask for Isadore Katz. Freebie: none
Incentia TimeCraft-SSTA also STA and SSTA and claims "fast analysis
and large capacity" plus it "performs both path-based and block-
based analysis, based on user defined correlations, such as intra-
parameter, inter-parameter, and spatial correlations". Both CCS-VA
and S-ECSM library formats are supported. New SSTA tool this year.
Also check out their new ECOCraft tool; it's for late stage ECOs!
(booth 600) Ask for Arthur Wei. Freebie: deck of poker cards
Synopsys PrimeTime also does STA, SSTA, noise, crosstalk and power.
This DAC's claim is PT is "up to 4X faster and multi-core enabled".
(booth 1349) Ask for Ken Rousseau. Freebie: Starbucks card
3.) Now that OneSpin has customers beyond its parent Infineon, it's a
legitimate EDA company in my book. Their 360MV tool does something
called "gap-detection" plus timing diagrams on your design's System
Verilog Assertions. Customers: NXP, Bosch, and Alcatel-Lucent.
(booth 625) Ask for Michael Siegel. Freebie: Sudoku puzzle
Real Intent Meridian CDC does much appreciated clock domain crossing
verification. Formal analysis and interfaces to simulation. Neat!
(booth 2540) Ask for Jin Zhang. Freebie: racing flag pens
Behind suite doors, Jasper has a thingy which lets you interrogate
alien IP, using NO stimulus, so you can tweak that IP for your chip.
(booth 2346) Ask for Rajeev Ranjan. Freebie: 512 Mb USB mem stick
4.) It turns out, that after all the mystery, the NuSym DeNibulator is
what is now called an "intelligent testbench" thingy. It hunts down
your hard to find coverage points and automatically tweaks your TB
to reach them. It's next gen constrained random. See ESNUG 473 #6.
(booth 379) Ask for Jayant Nagda. Freebie: Twinkies
The traditional rival to the NuSym DeNibulator is Certess Certitude.
After cutting through a LOT of the Certess marketing bullshit, it
appears Certitude injects errors in your DUT and runs regressions to
see if the error is caught. It grades your TB for coverage holes.
(booth 324) Ask for Joerg Grosse. Freebie: magnetic bendy bugs
Another "intelligent testbench" is Mentor inFact. It appears to be
a graphical tool that generates, grades, and then upgrades TBs. It
now drives existing e, Vera, SV, or C/C++ TBs. Does OVM & VMM, too.
(booth 2301) Ask for Mark Olen. Freebie: iPod earbuds
5.) Sequence PowerArtist does automated RTL power reduction "up to 50%
cut". Ran on a 15 M gate design in 4 hours with a 12 GB footprint.
"Power savings are over and above those achieved during synthesis."
(booth 2100) Ask for Preeti Gupta. Freebie: psychedelic pens
Calypto PowerPro CG also does automated RTL power opto, but it
"inserts clock gating enable logic into the users RTL code and
comprehensively formal verifies the result" with their SLEC tool.
(booth 1354) Ask for Mitch Dale. Freebie: 1 GB USB USB mem stick
6.) If you're into ANSI design, CebaTech is showing their C2R Compiler,
which takes untimed ANSI C and outputs Verilog RTL. "Supports
control and data path equally well plus floating point libraries."
(booth 760) Ask for Chad Spackman. Freebie: mints on keychains
If you're into SystemC design, Forte Cynthesizer v3.4 adds support
for Power Compiler for "best-in-class area, performance, and now
power results" and "management of ECOs by graphically mapping RTL
back to the original SystemC design" and inter-block interfaces.
(booth 1645) Ask for Brett Cline. Freebie: caricatures
If you're into C++ design, Mentor is barking about their Catapult C
synth & Vista ESL tools. What's new this year? They said nothing.
(booth 2301) Ask for Shawn McCloud. Freebie: iPod earbuds
If you're into Verilog-RTL-to-C conversion for simulation (instead
of C-to-Verilog-RTL for design), check out Carbon's Model Studio.
It's more for architects and SW guys wanting models before silicon.
(booth 2467) Ask for Bill Neifert. Freebie: stuffed soccer balls
Synfora Pico Extreme also plays in C, but I'm not sure exactly how.
(booth 329) Ask for Vinod Kathail. Freebie: none
If you want to piss off all the C people, check out Bluespec with
its proprietary "general purpose high-level synthesis & simulation
for modeling, verification and implementation". Transactional.
(booth 2367) Ask for Steve Allen. Freebie: electronic Sudoku
Simon Davidmann's new company, Imperas, sort of lands here with
what appears to be yet-another-ISS tool, OVPsim, for embedded SW.
(booth 467) Ask for Duncan Graham. Freebie: leather beer coaster
Mirabilis VisualSim does "graphical SystemC TLM 2.0 import without
any code development; and power estimation of the full system."
(booth 778) Ask for Deepak Shankar. Freebie: none
7.) First Encounter is known as being a kick ass prototyper that's been
morphed into being a floorplanner. Jupiter-XT is known as being
a kick ass physical floorplanner that's had to learn to speed up.
This year, Magma punted its olde BlastPlan and is replacing it with
"Hydra" which does "auto-interactive hierarchical design planning
and prototyping". They claim its 5X faster than "any other" tool,
plus it has a shape-aware block placer and does soft block shaping.
(booth 2349) Ask for Yukti Rao. Freebie: sunglasses clip
8.) All three of the P&R flows claim to do CTS, but if you use them
they're all crap. This year one company, Azuro, has made it their
bread & butter to focus solely on CTS and post-CTS-optimization.
They claim their PowerCentric tool "reduces clock power by up to
40%. Reduces clock area, insertion delay and skew." Broadcom,
ST, Nvidia, Toshiba, and TI use PowerCentric, too, so it probably
works. Supposedly they have tapeouts in all Big Three P&R flows.
(booth 601) Ask for Marc Swinnen. Freebie: cell phone charger
Prolific ProTiming/ProPower also does post-P&R timing/power opto
by swapping cells in your design. It "reduces leakage power by
25%-70% after P&R tools have fully optimized your design." The
freaky thing is that this year Prolific's tools actually ride on
top of PrimeTime for MCMM analysis. It's signoff quality opto!
(booth 1309) Ask for Paul de Dood. Freebie: T-shirts
Nangate Design Optimizer does automated full custom optimization.
It figures out what cells would be needed to obtain higher speed,
smaller area or lower power; creates the new cells; then stitches
in the new cells into your netlist. NXP is using them at 32 nm!
(booth 759) Ask for Jens Michelsen. Freebie: T-shirts
DAC newbie Envis also has two tools, "Chill" & "Kelvin", which do
netlist level tweaks. Chill does clock gating power opto. Kelvin
does auto power pattern gen so you can find typical power early.
(booth 2852) Ask for Elias Echeverri. Freebie: polar bears
9.) For design data management, on DAC Tuesday at 10:30 AM, I'll be in
Room 206AB for Steve Golson's "Four Principles of Flow Engineering"
talk. Steve's a damn good presenter. Freebie: propaganda buttons
I'll also be checking out Dassault Synchronicity DesignSync this
year. Users brutally beat them up in ESNUG in the past. They
claim to have some much better Cadence data management tools now.
(booth 620) Ask for Peter Haynes. Freebie: folding rulers
On the gossip front, I heard that IC Manage had recently beat out
DesignSync by 3X to 5X on an internal LAN benchmark at AMD Green.
(booth 2200) Ask for Dean Drako. Freebie: weird lasting mints
ClioSoft has a Universal DM Adaptor to its SOS tool used by TSMC,
Analog Devices, and SUN. They're focused on custom design data.
(booth 1665) Ask for Karim Khalfan. Freebie: Swiss army knife
For speedy data transfer, ask Shearwater about the Saratoga Flume.
They claim data sends 3-100x faster than dog slow FTP. Zoom!
(booth 1635) Ask for Robert Cousins. Freebie: print anything big
10.) On the P/G noise front, this year Apache RedHawk is doing switched
memories, backbiasing, and on-chip LDO voltage regulators. They're
also claiming transistor-level full chip power supply analysis.
(booth 2311) Ask for Aveek Sarkar. Freebie: stuffed dogs
Berkeley AFS NAO -- their Noise Analysis Option was just announced
this year. "It's the first tool to provide practical transistor-
level device noise analysis for ADCs and fractional-N PLLs."
(booth 2641) Ask for Glenn Crosby. Freebie: flashlight pens
For the truly freaky, you multi-Gbit guys should check out Agilent
EEsof. They now claim that their ADS planar-3D electromagnetic
simulator is 10X faster and has 6X more capacity. Damn RF freaks!
(booth 1601) Ask for Larry Lerner. Freebie: mouse pads
11.) Nascentric OmegaSim GX is easily this year's most interesting SPICE
and Fast SPICE tool; because it's HW tuned to the Nvidia Tesla GPUs.
Whoa, mama! Hardware turned! Claim they're 10X faster over all
comers with Berkeley accuracy. I believe them. This is a MUST SEE.
(booth 1571) Ask for Adrianna Galletta. Freebie: sling rockets
Berkeley AFS claims it's "integrated into Cadence Virtuoso ADE,
requires no block-level tuning, and produces standard waveform
output formats" and its "5x-10x faster on 5x-10x larger circuits".
(booth 2641) Ask for Glenn Crosby. Freebie: flashlight pens
Magma FineSim SPICE this year at DAC is emphasizing its multi-CPU
SPICE and claim to have linear scaling. AMD and Toshiba uses them.
(booth 2349) Ask for KT Moore. Freebie: sunglasses clip
12.) Apache Sentinel-PI (formerly Optimal PowerGrid) reads in RedHawk
generated Chip Power Models for signoff power analysis across the
chip, package & PCB. Claims a new 3D, full-wave engine inside.
(booth 2311) Ask for Dave DeMaria. Freebie: stuffed dogs
In contrast, Magma RioMagic is a chip-package co-design tool which
focuses on I/O & bump placement, RDL routing, escape routing and
package-pin assignment. RioMagic is more of an implementation tool.
(booth 2349) Ask for Jayshree Desai. Freebie: sunglasses clip
13.) AtopTech Aprisa, the P&R tool that caused so much drama at Broadcom
in ESNUG 470 #1 and it was finally vindicated in ESNUG 473 #1 with
3 tapeouts. (Actually now 8 tapeouts.) This DAC they're chatting
up multi-threading and multi-processing. BRCM, Sharp, RMI users.
(booth 619) Ask for Stephen Deng. Freebie: buzz ball
Mentor Sierra Olympus supports "MCMM optimization of timing, power,
SI, size, leakage, CTS, on-the-fly extraction" plus DFM-aware
routing and it analyzes "IR drops, leakage current, cell sizing,
transistor voltage thresholds, and electromigration effects. High
capacity. 100M+ gate designs handled flat with no segmentation.
Low power design features." Gosh!, is there nothing it can't do?
(booth 2301) Ask for Sudhakar Jilla. Freebie: iPod earbuds
Magma Talus Vortex this year is "smoking fast and efficient MCMM
optimization with tight integration to third-party electrical
sign-off." (Is that Marketing for "it works with Calibre"? Or
is it PrimeTime?) The Talus Power Pro is more interesting. It
uses UPF for low power P&R. TI, Qualcomm, Nvidia, Broadcom users.
(booth 2349) Ask for Jonathan Smith. Freebie: sunglasses clip
Synopsys IC Compiler has added Z Route, which is a multi-threaded,
multi-core based router which has a "10X speed-up". Their DAC demo
shows it routing a "10 M gate design LIVE in less than 30 minutes."
(booth 1349) Ask for Joel McGrath. Freebie: Starbucks card
Synopsys DC Graphical lets RTL designers "predict, visualize and
optimize wire-routing congestion early in the design flow, prior
to physical implementation." Stop congestion hot spots early.
(booth 1349) Ask for Priti Vijayvargiya. Freebie: Starbucks card
14.) EVE ZeBu is showcasing PCIe and AXI synthesizable transactors and
its System Verilog support for custom transactors. ZEMI-3 stuff.
(booth 301) Ask for Alain Raynaud. Freebie: water bottles
Mentor Veloce folks will show a demo "using mixed System Verilog
and SystemC based upon System Verilog DPI standard 2.0" with their
Nucleus embedded RTOS stuff also thrown in for good measure.
(booth 2301) Ask for Sanjay Sawant. Freebie: iPod earbuds
Synfora Pico Extreme FPGA might also play here, but not sure how.
(booth 329) Ask for Vinod Kathail. Freebie: none
15.) It's weird. Ever since Synopsys bought Synplicity, I haven't
heard a peep from the Synplicity folks. Who's been laid off? Who
just quit? Who is going to still stay? Is Synplify Pro going to
disappear? What about Identify? Certify? Premier? HAPS? DSP?
(booth 1310) Ask for Ken McElvain maybe. Freebie: his job?
16.) For practical DFM/yield, I'm now looking at the Pyxis NexusRoute
router. They have "break-through" 3D wire balancing stuff for
yield/power/timing and concurrent shape-based DRC fixing during
routing. Microsoft XBOX used them. Runs in Magma and Synopsys
backend flows. They're talking 45 nm and 32 nm. Yup, I'm there.
(booth 374) Ask for Sharad Mehrotra. Freebie: guitar picks
Mentor YieldAssist says that it "helps failure analysis engineers
rapidly identify the location of defects found in production
testing using actual silicon failure data." Infineon uses it.
(booth 2301) Ask for Ron Press. Freebie: iPod earbuds
Mentor Calibre CMPAnalyzer is directly linked with VCMP, TSMC's
CMP simulator, to provide 3-D hotspot detection and optimum fill
strategy. SmartFill then adds the fill elements directly into
your layout design database. Both improve parametric yield.
(booth 2301) Ask for Jeff Wilson. Freebie: iPod earbuds
Synopsys TetraMAX has added some new weird tests that aren't your
usual standard stuck-at tests; many now are subtle yield/DFM tests.
(booth 1349) Ask for Robert Ruiz. Freebie: Starbucks card
Magma Camelot, which does fab yield management, at this DAC has
"3D cross section visualization, passive voltage contrast checker,
hot spot analysis, layout search analyzer, standalone wafermap".
(booth 2349) Ask for Scott Shen. Freebie: sunglasses clip
Lib Tech YieldOpt finds best/worst timing of a circuit under global
and random process variations. It's like exhaustive Monte-Carlo.
(booth 1135) Ask for Mehmet Cirit. Freebie: none
DAC newbie Gauda claims 200X faster OPC/OPV because they cleverly
partition designs and are run on commercial Nvidia & ATI GPUs.
(booth 323) Ask for Ahmet Karakas. Freebie: none
Synopsys has PrimeYield LCC litho checking, but didn't say much.
(booth 1349) Ask for Rahul Kapoor. Freebie: Starbucks card
17.) In physical design, DAC newbie Fenix CrossFire finds inconsistencies
across different views of IP (or libraries) -- LEF, Spice, DFII, OA,
Milkyway, .lib, Verilog, VHDL, GDSII, TLF, Liberty, CCS, ECSM, etc.
(booth 534) Ask for Chris Strolenberg. Freebie: Belgian chocolates
Also in the std cell library game, Prolific is pimping ProGenesis for
32 nm layout. Claims better than hand drawn. ARM to Xilinx uses it.
(booth 1309) Ask for Paul de Dood. Freebie: T-shirts
Magma SiliconSmart is yarping about how their lib characterization
works with their FineSim SPICE (yawn!) plus functional recognition of
complex circuits, and plans for advanced memory characterization.
(booth 2349) Ask for Steve King. Freebie: sunglasses clip
Z Circuit ZChar does general purpose cell library characterization.
(booth 941) Ask for Ralph Lanham. Freebie: chocolates
Altos Liberate and Variety tools do cell and I/O characterization for
nominal and SSTA models. Used in production by TSMC at 40 nm.
(booth 1665) Ask for Jim McCanny. Freebie: toy car
18.) In the quick & dirty debug business, LogicVision Silicon Insight
is SW in a laptap which talks directly through a USB cable to the
JTAG interface to get to their LogicVion BIST in your chip. This
lets you cheaply snoop real time on your chip's guts. Neat!
(booth 1620) Ask for Steve Pateras. Freebie: foldable frisbees
For a more detailed debug, you can insert Dafca ClearBlue in your
chip and you get as much comprehensive surveillance of practically
anything you want to see on your chip. Check out ESNUG 469 #6.
(booth 2218) Ask for Dan Hoggar. Freebie: small toolkits
19.) In the DRC game, as usual Mentor is kicking ass with Calibre adding
the ability to do equation-based DRCs, for the really messy checks
DFM/yield work needs, and distributed parallel incremental DRCs.
(booth 2301) Ask for Michael White. Freebie: iPod earbuds
Synopsys is hyping how Hercules hooks with IC Compiler to "provide
production-proven 45/40 nm DRC checking". Yawn. OK, so 40 nm ain't
nothing to yawn at; hooking to ICC is! Christ, it's a SNPS tool!
(booth 1349) Ask for Rahul Kapoor. Freebie: Starbucks card
20.) For funky RTL tools, I always check out FishTail Focus and Confirm.
They're really good for correct constraints on multi-cycle paths.
(booth 767) Ask for Ajay Daga. Freebie: none
VeriEZ EZVerify covers you design, assertions and testbench. They
added full System Verilog support this year plus VMM/OVM checking.
(booth 1936) Ask for Sashi Obilisetty. Freebie: pens
Veritools usually has linters, code coverage and waveform viewers
that are pretty cool, too. Supports SV dynamic objects this DAC.
(booth 1334) Ask for Robert Schopmeyer. Freebie: squeeze balls
Atrenta 1Team-Genesis (new tool) is for "architecture capture, IP
import, high-level chip assembly and hook-up." Ugh. Frameworks.
Atrenta GuideWare (new tool) "takes the thousands of rules Atrenta
has developed over the years and organizes them into pre-packaged
templates that reflect the SoC design process. More frameworks!
(booth 2327) Ask for Krishna Uppuluri. Freebie: magic trick
Paradigm Works SV Frameworks supposedly "enables design teams to
get started with VMM much faster". I fucking hate frameworks!
(booth 2318) Ask for Saeed Coates. Freebie: M&Ms
21.) If you want to know where the source code comes from for many EDA
tools, just swing by Verific. They provide the front-end HDL
parsers in C++ for over 50 EDA tools, including all FPGA vendors.
(booth 655) Ask for Rob Dekker. Freebie: stuffed giraffe
22.) And this year the Denali guys are chatting up the fact that they
now have wall-to-wall System Verilog methodology support (OVM,
VMM, AVM) across their entire PureSpec portfolio. Yay, Denali!
Also that "The MMAV package has been extended this year to support
System Verilog (all flavors, methodologies) and non-memory
protocols (AMBA, OCP, DFI and SystemRDL)". Whatever that means...
(booth 1611) Ask for Sanjiv Kumar. Freebie: party tickets
Most people don't know that Google.com was originally going to be
called Wahoo.com until Denali CTO Mark Gogolewski early angel
funded the search engine start-up. Ask him about his GOOG shares.
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
ESNUG/DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
or (508) 429-4357.
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