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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2011"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this as an unofficial guide to the
San Diego DAC exhibit floor next week. List ranked in order of importance.
1.) With all chips over 10 M gates being 99% IP, and the GSA saying 66% of
all IP is homegrown, IC Manage's IP Central helps design houses with
100's or 1000's of internal legacy IP make that IP actually reusable
in-house. When before you'd have a company HTML index of IP tarballs
with a few READMEs thrown in; now IP Central creates one *dynamic*
monster database of all *incremental dependencies* of EVERYTHING about
each IP. You get the IP source code, its testbenches, its many bug
relationships, its docs, who's using it, how it has changed, plus
how each specific change ripples through to other designs. Searchable
and claims to be open. "IP data can be imported or linked from CVS,
Subversion/SVN, Mercurial, Git, ClearCase, DesignSync, Enovia and
internal databases or file systems for a central view of IP assets."
(booth 1617) Ask Shiv Sikand. Freebie: "Reuse" peanut butter cups
The Atrenta SpyGlass IP Kit was from working with TSMC to ID the 100's
of rules that should be run on soft IP *before* anyone tries to reuse
it. Creates "datasheet" of IO ports, power dissipation, clock trees,
reset trees, gate count, testability. Also creates a "dashboard": Is
anything missing for synthesis? What will stuck-at and at-speed test
coverage be? Sequential elements scan-able? Power domains correctly
defined? Are clock and reset constraints set properly? Are clock
definitions consistent, correct, and complete? Are CDC synchronizers
bug-free? Are timing constraints consistent across block boundaries?
False & multi-cycle paths IDed? Users ST, TI, Renesas Mobile, Sonics,
Arteris. (booth 1643) Ask for Mike Gianfagna. Freebie: t-shirt
2.) Rumor has it Samsung Memory and Samsung Logic both used to be 100%
Synopsys HSPICE/CustomSim/HSIM/NanoSim/XA houses until two benchmarks
caused Samsung Memory to go 100% and Samsung Logic to go 50% Magma
Finesim. That's an est new $15 M / year for 3 years going to LAVA!
Why? Magma's DAC write-up says it all: "Finesim's the only fast-SPICE
today that runs on multi-CPUs/multi-machines. One customer taped-out
a 1.5 M transistor design that ran on 8 CPUs in 4 days, and 1 day on
32 CPUs. Adding RF (harmonic balance) this year. In one benchmark
Finesim averaged 3X faster vs Synopsys XA, 3.2X faster vs Spectre APS.
In another, 6X faster vs HSPICE and Spectre couldn't run the design."
Toshiba, Hynix, Micron, Sandisk, IDT, TI, TSMC, Maxim, Melfas use it.
(booth 1743) Ask for Greg Curtis. Freebie: ear buds
Berkeley AFS gets "identical results to Spectre & HSPICE (guaranteed)
5x-10x faster single-core & up to 50x faster with multi-core parallel
operating mode for characterization. Handles 10 million elements."
Claims results within 1-2 dB of silicon 5x to 10x faster. Qualcomm,
Broadcom, Fujitsu, NXP, Samsung, Sony, LG, NXP, Panasonic uses them.
(booth 3149) Ask for Roshan D'sa. Freebie: pen tool kit
Mentor Eldo Premier "provides a 2x to 20x improvement over traditional
SPICE and averages 2.5x for single-threaded and multi-threaded runs."
It's "especially for very large transient simulations." Via Tech says
Eldo Premier benchmarked 4X faster vs. Eldo Classic on a 40 nm PLL.
(booth 1542) Ask for Cyril Descleves. Freebie: none
Cadence MM-Sim is the third or fourth renaming of Spectre (I think)
and claims to be "scalable and parasitic-aware on multi-core compute
resources". It's big plus is it's in IC615 ADE. Used by NXP, ST,
NEC, Renesas, Broadcom, Maxim. (booth 2237) Ask for John Pierce.
3.) Synopsys wants to be your company gatekeeper SysAdmin by relaunching
its DesignSphere.com cloud computing SaaS from 2000. Now its online
burst VCS or HSPICE is on 100% Synopsys-controlled Amazon EC2 servers.
"Look, Aart!, we locked out Magma!" Ask for David Hsu. (booth 3433)
Cadence does cloud computing SaaS with its Hosted Design Solutions
that targets tiny full custom start-ups to use a one-size-fits-all
Virtuoso flow. Ask Vishal Kapoor. (booth 2237) Freebie: t-shirt
Imera Virtual Fabric lets you set up your own cloud-based server farm
where YOU get to decide which EDA tools are or are not on it. Rivals
"VMware and Altor work at hypervisor layer & support only virtualized
cloud computing. Imera works in VM guest OS layer and the physical
machine OS layer." Mentor, Qualcomm, Cadence, AMD, TSMC uses Imera.
(booth 3225) Ask for Tim Goh. Freebie: pens
Nimbic nCloud does scalable cloud computing with pay-as-you-go or
subscription models. Formerly "Physware", they have their nWave full
3D EM solver and their nApex 3D parasitic extractor already installed.
(booth 2617) Ask for Don MacMillen. Freebie: sticky wall walker
Univa calls itself the "Data Center Optimization Company" and is
also chatting up cloud computing and the Grid Engine. (booth 2124)
And EMC Isilon sells stuff for your own cloud computing. (booth 3213)
StarNet X-Win32 iLIVEx lets engineers suspend Unix/Linux-based EDA
tools from their office PC and resume their running from an iPad.
It's like RealVNC. Rockwell Collins, Raytheon, AMD, Xilinx uses it.
(booth 2926) Ask for Paul Swart. Freebie: St. Bernard dog
4.) NEW TOOL - Magma Chill does netlist-based dynamic power reduction
through combinatorial and sequential clock gating. Since it's a
netlist tool, you can use it in a SNPS/CDNS/LAVA/MENT/ATOP flow
with no special tweaking needed. It's an easy out-of-the-box 20%
to 30% power reduction. (booth 1743) Ask for Mark Richards.
Calypto PowerPro 5.0 is an RTL power reducer that works on everything;
logic, memory (dynamic and leakage), and embedded processors. Uses
formal EC to check. This year 2x faster, new stuff for memory opto,
advanced reset logic insertion. STARC, Ikanos, Advantest, AMD use it.
(booth 2012) Ask for Anmol Mathur. Freebie: none
Conformal Low Power is the Cadence version of Synopsys Formality/MVRC.
Qualcomm, Broadcom, Freescale use Conformal Low Power. Both tools
read in your RTL or gate-level netlist and then do magical "power
intent" comparisons and checks on your chip. Synopsys is UPF only.
Cadence is CPF. Ask for Buda Leung. (booth 2237) Freebie: t-shirt
Atrenta Spyglass LP does power estimation at RTL/gates with UPF/CPF.
Finds new clock & memory gating in RTL for CDC-aware power reduction.
Automatically implements new clock and memory gating then proves
results with sequential formal checks. Used by TI, ST, Ericsson,
Intel, Juniper, Marvell, Samsung, Infinera, STARC, Renesas, Cisco.
(booth 1643) Ask for Kiran Vittal. Freebie: t-shirt
Docea Aceplorer does power and thermal dynamic simulation and opto at
the architectural level. Tool is meant for SoC power architects.
ST-Ericsson cut their power management software debugging time by 2/3.
(booth 1912) Ask for Rabih Saade. Freebie: French candy
Prolific ProPower provides PrimeTime-based, simultaneous multi-corner,
block-level, backend power optimization. "Get at least 25% leakage
power improvement." 2x faster. (booth 2331) Ask for Paul de Dood.
Apache PowerArtist-PACE generates RTL clock and capacitance models for
power analysis "because wireload models no longer work" and "RTL power
analysis is meaningless without adding in clock trees." PowerArtist
together with RedHawk and Chip Power Model (CPM) "uses RTL simulations
to identify peak power and peak di/dt switching scenarios, otherwise
missed with vectorless approaches." Used by AMD, Exar, LSI, Sigma.
(booth 2448) Ask for Will Ruby. Freebie: stuffed animal
5.) This year Atoptech Aprisa has added fancy-pants clock tree synthesis.
"Clock skewgroups are automatically identified and their latency
adjusted, either forward or backward in time, to reduce your total
negative slack (TNS)." PMC-Sierra, Broadcom, Netlogic uses them.
Atop is also working with Extreme DA to improve sign off correlation.
(booth 2816) Ask for Eric Thune. Freebie: stuffed tiger
Mentor Olympus-SoC has "new features for TSMC & Globalfoundries 28 nm
processes." Hierarchical stuff, macro analysis and placement, rapid
prototyping, advanced block shaping, clock planning and chip-level
assembly, proprietary modeling, flow parallelization and MCMM stuff.
ST, AMD, Fujitsu uses it. (booth 1542) Ask for Sudhakar Jilla.
Magma Talus Vortex FX now does multi-machine, multi-threaded, getting
MMMC runs at 28 nm with 20-30% overhead for 15-20 scenarios. Runs
of 5 M instances in 2 days; 10 M instances *FLAT* in a week. It's
rumored used on 28-nm Qualcomm Snapdragon, Nvidia Tegra2 and TI Omap.
Magma Hydra does chip prototyping and hierarchical floorplanning.
Automates macro placement (500 macros/hr timing driven!), partition
creation, placement and shaping, global route topology planning, pin
assignment and budgeting. "Pin assignments using timing driven global
routing for congestion. Boundary optimization for interface timing."
20 M instances, placed, global routed in 4 days. Magma is squirrelly
about who uses their stuff, but heard Nvidia, Sony, Fujitsu use Hydra.
(booth 1743) Ask for Mark Baker. Freebie: ear buds
NEW TOOL - Because ICC and First Encounter internal timers don't match
PrimeTime's signoff timer, Magma Tekton SPX is a new standalone "chip
finisher" that magically does all-in-one extraction, incremental P&R,
and LVS/DRC to fix your new chip's 4,876 set-up & hold violations. It
works *with* IC Compiler, Cadence Encounter, Atoptech, Mentor Olympus.
Does ECOs, too. (booth 1743) Ask Ruben Molina. Freebie: ear buds
Cadence Encounter Digital is all about ARM Cortex A15/A9 cores at 28
and 20 nm. "Prototyping and analysis on a 200 M gate design in less
than an hour." Whiz-bang floorplanning (always a CDNS strong suit)
and 10x faster TAT. Used by Renesas. Ask for Paul Kollaritsch.
Their Encounter Yield Diagnostics seem interesting; it taps into your
already existing ATPG setup to give you lots of info on your yield
problems. IBM, Toshiba, Fairchild uses it. Ask for Lisa Jensen.
Cadence is also chatting up their monster end-to-end CPF low power
flow that goes Palladium, NC-Sim, RTL Compiler, Conformal, Encounter,
ATPG, DRC. Faraday and Fujitsu uses it. Ask for Pete Hardee.
To quiet the embarrassing $44 million Apache Redhawk IR-drop problem,
CDNS Marketing is slapping the words "Virtuoso" and "Encounter" onto
their old Simplex tools. (booth 2237) Ask for John Kane.
Teklatech FloorDirector 3.0 reduces the peak and shaping the slope of
dynamic on-chip currents by tweaking your clock tree. Hey, it beats
lots of de-cap, thick metal, re-spins. Their new Frequency Domain
Optimizer lets you choose best power integrity AND minimum noise at a
specific frequency. Cadence, Synopsys and Magma CTS all supported.
Working on Atoptech. (booth 1305) Ask for Tobias Bjerregaard.
Tuscany Tego is a datapath design tool. Does what-if analysis and
micro-floorplanning. See what wire length, timing and power do
quickly before taking your final structure to P&R. Has pre-router,
SDC support, congestion analysis. Used by LSI, NetLogic, Maxim.
(booth 3349) Ask for Matt Michels. Freebie: pens
Cadence Conformal ECO Designer creates functional ECOs based on your
RTL changes. "It is now integrated with other Cadence point tools
to provide industry's *only* RTL-to-GDSII physically-aware ECOs, both
pre- and post-mask capable." Ask for Kenneth Chang. (booth 2237)
6.) Mentor Catapult C synthesizes C/C++/SystemC to production quality RTL.
Now does incremental synthesis for ECOs plus it lets SystemC users
synthesize TLM models to create TLM-based virtual prototypes. Used by
Qualcomm, Hitachi, Ericsson, ST, TI, Telegent, Panasonic, Fuji Xerox,
Toshiba, Fujitsu, Sanyo. (booth 1542) Ask for Thomas Bollaert.
Forte Cynthesizer does SystemC synthesis to Verilog RTL of control and
datapath designs. Brett's showing a "bus-based system with complex
interfaces in pin and TLM w/ highly abstract coding styles, pipelined
memories, untimed and timed code, and full SystemC support. Sony,
Realtek, Samsung, Toshiba, Ricoh, Fujitsu, Sanyo, Megachips use it.
(booth 3417) Ask for Brett Cline. Freebie: caricatures
Cadence C-to-Silicon Compiler synthesizes SystemC TLM to Verilog RTL.
They're very proud it's in the whole proprietary CDNS flow. Will demo
an ECO. Used by Fujitsu, Renesas, TI, Freescale, Casio, Hitachi.
(booth 2237) Ask for Mark Warren. Freebie: t-shirt
Calypto SLEC 6.0 is *the* C/C++/SystemC equivalency checker. Now has
a new word-level solver for inductive setups, SystemC 2.2 support,
automatic wrapper and setup generation, CDNS C2S clock-gating, resets.
(booth 2012) Ask for Anmol Mathur. Freebie: none
Carbon SoC Designer Plus creates cycle-accurate SystemC models of your
chip. "Swap from the 100s of MIPS performance to 100% accuracy at any
software breakpoint." Samsung, ST, ST-Ericsson, LG, Huawei, Broadcom
use it. (booth 1914) Ask for Bill Neifert. Freebie: none
CoFluent Studio does ESL modeling. New release v4.0 can do automatic
generation of SystemC code from graphics for TLM-2.0 LT/AT and SCML2
interoperability. Has an Eclipse-based C++ debugger where changes in
user-reserved areas in generated code is propagated back into your
graphical model. Nokia, RIM, ST, Canon, Seagate, Toyota uses it.
(booth 1815) Ask for Laurent Isenegger. Freebie: none
Bluespec BDW is a GUI for the development, analysis and debug of
high-level models, transactors, stimulus generators using Bluespec
System Verilog (BSV). Now does source debug with designs in Verilog
simulation/emulation or FPGA prototype. "This is enabled by BSV's
100% architectural transparency, which is different from high-level
designs that are C-based." Used by Fujitsu, IBM, Intel and Qualcomm.
(booth 3031) Ask for George Harper. Freebie: a book on Bluespec
Mentor Vista does TLM modeling style architecture design and virtual
prototyping, links to MENT embedded and ESL-to-RTL SoC verification.
Used by Honeywell. (booth 1542) Ask for Jon McDonald.
Target Compiler MP Designer automatically parallelizes C code across
customer-defined multi-core architectures. (i.e. load balancing)
NXP used it to get 2.9x on a new 3-DSP architecture, compared to a
single DSP, with an instruction-cycle utilization of 97% on each.
(booth 2227) Ask for Erik Duymelinck. Freebie: post-it pads
Cadence SDS/VSP does HW/SW co-design "from architectural-level SW
development through system validation to post-RTL prototyping." Does
SystemC and UVM. Used by firmware/software teams at ARM, Nvidia,
Western Digital. (booth 2237) Ask for Leo Drucker.
ApS Brno Codasip uses an architectural description language called
"Codal" and building blocks called "ASIPs" that all synthesizes to
Verilog HDL with known area, power, timing. They're new to DAC.
(booth 3218) Ask for Karel Masarik. Freebie: none
Mentor Embedded Sourcery CodeBench provides a "complete C/C++ dvlpmnt
environment for embedded software design." It won the Embeddy Award
at the recent ESC 2011. (booth 1542) Ask for Stephen Olsen.
7.) TSMC is chatting up its "Silicon Interposer" and its Through Silicon
Via (TSV) for 3D. Ask for Tom Quan. (booth 2535) Freebie: toolkit
New stuff in Atrenta SpyGlass Physical 3D is native 3D floorplanning
with automated partitioning across the stack, routing congestion
analysis, TSMC Through Silicon Via (TSV) placement and Backside
Redistribution Layer (RDL) routing support, and a floorplan heat map.
Users Qualcomm and IMEC. (booth 1643) Ask for Mike Gianfagna.
Cadence 3D-IC Co-Design System supports TSV and silicon interposer.
Integrated analog, digital and package system based on Open Access.
Supports DFT, 3D exploration, 3D Floorplanning, TSV/Bump RDL
optimization and routing, 3D power and thermal analysis, custom edits
to the TSV and bumps, IC package among several others. Supports
wide I/O memory controller IP integration compliant with JEDEC.
Used by ST and Qualcomm. (booth 2237) Ask for Samta Bansal.
Mentor Calibre now supports 3D-IC verification including TSMC silicon
interposers and TSMC TSV's. (booth 1542) Ask for Michael White.
Apache RedHawk 3DIC does power analysis on 3D multi-die designs,
generates CPM that includes device-level current (switching and
leakage) and parasitic (diffusion, gate, signal, well) information.
(booth 2448) Ask for Aveek Sarkar. Freebie: stuffed animal
8.) NextOp BugScope generates functional assertions & coverage properties
from the RTL and testbench, for simulation, formal and emulation.
Emulation ABV without area overhead. RTL/assertion review with GUI.
System Verilog, VHDL beta. New Assertion Debugger. Huawei, IDT, TI,
Nvidia use it. Was #1 at DAC with users last year. See DAC 10 #1.
(booth 3131) Ask for Yunshan Zhu. Freebie: glitter wand
NEW TOOL - Real Intent Ascent XV is the "first tool for signing off
on X-propagation at the RT level." It formally determines where X's
might arise in a design after a reset state is reached, and where
X-Optimism can mask a functional bug in simulation. A hazard report
is generated which identifies specific constructs in your design that
are susceptible to X-Optimism and X-Pessimism. An X-accurate model
is generated which removes optimism and pessimism for accurate
simulation results at the RT or netlist levels. Holy mackerel!
(booth 2131) Ask for Lisa Piper. Freebie: mini-stapler
OneSpin Quantify MDV provides accurate metrics for formal verification
progress and quality without having to use simulation. It answers
three big questions: How good are my assertions? How good are my
constraints? How much of the verification plan has been completed?
Now backed by Azini Capital UK; Infineon is no longer a shareholder.
Bosch, Infineon, Intel, Renesas, Alcatel-Lucent, Nokia Siemens users.
(booth 1505) Ask for Peter Feist. Freebie: puzzle
Jasper ActiveProp generates SVA assertions automatically from RTL and
simulation for use in simulation, formal, & emulation. Now has static
checks and hierarchical support. (booth 1931) Ask for Alok Sanghavi.
Vennsa OnPoint does automatic root cause analysis of failures. It
shows "suspects" pointing to the actual bugs with no user direction
needed. Simular to Springsoft Verdi. See ESNUG 492 #4. Panasonic
uses it. (booth 2912) Ask for Sean Safarpour. Freebie: key chains
Cadence IFV and IEV now let "any engineer automagically create tests
from either SVA or PSL assertions to find bugs and to drive code
coverage and to flag completely unreachable states." Freescale, AMD,
STMicro, Marvell uses it. (booth 2237) Ask for Joe Hupcey III.
Avery Insight PSYN does "automatic microarchitecture assertion and
cover property synthesis"; similar to NextOp. It uses symbolic
methods and has a new SpringSoft Verdi integration. New tool.
(booth 1605) Ask for Kai-hui Chang. Freebie: LED flashlight
9.) In a world class betrayal of ARM Ltd, Synopsys is now showcasing its
"new" Virage DW ARC 600 & 700 family of cores at DAC which "utilize
a 16-/32-bit ISA that provides both RISC and full DSP capabilities
in a unified architecture". Ouch! (booth 3433) Freebie: pens
Carbon Design claims to have "the only accurate SystemC virtual model
of the ARM Cortex A15 available anywhere". It's integrated with the
ARM RealView debugger. (booth 1914) Ask for Bill Neifert.
Cadence has a 28/20 nm ARM Cortex A15 flow on demo. Rumor has it that
CDNS is ARM's preferred iRM (reference flow) at 20 nm, after what SNPS
did to ARM. Still in beta. (booth 2237) Ask for Paddy Mamtora.
Bluespec SVP is a subsystem of synthesizable models of ARM processor
ISS, memory, peripherals and AMBA interconnect that runs in FPGA
emulation and simulation, plus has ports for integrating homebrew IP
in the form of synthesizable models (before RTL is available) or RTL.
(booth 3031) Ask for George Harper. Freebie: a book on Bluespec
Avery AMBA-Xactor verifies AMBA-based designs using directed and
constrained random tests on AXI3/4 and AHB 2.0. SV/VMM/OVM
(booth 1605) Ask for Zhihong Zeng. Freebie: LED flashlight
10.) Oasys RealTime takes your chip's RTL and floorplan to placed-gates
"10X to 60X faster than Synopsys DC-Graphical can." Verilog, VHDL,
System Verilog, multi-mode synthesis, DFT, UPF/CPF low power design.
Their DAC demo is a *live* 30 min run of 300 K lines Verilog, 1.6 M
instances, 45 nm lib, 1.2 Ghz, full chip physical, low-power, DFT.
Texas Instruments, Juniper Networks, Netlogic, Xilinx uses them.
(booth 2031) Ask for Paul van Besouw. Freebie: t-shirts
Because Design Compiler is too big and too old and too complex to
speed-up, this year Synopsys is showing DC Explorer, an RTL estimator
pre-processor to DC. 4X speed-up says STmicro. I'm sure Aart says
"THANK GOD FOR THOSE BUNDLED SW DEALS!" to himself almost every day.
(booth 3433) Ask for Gal Hasson. Freebie: pens
Tiempo ACC synthesizes clockless, delay-insensitive TLM System Verilog
designs directly to gates. Yes, that's NO CLOCKS, folks! But it
auto-generates the interfaces to your synchronous-logic. Claim useful
for below 32 nm to "mitigate huge delay-variations caused by process,
voltage, temp, etc." (booth 3041) Ask for Marc Renaudin.
Magma Talus Design has added a 'congestion blob' cross-probing back
to/from your RTL source code plus Syntests' advanced DFT tool. The
placed-gates output works well with either PrimeTime or new Tekton.
Marvell, IDT, Sigma, Emulex, Vitesse, EXAR, Maxim, eSilicon uses it.
(booth 1743) Ask for Mark Richards. Freebie: ear buds
Cadence RTL Compiler is pushing low power RTL synthesis targeting
small die sizes and ARM core A15/A9 designs. Also does power-aware
DFT insertion and analysis, and physical synthesis. Users are
Freescale, Spansion, PMC Sierra. RC did well vs DC in ESNUG 492 #1.
(booth 2237) Ask for David Stratman. Freebie: t-shirt
11.) TSMC is everywhere showing off its Ref Flow 12.0, AMS Ref Flow 2.0,
and RF Ref Design Kit 3.0 swimming with PDKs, foundation IP, std cell
libs, standard I/O, eFuse and mem compilers; and IP like USB, PCI,
DDR/LPDDR. Ref Flow 12.0 will show TSMC's 20 nm Transparent Double
Patterning design solution. Has 89 tape-outs at 28 nm in the pipe.
(booth 2535) Ask for Tom Quan. Freebie: toolkit
Globalfoundries is acting just like TSMC in that GF is showing off a
bunch of EDA "partners" in their booth, too. Of unique interest are
Lorentz Solutions PeakView for EM-based synthesis, extraction, and
modeling; Analog Bits for SRAMs & T-CAMs and analog IP, Kilopass
NVM 40 nm, and Toppan photomasks. (booth 1517) Ask for Walter Ng.
MOSIS combines many companies' designs into one wafer run for low
volume and prototyping production. GF, IBM, TSMC. (booth 1509)
IMEC Europractice does low cost ASIC prototyping and small volume
production. 0.8 um to 40 nm from ON, IHP, TSMC, UMC. (booth 3027)
CMP is a manufacturing service for prototyping and low volume IC
production. CMOS, SiGe, BiCMOS from ST. 20 nm FDSOI from CEA-LETI.
3D-IC from Globalfoundries. (booth 2426)
12.) Ausdia Timevision generates/verifies/manages your timing constraints
for STA, synthesis, and P&R. RTL or gate, capacity 200 M instances,
5000+ clocks, mode management: discovery/merge/conflict/coverage.
(booth 3142) Ask for Sam Appleton. Freebie: keyboard cleaner doll
Tuscany Pinpoint is an EDA aware web-based status tool. It can be
Questa, Primetime, Atoptech, Quartz, Silicon Frontline, ICC, FE; it's
EDA vendor neutral! Was #3 with users last year. See DAC 10 #3.
(booth 3349) Ask for Matt Michels. Freebie: pens
Satin VIP Lane does design quality monitoring by generating dashboards
from logfiles, text files, specs, documentation, user SQL databases,
URLs to tell how "good" your chip is. ST and ST-Ericsson uses it.
(booth 3224) Ask for Michel Tabusse. Freebie: strawberries
Cadence Enterprise Manager (IEM) lets you run CDNS verification SW on
your own private server farm and collects metrics across these runs.
(booth 2237) Ask for Tom Anderson. Freebie: t-shirt
13.) Synopsys PrimeTime now claims "500 M instances" and "5X-10X better
runtimes for the full chip timing analysis and 5X-10X smaller memory
footprint compared with classic flat analysis". Also there's a
PrimeTime SIG on Monday. Ask for Robert Hoogenstryd. (booth 3433)
Magma Tekton added 2D AOCV, noise glitch analysis, setup & hold opto
and parallel processing. 2X speed up. "Ran one scenario 40 nm 18 M
inst in 1 hour with SI and OCV/CRPR. PrimeTime was 4.5 hours, same
# of threads. Tekton MMMC took 2 hours for 10 scenarios, 8 threads."
(booth 1743) Ask for Ruben Molina. Freebie: ear buds
Cadence ETS is bragging of "Multi Mode Multi Corner (MMMC) signoff",
an automatic timing analysis to generate an ECO repair file fixing
all your chip's hold violations. CDNS won't say if anyone is using
MMMC signoff. Ask Hitendra Divecha. (booth 2237) Freebie: t-shirt
Extreme GoldTime does static timing analysis, plus SI, POCV, and full-
statistical TA. New power analysis and POCV variational analysis
qualified by TSMC at 28 nm. 2X speed-up year-over-year. "GoldTime
does STA + SI + POCV analysis on 10 M instances in 1 hour." Claims
50 tape-outs. Broadcom, Netlogic, Nvidia, PMC-Sierra, Qualcomm
uses it. (booth 2939) Ask for Emre Tuncer. Freebie: stuffed tiger
CLK-DA AOCV FX does "really fast AOCV table generation so you can
reduce pessimism safely! Do an entire lib; clock & data, every cell,
every arc, every load/slew in 2-3 days using a typical 8 CPU machine."
CLK-DA Path FX replaces SPICE and Monte Carlo SPICE sims. Works with
Primetime. Does SI crosstalk analysis and block-level timing models.
(booth 1043) Ask for Lee LaFrance. Freebie: key chains
ASICserve BooStart is a PrimeTime add-on that analyzes and optimizes
PrimeTime timing constraints and use. Rumor is CDNS tried to acquire
this tool. (booth 2015) Ask for Yossi Rindner. Freebie: ear buds
14.) Mentor Questa Intelligent Testbench claims "it gets coverage during
functional sim 10x to 100x faster than anything else." Atheros got
50x. Applied Micro 100x. Ask for Mark Olen. (booth 1542)
Axiom MPSim is a full System Verilog and OpenVera simulator with OVM,
VMM and UVM support plus coverage analysis. Fast multi-CPU runs that
auto-partition your designs, apps, and testbench. Cortina, NetLogic
use it. Ask for Tarak Parikh (booth 3320) Freebie: water bottle
Real Intent Ascent Lint 1.4 generates an incremental report, which
shows violation differences between runs. A way to waive violations
from the command line, design source files or GUI. A way to focus
on specific portions of your design. New rules for arithmetic
data path checking, dubious logic modeling, and RTL coding policy.
(booth 2131) Ask for Shiva Borzin. Freebie: mini-stapler
Atrenta SpyGlass Lint does formal on RTL problems without assertion
input. Checks FSM, dead code, parallel and full-case pragmas, bus
contention, floating bus detection and debug for root cause analysis.
(booth 1643) Ask for Namit Gupta. Freebie: t-shirt
Cadence Incisive (NC-Sim) has new coverage analysis, SimVision, and
IVB capture tools. Does UVM for SystemC and Specman e, mixed-signal
and low-power. Claims a 30% speed-up. Users Broadcom and Boeing.
(booth 2237) Ask for Adam Sherer. Freebie: t-shirt
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
Supports UVM 1.0 and encryption P1735. Westinghouse, Teradyne use it.
(booth 1243) Ask for Dima Melnik. Freebie: aluminum water bottles
Cadence Specman "e" added stuff "not yet feasible in System Verilog
like reseeding and dynamically loading new tests to improve overall
coverage." UVM, SystemC. SNPS and MENT both support Specman "e",
but want to sell you away from it. Users liked "e" in ESNUG 488 #5.
(booth 2237) Ask for Tom Anderson. Freebie: t-shirt
Amiq DVT IDE provides IDE capabilities for CDNS Specman "e", System
Verilog, VHDL. Visual C like stuff. This year a Specman debugger and
upgraded UVM support. Ask for Cristian Amitroaie. (booth 2114)
Mentor Certe Testbench Studio is a Eclipse-based environment for rapid
creation of UVM and OVM testbenches. Ask Mark Olen. (booth 1542)
15.) This year Cadence Virtuoso ADE has RelXpert - circuit degradation
over time due to Hot Carrier Injection (HCI) and Negative Bias
Temperature Instability (NBTI); Worst Case Corners - simulation goes
from 100's of corner cases to a few; High-Sigma Yield - cuts Monte
Carlo trials without reducing coverage. Users are Qualcomm, NXP,
ST, Renesas. Ask for Rama Jupalli. (booth 2237) Freebie: t-shirt
NEW TOOL - Virtuoso Parasitic Aware Designer. It's a formal tool for
managing pre- and post-layout parasitics and re-simulations. Debug
environment when simulations fail due to parasitics (estimated or
actual). Understands parasitic sensitivities. Ask Jeremiah Cessna.
NEW TOOL - Another new tool for Virtuoso users is its ViSO PVS. It
lets custom designers do DRC/LVS *during* the design flow. ViSO
meshes nicely with Virtuoso DRD (Design Rule Driven) layout, too!
Runs in "live" or "batch" mode. Ask for Hitendra Divecha.
NEW TOOL - In addition, there's something called "Circuit Prospector"
inside Virtuoso simular to TSMC iConstraints. Ask for Mike Kelly.
To quiet the embarrassing $44 million Apache Redhawk IR-drop problem,
CDNS Marketing is slapping the words "Virtuoso" and "Encounter" all
over their old Simplex and Celestry tools. Ask for John Kane.
They'll also show Modgens, which are a constraint that enables near
instant layout of regular structures (like a differential pair), now
integrated in the Virtuoso Spaced Based Router. Ask for Yuval Shay.
And Virtuoso Viva is CDNS's answer to Synopsys Waveview (Sandworks),
Mentor EZWave, Magma Finewave. "Views analog and digital waveforms
simultaneously. Special emphasis given to loading gigabyte transient
databases in moments vs. hours." Ask for Steven Lewis. (booth 2237)
Mentor Pyxis Custom Router offers fully automated hybrid grid and
shape-based routing, and multi-processor & distributed computing.
"It handles hierarchical cells without the need for abstracts,
propagates signal constraints up through the hierarchy to ensure clean
routing at all levels and allows the user to mix and match devices,
standard cells and hierarchical cells." Pyxis is OpenAccess based.
Pyxis V10.0 has a "concurrent editing" feature that lets multiple
users edit simultaneously within a single cell. The users can be
anywhere on a secure LAN and it automatically manages the database
changes and synchronization. Pyxis is qualified by TSMC at 28 nm
with hierarchical DFM. (booth 1542) Ask for Mitch Heins.
Magma Titan Whole Enchilada is LAVA's all-in-one wrap-up all of their
analog layout tools in one monster flow; analog optimization (ADX),
shape based router (SBR), analog prototyping and placement (AVP), and
analog layout migration (ALX); a complete circuit-to-layout design
flow capturing and optimizing analog circuit for a target process and
specifications using a library of analog building blocks (FlexCells),
followed by device-level placement and routing of the analog circuits.
(booth 1743) Ask for Jerry Zhao. Freebie: ear buds & shredded cheese
Solido Variation Designer is a custom IC tool that analyzes variation
impact on design specs, IDs hotspots, & fixes specification failures.
New high-sigma Monte Carlo+ tool to manage local random/mismatch and
global random variation to 4-6 sigma. Tests PVT and proximity wells.
TSMC Advanced AMS Ref Flow 2.0. Was #2 at DAC with users last year.
See DAC 10 #2. (booth 3138) Ask for Amit Gupta. Freebie: none
ClioSoft VDD is a Virtuoso add-on that does a visual diff on Virtuoso
data. Quickly compare two versions of a schematic or layout by
graphically highlighting the differences directly in the Virtuoso
design editor. Supports both IC 5.x (CDBA) and IC 6.x (OpenAccess).
Added a hierarchy based comparison; select the top-level cellview and
labels to compare. VDD goes through hierarchy & displays all changes
found. (booth 1535) Ask for Michael Henrie. Freebie: poker game
SkillCAD has three new Virtuoso IC5/IC6 add-ons. V-Editor integrates
editing steps of shape selecting, pushing and design rule enforcing
into one step, polygon pushing and bus editing. rRouter handles 100's
of connections and adjusts width & wiggle patterns. rChecker measures
path/polygon connection resistances. Ask Pengwei Qian. (booth 3025)
Tool Corp Lavis is a superfast 100 Gbyte layout visualization tool for
GDSII, LEF/DEF, Oasis, DRC LVS interface, Boolean layer overlay, node
tracing, cross section 3D view, F/A FIB, IR drop, path extraction,
power short checkers, connectivity/redundant via checker. For simple
edits and hot fixes. Used by Renesas, Fujitsu, Toshiba, Elpida, TSMC.
(booth 2226) Ask for Yukihiro Masuda. Freebie: yo-yo
AnaGlobe Thunder is the "only layout editor that can handle 100G+ GDS
OASIS/OpenAccess. 30X performance gain. Does normal viewing/editing
plus LVL (100X faster than Calibre) and metal density checker." Used
by Nvidia, Marvell, AMCC, Pyramid, TSMC, UMC, VIS, SMIC, HiSilicon.
(booth 3016) Ask for Yan Lin. Freebie: none
NEW TOOLS -- Analog Rails Mr. Fixit automatically repairs layout, both
DRC and LVS. Placer generates layouts of ADC, SC-Filters, biases, and
digital. "Automatic! No scripting needed!" Router is electrically
aware, handles EM, shields, double vias, welltaps. Layout Editor
crossprobes even when flattened. Optimizer does auto xistor sizing.
Mismatch tool does variation-aware. Also has IR-drop and migration.
(booth 1631) Ask for Cliff Wiener. Freebie: Cliff's surly attitude
Ciranova Helix automatic custom layout. 28 nm support plus density.
New early-estimation mode "within 1% of tapeout area on a 2,000-
transistor design." Claim to be seeing 10-20% less area vs handcraft.
(booth 2517) Ask for Dave Millman.
Pulsic Unity Analog Router was "selected as the analog routing flow
by the STARC consortium for its Analog/Mixed-Signal Reference Flow
in competition with at least 3 other routers." Chip Planner does
hierarchical full chip planning. Bus Planner is a GUI based guide-
driven tool for inserting large numbers (100+) of very wide bit
buses (up to 1024). Signal Planner does specialized complex routing
topologies ("L", "C", "H", "J") for inter-block routing. Power
Planner does constraint-aware, multi-domain power grids. And ECOs.
(booth 2214) Ask for Mark Waller. Freebie: key chain
Tanner EDA sells S-Edit schematic capture, L-Edit custom layout,
HiPer Verify DRC, and T-Spice SPICE. Founded in 1988, and known
for their "cost effective" pricing. Not bad for the cheap seats.
(booth 2231) Ask for Nicolas Williams. Freebie: microfiber cloth
Mentor Calibre RealTime now lets you do physical signoff *DURING*
your AMS custom design. Provides instant feedback on DRC violations
and how to fix them in either Mentor IC Station or SpringSoft Laker.
Mosys, Mobius uses it. (booth 1542) Ask for Joe Davis.
Apache Totem is a transistor-level power/ground noise analysis tool
used for verification of custom designs. It concurrently analyzes
the power noise propagation through power delivery network, substrate
network, & package/PCB network. Full-chip dynamic electro-migration
(booth 2448) Ask for Aveek Sarkar. Freebie: stuffed animal
AnaGlobe Golf was "created on a request by PNR engineers who didn't
want to discuss a PCell spec with the PCell programming team and wait
one week for the delivery. With Golf, you use a GUI and NO SKILL code
to design a Pcell easily." (booth 3016) Ask for Yan Lin.
Prolific ProGenesis Elite does 20 nm standard-cell library creation.
"Handles the over-constraints of 20 nm design rules and lithography."
(booth 2331) Ask for Paul de Dood. Freebie: t-shirts
TSMC RF Reference Design Kit 3.0 is a silicon correlated, 60 GHz
millimeter wave design kit, plus "an innovative way to design
inductors through EM simulation. Ask for Tom Quan. (booth 2535)
Rumor is the Virtuoso competitors are telling the Virtuoso users that
Virtuoso supports PyCells. "#$%@ NO!!!" is the CDNS reply I got.
16.) Axiom MCDV is for multiple, synchronous clock domains, "finding errors
in synchronization is virtually impossible using simulation alone."
No testbench required; only required input is your source code. IDs
master, gated, derived clocks, CDCs and many types of synchronizers.
Ask for Tarak Parikh (booth 3320) Freebie: water bottle
Real Intent Meridian CDC 3.1 "performs fast and comprehensive CDC
sign-off verification." Did 130 M gates with 180 clock domains in
10 hours. Now better debugging and links to dynamic simulation.
Nvidia, Broadcom, Brocade, Samsung, Northrup Grumman uses them.
(booth 2131) Ask for Jin Zhang. Freebie: mini-staplers
Atrenta SpyGlass CDC looks at all asynchronous clock crossings across
multiple levels of logic from the architectural level, instead of
classifying each crossing as a double flop, FIFO or a handshake
protocol. This finds all the correct crossings, the chip killers,
and fewer false violations. ST, TI, Fujitsu, Emulex, Brocade use it.
(booth 1643) Ask for Kiran Vittal. Freebie: t-shirt
Blue Pearl VVE lets you rapidly identify CDC's and false & multi-cycle
paths and view them in a schematic window along with a logical trail
detailing the conflicts which caused the occurrence. Users Fujitsu,
KLA Tencor. (booth 1035) Ask for Scott Bloom. Freebie: mug
FishTail Focus merges multi-mode P&R constraints into one super mode
SDC constraint. "One customer's P&R runtimes dropped from 21 hours to
10 hours, memory usage drop from 21 GB to 8 GB, and # of violating
paths drop from 9300 to 1200." Conexant, Broadcom, STARC, Toshiba
uses it. (booth 1304) Ask for Ajay Daga.
17.) Cadence bought Altos which has "new packet technology for improved
throughput of large libs, automation for complex custom & I/O cells,
and large embedded memories, fast accurate AOCV table generation."
Rumor is Altos is TSMC's preferred characterization tool. CDNS is
adding hooks into Spectre and MMsim APS; bangs head on against Magma
FineSim and Synopsys HSIM. (booth 2237) Ask for Jim McCanny.
Calibre xACT 3D parasitic extraction "based on extremely efficient
field solver algorithms." (booth 1542) Ask for Carey Robertson.
Magma QCP does 2.5D signoff extraction. Claims 20x faster vs Star-RC.
"1.2 M nets extracted 5 corners (all in one shot) in 13 min; Star-RC
took 2 hours." Within 2% of QuickCapNX. Does "multicorner extraction
without requiring one job per corner." Qualified by TSMC for 28 nm.
(booth 1743) Ask for Surbhi Agarwal. Freebie: ear buds
EDxact Comanche Parasitics Analyzer takes schematic, extracted netlist
plus parasitics and layout as input. Does analyses to determine
electrical properties related to the interconnects, such as pin-2-pin
resistance, cross-coupling, etc. Pinpoints trouble. Capacity beyond
10 GB parasitics. GUI into SpringSoft's Laker allows cross-probing.
ST-Ericsson, AMD use it. (booth 2118) Ask for Youri Leclercq.
NEW TOOL - Extreme-DA GoldX does parasitic extraction for digital
designs, 10 million nets/hour performance. "Accuracy is stable across
any number of CPUs." Timing sign-off and ECO loops are 3X-5X faster
if GoldX is used with GoldTime. (booth 2939) Ask for Emre Tuncer.
Silicon Frontline H3D does hierarchical parasitic extraction providing
a hierarchical post-layout netlist. Provides sub-linear performance,
which means the larger your design, the faster the extraction per net.
(booth 3017) Ask for Yuri Feinberg. Freebie: pens
Sagantec SiFix does silicon design migration to smaller processes
correction of DRC violations. First successful 28 nm migrations!
New 2D DRC correction engine with 99% success rate for complex rules.
(booth 1432) Ask for Dan Blakely. Freebie: none
Magma SiliconSmart ACE is the olde RLC QuickCAP, the "gold-standard
3D capacitance extractor". It's legacy goes from 0.5 um to 28 nm.
This year they're chatting up how tight FineSim and SiS ACE are.
Rumor is Altos and SiS ACE were fierce rivals, with SiS 4x faster.
(booth 1743) Ask for Jerry Zhao. Freebie: ear buds
18.) Rocketick RocketSim loads your Verilog source into 100's of GPUs and
runs as a co-sim to Cadence NCSim, Synopsys VCS, Mentor ModelSim.
Mellanox got a 14X speed up while RAM use went down 83% from 192 GB
to 32 GB. Ask for Uri Tal. (booth 2914) Freebie: chocolates
This year the EVE ZeBu-Server capacity has expanded to 2,000,000,000
ASIC gates. Yup, that's 2 billion! Pennies per gate. ST, Renesas,
Toshiba, Fujitsu, Zoran, Konica-Minolta, ARM, LG, Qualcomm uses them.
New VIP transactors for PCIe Gen 3, Ethernet, TLM-2, I2C, ARM VSTREAM,
HDMI. Ask for Lauro Rizzatti. (booth 2836) Freebie: water bottle
Dini's Spartan-6 FPGA Boards and Stratix-4 FPGA Boards. "One single
DN7020k10 configured with 20 Altera Stratix IV 4SE820 FPGAs can
emulate up to 130 million ASIC gates." Users TI, Qualcomm, Intel.
(booth 3316) Ask for Mike Dini. Freebie: none
Cadence Rapid Prototyping Platform is an FPGA-based prototyper almost
exactly like Synopsys HAPS or the systems that the Dini Group sells.
(booth 2237) Ask for Philip deBuren. Freebie: t-shirt.
Gidel PROC_SoC10 is an FPGA-based prototyping system that does 120 M
ASIC gates each; and can be connected to do 360 M ASIC gates. System
clock up to 300 Mhz. (booth 2725) Ask for Reuven Wientraub.
BEEcube BEE3/BEE4 is yet another FPGA-based prototyping system at DAC.
(booth 2431) Ask for Joseph Rothman. Freebie: stress bees
Veridae Certus does multi-FPGA emulation of your ASIC. Did an eval on
13 FPGA Virtex-6 Dini board, with a complete synchronized VCD waveform
across all 13 FPGAs running at full-speed. "No clocking restrictions.
No clock frequency limits. No special I/O. No special connectors.
No CAD flow changes required." Ask for Andrew Hughes. (booth 3212)
SpringSoft ProtoLink Probe Visualizer provides "real-time visibility
inside a FPGA prototype board (thousands of signals over millions of
cycles) to enable RTL debugging with Verdi to cut debug time in half."
Works with Dini, Gidel, HAPS System, TAI Logic Module, and ChipIt.
(booth 2043) Ask for Sam Miller. Freebie: superhero squeeze toy
Aldec HES rides on top of one of these FPGA-based protypers (above)
and gives "4 Mhz emulation up to 40 M ASIC gates". It does TLM with
SCE-MI 2.0. Qualcomm uses it. (booth 1243) Ask for Louie De Luna.
Last year Cadence Palladium XP scaled up to 2 B gates, 512 users, and
it could "hotswap" between SW simulation and HW acceleration modes.
This year they're giving no hard data; instead CDNS is just claiming
how vaguely great Palladium is. (booth 2237) Ask for Dave Allen.
Mentor Veloce used to compete here, too, but I haven't heard from them
this year... OMG! Has Carl Icahn already cut the Veloce group!??
19.) GateRocket RocketVision lets engineers verify and debug their FPGA
design -- NO IT'S NOT AN FPGA-BASED PROTOTYPER. It cuts down on
your many FPGA synthesis/place/route cycles. Used by Qualcomm.
(booth 3126) Ask for Dave Orecchio. Freebie: toy rocket
Mentor Precision Hi-Rel does FPGA synthesis mitigation against soft
errors like single event upsets (SEUs) and single event transients
(SETs). Includes safer FSM encoding and triple modular redundancy.
For medical & space. (booth 1542) Ask for Roger Do.
20.) Mentor Calibre PERC does electrical rule checking, including ESD
validation and identification of inappropriate connections between
multiple power supplies in mixed-signal ICs. Used by Via Tech,
Fujitsu, On Semi, Faraday. (booth 1383) Ask for Carey Robertson.
Magma Quartz DRC/LVS now does at 20 nm ERC, dummy fill, XOR checking,
double patterning decompositioning, and patterning matching. It's
also known for speed. Used by IBM, Samsung, Nvidia, TI, Wintegra.
(booth 1743) Ask for Vijay Patri. Freebie: ear buds
For DRC/LVS, Cadence is showing its Interactive Short Locator (ISL)
plus Graphical LVS Debug. Claims no one else has a short locator.
"ERC run time 1.5 hours with 8 CPUs. Without ISL, designers spent
9 hours to clean a short, but only 3 hours with ISL." Fujitsu uses
it. (booth 2237) Ask for Hitendra Divecha. Freebie: t-shirt
21.) Cadence Encounter Test Low Power ATPG .... "Synopsys Low Power ATPG
causes a vector count explosion which sends tester time through the
roof. Encounter Low Power ATPG easily limits test vector switching
activity levels to prevent false fails while keeping test vector count
and test time growth to a minimum." Qualcomm, IBM, Fujitsu, Hitachi
uses it. (booth 2237) Ask for Lisa Jensen. Freebie: t-shirt
Mentor Tessent now supports 3D-IC testing with ATPG and BIST for TSMC
silicon interposers and TSVs. (booth 1542) Ask for Steve Pateras.
NEW TOOL - Avery Insight DFT does Verilog RTL at-speed Small Delay
Defect (SDD) and Path Delay Fault (PDF) DFT analysis and repair.
(booth 1605) Ask for Chris Browy. Freebie: LED flashlight
22.) ClioSoft SOS configuration management & version control integrated
with Cadence Virtuoso, SpringSoft Laker, Mentor ICstudio. SOS now
integrates with Mentor's new DMGR interface for IC Station and has
a plugin for Eclipse IDE. Users Analog Devices, Broadcom, Dongbu,
Huawei, IDT, Lawrence Berkeley Labs, Oracle, Marvell, MIT Lincoln
Labs, Netlogic, Northrop Grumman, Tektronix, Toshiba, TSMC, Zarlink.
(booth 1535) Ask for Karim Khalfan. Freebie: poker/blackjack game
IC Manage GDP is also a design data management system. This year
they added ICMSdiff, a schematic diff for Virtuoso, and a newly
designed visual client for digital designers. Users AMD, Cypress,
CSR, NVidia, Xilinx, Maxim, MediaTek, Ikanos, SanDisk, Spansion.
(booth 1617) Ask Shiv Sikand. Freebie: "Reuse" peanut butter cups
Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA tool developers. This year they've added a new Perl interface.
Synopsys, Magma, Apache, EVE, SpringSoft, IBM, Infineon, NXP uses
them. (booth 2733) Ask for Rob Dekker. Freebie: stuffed giraffe
23.) If you're at DAC and you want to hook up to talk trash, on DAC Sunday
I'll be at Gary Smith's pre-DAC talk at:
Sunday 7:00-8:00 pm, Omni Hotel, Ballroom Salon AB
and on DAC Monday, I'll be moderating my DAC "Headaches" Panel at:
Monday, 3:30-4:30 pm, DAC meeting room #25A
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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