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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2007"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this to use as an unofficial guide
to the San Diego DAC exhibit floor next week.
1.) If you can eval only one DFM vendor, ClearShape is the one you must
see. At 65 nm, ClearShape's model-based approach competes with
the mostly rule-based Blaze DFM (who just added models with their
Aprio buy) or the re-packaged OPC tools from Mentor and Synopsys.
TSMC, UMC, and Chartered-IBM-Samsung have validated InShape for
65 nm. At DAC, TI will now show InShape and OutPerform at 45 nm!
Two rumors: 1.) Joe Sawicki, a Mentor DFM bigwig, bailed at the
last minute on the DVcon Troublemakers Panel cause he didn't want
to square off against ClearShape; 2.) Cadence offered $100M for
ClearShape. (booth 7164) Ask for Nitin Deo. Freebie: laser pen
For DFM from the Big 4, you'll first want to talk to Mentor cause
they were talking OPC and RET waaaaaaay before any of us could
even spell it. They're showing their Calibre LFD, YieldAnalyzer,
and YieldEnhancer tools this DAC. (booth 3676) For LFD, ask for
Jean-Marie Brunet; for the Yield* stuff ask for David Abercrombie.
(While there you might want ask "What is Joe Sawicki afraid of?")
Synopsys is showing its PrimeYield LCC, which plays off of the
Avanti Proteus OPC. Their cheesy marketing claim is "no false
positives, no escapes." (booth 5278) Ask for Rahul Kapoor.
For random defect modeling DFM, check out Ponte. Qualcomm uses
it. (booth 4360) Ask for Subra Nathan. Freebie: playing cards
Magma will showcase automatic, incremental avoidance and surgical
repair for hot spots, CAA, etc. (booth 4578) Ask for John Lee.
And remember Mike Gianfagna? That exceptional CEO at Aprio who
laid himself off, instead of his employees, when his sales failed?
He's now a VP at ASML-Brion. (booth 7282) Freebie: integrity
2.) In my book, Mentor's 0-In CDC and the other clock domain crossing
tools have arrived. And I'm a big fan of talking to the guys who
were there first, namely the 0-In CDC guys. (booth 3676) Ask
for Ping Yeung or Mark Eslinger. Freebie: olde 0-In shirts
The other players are: Atrenta SpyGlass-CDC, (booth 6082), ask for
Kiran Vittal or Shaker Sarwary. Freebie: magnetic darts set
Real Intent also has a tool called Meridian CDC, (booth 5260), ask
for Rich Faris. Freebie: frisbees and tacky sunglasses
Cadence has something Conformal (naturally) that might dabble in
CDC, but I have no info if it's showing at this DAC or not.
3.) For "coverage convergence" tools, see Nusym DeNebulator. Details
are at DVcon07 #6. Nusym seems to be pretty much only beta right
now. The infamous Lucio Lanza and John Sanguinetti are investors.
(booth 1572) Ask for Jayant Nagda. Freebie: apples
The other player is Certess Certitude. ST, Juniper, and Aquantia
are current customers. Details at DVcon07 #5. (booth 7678) Ask
for Joerg Grosse or Mark Hampton. Freebie: T-shirts
Neither are typical code coverage tools! Read the detail links!
4.) Sierra this year is showing off three new parts to its Olympus-SoC
P&R tool focused on 45 nm layout: 1.) an internal CTS tool which
handles resistance variation across MCMM, 2.) FalconGR, their new
router that trades off layer assignments with buffering, and 3.)
a new internal shape-based DRC tool. One big thing about Sierra
is that its memory footprint is extremely efficient. For example,
a 27 M instance design loaded FLAT into Sierra with 40 physical
blocks and no abstraction using only 42 GB. On the gossip side,
rumor is that Mentor is buying Sierra for around $100 million.
(booth 6682) Ask for Sudhakar Jilla. Freebie: 3-in-1 laser pen
A new unknown face in layout is Nanovata. They claim to "optimize
a layout to gain the best timing/SI, yield and manufacturability
towards the sign-off quality on top of what current tools provide.
Plug-and-play with existing P&R tools." (booth 672) Ask JT Li.
One odd thing about Nanovata, though. It sounds an awful lot like
the Athena Design Milos tool from last year. Seriously, an awful
lot. (booth 1264) It's time to ask John Murphy what he thinks...
5.) The best Catch-22 tool I plan to see at this DAC is GateRocket.
It cleverly using FPGAs to validate FPGAs. It uses a Xilinx
Virtex-4 LX-200 (or an Altera Stratix II 180) board that goes
into your PC drive bay that they call a "RocketDrive". First
off, you synth/P&R your FPGA design, dump it into the RD, the
simulator on my PC can then directly access the RD via the PLI
and happily run. All the control is through PLI calls. They
can run up to 8 RocketDrives in parallel. It's quick, dirty,
cheap, and way cool! (booth 2559) Ask for Dave Orecchio.
6.) This year the Mentor Calibre nmDRC marketing folks are gushing
about how their DRC baby can use multi-termed checks that have up
to hundreds of terms each -- whereas Cadence/Synopsys/Mojave DRC
can't. IBM will talking about this at their booth. Also this
year they can read and write LEF/DEF, Milkway, OpenAccess -- with
the only holdout being Magma Volcano because Magma won't let them!
(booth 3676) Ask for Michael White. Freebie: colorful kite
Magma Mojave Quartz DRC this year features incremental DRCs, it
automatically recognizes changes to your database and only the
changed portion is re-analyzed. The first rev supports Volcano
DB only, next rev GDSII. (booth 4578) Ask for John Lee.
The Synopsys Hercules PVS cronies are jumping into this fray by
claiming their baby finds design shorts super uber quick now. On
a 300 M transistor design, 90 nm with 8 layer metal, 16x16 mm2
in 20 Gb GDSII, Hercules PVS found the design shorts in 1 hour.
(booth 5278) Ask for Marilyn Adan. Freebie: gold logo pens
7.) I generally don't like pointing EDA users to go look at demos of
tool flows because they're invariably traps designed to lock you
into one vendor's tools. But since the CPF vs. UPF wars are a
raging, I'll make an exception. On the proprietary Cadence CPF
side you should see their "Design with Power" demo. They CLAIM
it's great because it's a power flow that works NOW, while the
pro-UPF flows are very hypothetical and not fully working yet.
(booth 2753) Ask for Michael Munsey. Freebie: cloth tote bag
On the anti-Cadence "open" side for UPF, for Synopsys there's the
"End-to-End Power Management Solution" UPF demo. (booth 5278)
Ask for Gal Hasson. Like the olde RMM, they're even throwing in
a "Low Power Methodology Manual (LPMM)" they co-wrote with ARM.
Ask Phil Dworsky at Synopsys or Tim Holden at ARM. (booth 5273)
For Magma, see their "Ultra Low-Power Chip Design" UPF demo which
features their new Talus Power and Quartz Rail. (booth 4578)
Ask for Arvind Narayanan. Freebie: DVD cleaner
For Mentor, see their "Questa Power Aware" UPF demo which uses
O-In CDC, FormalPro, and their new Questa PA tool. (booth 3676)
Ask Steve Bailey. Freebie: colorful kites
And there's even a separate UPF "Power of One" (booth 7860) where
they're demoing ArchPro, Axiom, Synopsys, Magma, and Mentor UPF
flows that work today. Ask for Dennis Brophy or Yatin Trivedi.
Freebie: hand-crank flashlight/cell phone charger
8.) For synthesis, the Synopsys guys are giving a first peek at the
7.12 release of DC-Topo, which on paper sounds neat, because it
will do analysis/reporting/optimization of congestion problems
while *in* synthesis. (booth 5278) Ask for Priti Vijayvargiya.
In addition, the Cadence Get2chip RTL Compiler folks will also be
previewing their own physical prediction/analysis/optimization
pre- & post- floorplanning hooks into First Encounter -- which
their marketing calls "Design With Physical". I like the idea.
(booth 2753) Ask for Jack Erickson. Freebie: cloth tote bag
The Magma Blaste Create people are pimping overall flows more
this year, rather than showing their synthesis alone. Too bad.
(booth 4578) Ask for Sanjay Bali. Freebie: DVD cleaner
9.) In a ballsy all-or-nothing gambit, FishTail is asking engineers
to bring in their designs to DAC and they'll run their Focus and
Confirm false/multi-cycle path tools on it. No carefully tested
demo? And on real life designs?! Holy shit! Talk about balls!
(booth 7669) Ask for Ajay Daga. Freebie: iPods for real designs
Atrenta, another serious false/multi-cycle path tools player, has
SpyGlass Constraints. (booth 6082) Ask for Sridhar Gangadharan.
Blue Pearl (booth 4660) made noise about this last DAC, but they
may have dropped it. Don't know. Also, Cadence has something in
this space, too, but God knows if they're showing it at this DAC.
And my hat goes off to the Aldec folks because they're charging
into blood thirsty RTL linter market with their new "Alint" tool.
(booth 5860) Ask for David Rinehart. Freebie: 5-ball pendulum
10.) On power, Sequence is showing the new CoolTime SSN where "current
manual SSN analysis methodologies are time-consuming, error prone,
and capacity constrained, often requiring a week for a correct
simulation netlist; CoolTime SSN takes 1 hour" and which competes
directly against Apache RedHawk. Sequence is also showing off the
new hot spot viewer cross-probed to RTL in its PowerTheater 65.
(booth 4860) Ask for Rama Rao. Freebie: a 512-MB USB drive
The new ArchPro Maveric appears to be an RTL architectural power
profiler that can somehow spot your legal multi-voltage sequences.
(booth 1580) Ask for Srikanth Jadcherla. Freebie: a mini-mouse
The new Calypto PowerPro CG also reads in RTL and spits out power
optimized RTL. They yarp about sequential clock gating and enable
logic. (booth 2680) Ask for Mitch Dale. Freebie: chocolates
In a sweetheart duet, Blaze DFM and TSMC are presenting a hands-on
tutorial on how to get the most from Blaze MO on TSMC 65 nm. MO
is their leakage power tool. (booth 1884) Ask for Dave Reed.
Also you might want to check out Atrenta Spyglass Power tool, too.
(booth 6082) Ask for Michael Carrell. Freebie: magnetic darts
11.) I laughed when I saw, as a big F.U. to Cadence, the DAC Committee
put the Interoperable Pcell Libs (IPL) coalition (booth 2957) less
than 50 feet from Cadence (booth 2753)! Last year Cadence had
held a rival show 2 blocks from DAC; which pissed off the DAC
organizers to no end. The IPL Gang of Seven (Synopsys, Mentor,
Magma, SiCanvas, AWR, SiNavigator, and Ciranova) hope to break
the Cadence grip on Pcell & SKILL to bust the Virtuoso monopoly.
Ask for Jingwen Yuan or George Janac. Freebie: lunch cooler bag
12.) For Virtuoso alternatives, you might want to give SiCanvas Laker
a look. This DAC they're yarping about RDR for "a preventative
approach to DFM" and "running natively on a true Open Access
database." They used to be primarily only interested in Taiwan
fab customers, but they're thinking of broadening their markets
now. Rumor has it that Magma is in talks to acquire SiCanvas.
(booth 2379) Ask for Brady Logan. Freebie: anti-SKILL t-shirt
Pulsic Lyric and Unity also have a presence in the custom layout.
(booth 2060) Ask for Kevin Steptoe. Freebie: illuminated balls
Newbie Get2spec Analog Rails is NOT a power rail tool, but a
custom layout tool. It's based on OA and it can do automated
analog place and routing. (booth 2679) Ask for Cliff Wiener.
13.) For Virtuoso hangers-on, Silicon Navigator has its RDE Framework.
It does/runs/mimics/interacts with Pcells, Composer, SKILL, IPL,
Virtuoso, First Encounter, Simplex, DC, PrimeTime, PrimePower,
PhysOpt, Blast Fusion, Calibre, etc. to make a design evironment
with Open Access as its underlying database. CAD groups usually
buy RDE. (booth 2179) Ask for George Janac. Freebie: t-shirts
Sagantec Anaconda-M is the other Virtuoso-friendly tool that got
my interest. It accelerates analog physical design by automating
laborious tasks such as process migration, design-rules updates,
design ECOs, fine-tuning performance, etc. It's integrated into
Virtuoso, and can be driven from both schematic and layout views.
It's planned to be OA based. (booth 3259) Ask for Coby Zelnik.
14.) For the SystemC junkies, you'll of course want to check out Forte
Cynthesizer 3.3 because it now has hooks to Magma Blast Create and
Blast Fusion. Their idea now is to go from SystemC-to-GDSII.
(booth 3660) Ask for Brett Cline. Freebie: caricature and pens
And if you want to piss off Brett Cline this year, you might want
to take a look at Bluespec Compiler which Forte couldn't deal with
in Wiretap 070214. This year's demo is their new Azure IP libs
running uber fast on a EVE Zebu box. ST and Nokia use Bluespec.
(booth 6963) Ask for George Harper. Freebie: electronic Sudoku
For the ANSI C fans, the Mentor Catapult Synthesis folks are
releasing open source ANSI C++ synthesizable DSP IP libraries.
(booth 3676) Ask for Shawn McCloud. Freebie: colorful kites
And since Mentor bought Summit Design this year, the Vista SystemC
Debugger and IDE is now there, too. Ask for Zvika Amir.
ChipVision, who did Orinoco, supposedly has an unnamed tool that
does power-optimized synthesis on SystemC or ANSI C input, but it
won't be ready until December. (booth 6378) Ask Thomas Blaesi.
And if you're sick of all this SystemC/ANSI C crap, I suggest you
check out Axiom MP-Sim -- it's a Verilog, System Verilog, SystemC,
and OpenVera single kernel simulator that runs multi-CPU. Zoom!
(booth 4560) Ask for Tarak Parikh. Freebie: t-shirts and hats
15.) Carbon VSP converts Verilog/VHDL RTL into fast, cycle accurate
SystemC or ANSI C. Their goal is so "firmware engineers can debug
SoC models at ISS speeds." (booth 6870) Ask for Bill Neifert.
The new CoWare Virtual Platform sounds a lot like Synopsys-Virtio
or VaST. It's SW models that are "a replacement for the physical
development boards used in embedded software development debugging
and system integration." (booth 3373) Ask for Marc Serughetti.
The newbie Mirabilis VisualSim Architect seems to play in this
system-level niche, too. (booth 2657) Ask for Deepak Shankar.
Mimosys Clarity does HW/SW partitioning of embedded "C" source
code to create instruction set extensions for processors in HW.
Huh? (booth 863) Ask for Chris Podger. Freebie: t-shirt
16.) In FPGAs, the Mentor people won't be showing Leonardo Spectrum,
because their focus at this DAC is on Precision. For Precision
they're hyping their kick ass support for System Verilog, FPGA
physical design, plus their new automatic incremental synthesis.
(booth 3676) Ask for Roger Do. Freebie: multi-colored kite
In contrast, Synplicity is emphasizing their ASIC protyping tools
like Indentify Pro, which is similar to Novas Siloti, but without
the hassle of ChipScope or SignalTap or Temento; instead it's an
all-in-one debug tool. Takes the "ad hoc" out of FPGA protyping.
(booth 4278) Ask for Juergen Jaeger. Freebie: pens
17.) Almost anyone who's done verification knows about Synopsys' VMM,
but this new Teal and Truss open source equivalent caught me off
guard. It's by two guys: Mike Mintz and Robert Ekendahl who wrote
a book about C++ verification and it blossomed from there into
free libs for System Verilog and C++ that run in Questa and VCS,
with NC-Sim and Aldec in the planning. Sun, Freescale, Cisco, and
Avid are some of its users. The good people at Aldec (booth 5860)
are letting Mike Mintz present there. Freebie: temporary tatoos
In the unfair competition catagory, the Mentor folk are happily
calling on all Star Trek nerds (like myself!) to meet the actual
Brent Spiner (Data) and Marina Sirtis (Deanna Troi) on DAC Tuesday
for lunch in Room 29 A/B/C/D of the convention center -- where
the actors will be signing copies on the new version 3.0 of the
Mentor AVM cookbook! (booth 3676) Ask Jan Johnson to register.
Oh, yea, for those non-Trekkies, there's some sort of Synopsys VMM
something or another, too. Stu Sutherland, TI, and Analog Devices
might be involved with it. (booth 5278) Ask for Tom Borgstrom.
18.) I was surprized by Jasper's placing in the bug hunter stats of
my recent Verification Census. See DVcon07 #14. Yes, Magellan
and Mentor 0-In and Cadence IFV did well, but they each have
thousand-man armies selling them! Little olde Jasper has, well,
let's just say it's NOT a thousand-man army -- yet they kept up!
(booth 2853) Ask for Lawrence Loh. Freebie(s): T-shirts and
erasable 256-MB USB flash drives with JasperGold propaganda
On the secret side of DAC, Mentor is showing under NDA-only their
reincarntion of the olde Silicon Forest tool. Ask for Mark Olen
and the "Algorithmic Testbench Synthesis Suite". (booth 3676)
19.) Extreme DA is going to be showing their GoldTime SSTA tool (which
is a renaming of their old "XT"). This year they're emphasizing
multi-threading across multiple CPUs that share the same disk,
plus MCMM analysis. Their big claim is speed & capacity. They
claim 11 M placed instances (including SI) in 4 hours using only
10 GB. Their other claim is getting signoff capacity. In their
booth you'll see Samsung, UMC, TI, Toshiba, and ST. (booth 1561)
Ask for Mustafa Celik. Freebie: laser/LED flashlight combo
Synopsys, the big dog in STA, will be showing their PrimeTime-VX
statistical timing tool in a demo doing powwer recovery with ICC.
(booth 5278) Ask for Robert Hoogenstryd or Kayhan Kucukcakar.
Magma has some SSTA stuff, too, but only part of a larger demo.
(booth 4578) Ask for Behrooz Zahiri. Freebie: DVD cleaner
And tiny Incentia is also offering TimeCraft-ADVOCV which does
surprize! OCV. (booth 6177) Ask for Arthur Wei. Freebie: cards
For SSTA libs, check out Altos "Variety", (booth 1260), ask for
Jim McCanny. Freebie: T-shirts and, of course, Altoids mints
New for Synopsys at this DAC is Liberty NCX, a direct competitor
to Altos. (booth 5278) Ask for Nanda Gopal. Freebie: frisbee
Oddly behind the curve, newbie CLK DA is showing its Amber static
timing tool. Yup, static. It's claim to fame is that they use
multi-core, multi-processor compute platforms making it uber fast.
They also claim to be within 1% of PrimeTime and their SI flavor
is within 3% of SPICE. (booth 5671) Ask for Isadore Katz.
20.) While their rival, Zenasis, just went belly up a few months ago,
Prolific is alive and doing very well. This year Prolific is
hyping their final-pass power optimizer called "ProPower" that
works via cell selection and Vt swapping. It reduces active power
in addition to leakage power and reads SAIF files directly. Ask
for Paul de Dood. (booth 6064) Freebie: laser pointer pens
Other power-cell-tweaking-stuff rivals are: Nangate, which does a
weird sort of standard cell resynthesis. (booth 6860) Ask for
Jens Michelsen. Freebie: pens & clocks. And maybe Golden Gate,
(booth 7682) possibly does something in this space. Not sure.
21.) Apache is going up against the Rio Design folks this year in the
chip package I/O game. The Apache offering is called "Sentinel".
It seems to be much more power oriented and it's a sort of upgrade
to their Redhawk. For example, they claim to have run a full-chip
dynamic power simulation of a 40 M node extracted P/G network,
along with the package parasitics using RedHawk that took 8 hours.
The same chip modeled using the new Sentinel-CPM, plus the package
model running in SPICE took only 12 minutes. (booth 6382) Ask
for Aveek Sarkar. Freebie: cuddly stuffed animal
The Rio tool, RioMagic, focuses on "package escape", routability
and parasitics as part of the I/O planning process. Rio is the
established player here, with Apache as the new kid. Cadence and
Magma even invested in Rio. (booth 5982) Ask for Joel McGrath.
Freebie: pens. Sigrity (booth 5560) is rumored to have a tool,
OrbitIO, but it supposedly won't be ready until Q3.
I'm not sure, but you might also want to look at Optimal's PakSi-E
if this interests you. (booth 3063) Ask for Jamie Metcalfe.
22.) In the emulator/accelerator business, I'd recommend that you check
out the new Mentor Veloce box. Their big selling point vs. the
Cadence Palladium is that Veloce is a "dual engine" box; it can
run as a simulation accelerator -or- as an ICE emulator with all
the nice debugging hooks, etc. Cadence requires you to buy two
different boxes to do this. What's impressive is they already
have Broadcom, Mitsubishi, MIPS, and NXP as confirmed customers.
(booth 3676) Ask for Sanjay Sawant. Feebie: beach towels
And the EVE ZeBu people have had a kick ass year this year, with
revenue growth of 115% and 5 quarters of profitability. They
even bought out Tharas. Not bad for a start-up! (booth 4060)
Ask for Alain Raynaud. Freebie: sport water bottles
If you're into build-your-own ASIC protyping with big FPGAs, go
see the Hardi HAPS-50 which uses Xilinx Virtex-5 LX330's. Their
two first 2 boards are HAPS-52 and HAPS-54, and can handle up to
8 million ASIC gates. (booth 2869) Ask for John Hoekstra.
ProDesign CHIPit also plays in the build-your-own niche. This
year they have 3 new boxes: Copper V5, Iridium V5, & Platinum V5;
all based on Virtex-5's. (booth 6678) Ask for Markus Karg.
23.) For SPICE, see Nascentric AuSIM MT -- it's a Fast SPICE that's
multithreaded which makes it "10X or more faster than the fastest
competitor." They also claim no netlist cutting required.
(booth 7160) Ask for Steve McCarthy. Freebie: pump rocket
Berkeley has Analog FastSPICE and RF FastSPICE which is integrated
into Cadence Virtuoso ADE. They seem to be more accuracy fixated.
(booth 1780) Ask for Scott Guyton. Freebie: polo shirts
Agilent EEsof ADS seems to target the SI at Gbs+ data rate guys.
(booth 6364) Ask for Larry Lerner. Freebie: wind-up flashlight
Magma FineSim Pro and FineSim SPICE are also 2 new players, but
I'm not sure their specialty. (booth 4578) Ask for KT Moore.
24.) And for funky one-of-a-kind tools, go see the ChipEstimate.com
thingy. It's not really a tool, but a web site where it helps
you (you guessed it) generate a chip plan; predict die size,
power, performance and cost of packaged die. It's used in the
architectural phase through implementation, usually runs in
seconds and supposedly "correlates to within 95% of silicon."
(booth 2464) Ask Adam Traidman. freebie: 256 MB USB drives
25.) For design data management, IC Manage is showing its new GDP tool
which does automatic change propagation throughout your design's
database. (booth 6977) Ask for Shiv Sikand. Freebie: candy
One new tool in this space is TeamEDA LAM -- it keeps track of EDA
SW licenses, keys, vendors, license servers, daemons, contacts,
license agreements, PO's, costs, etc. It has a FlexLM reader to
pull out quantity, feature, expiration, and version number data
which the Macrovision people like to keep secret. It also does
email alerts. (booth 2787) Ask for Guy Haas. Freebie: pens
Aldec SFM is the another new tool in this niche that does server
farm management. Renesas uses it to track 100,000 test vectors
on 2,000 SW licences. (booth 5860) Ask for Igor Tsapenko.
ClioSoft (booth 2771) does data management & licensing tools, too.
26.) Denali -- yea, they have a monopoly on memory models. Who cares?
I wanna ticket to their San Diego DAC party! God help us -- this
year they've added an EDA Idols Amateur Talent Contest to the
party. Check out http://www.denali.com/dac_idol_contestant.html
(booth 6060) You must pester Kevin Silver to get a ticket.
27.) And if you happen to bump into Mike Fister, the CEO of Cadence, at
this DAC, make it a point to say "Hello, my name is [Your Name].
How are you?" -- this will make Fister very happy because in the
4 seconds it took you to say that, he earned $2.14! Yahoo CDNS
reports that Mike makes $4 million a year in pay. Using the
accounting standard of 40 hours work per week, that means that
Mike Fister earns $1,923.07 per hour or $32.05 per minute or
53.4 cents per second. It's like every 3 minutes some customer
taps Mike on the shoulder and gives him a hundred dollar bill.
Now, before you read this as Cooley's Fister-bashing, think again.
In the 5 years Ray Bingham was the CEO of Cadence, CDN market cap
went from $3.09B to $3.63B. A gain of 17.5%. In Mike Fister's
3 years, CDNS market cap went to $6.01B -- up a whopping 65.7%!
I may love to harrass Fister for his wingtip Ferragamo shoes, his
Armani suits and his incomprehensible Alan Greenspan-speak, but I
can't fault him for the positive influence he has on Wall Street
and CDNS shares. Because, like it or not, as Cadence goes up,
overall EDA goes up. As Cadence goes down, overall EDA goes down.
(booth 2753) Ask for Mike Fister. Freebie: $100 every 3 minutes
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there and that's me! :)
- John Cooley
ESNUG/DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
or (508) 429-4357.
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