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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2019"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
My unofficial guide to the Las Vegas DAC'19 exhibit floor. Enjoy!
RISC-V VS. ARM
1.) It's weird to see what was primarily an academic's/hobbyist's "fun
little open CPU project" in such a short time possibly become a very
serious threat to the ARM IP empire -- but that's what RISC-V has
quickly morphed into. Yes, right now it's nipping at unimportant
(actually trivial) chips that use tiny ARM Cortex-M0 sized CPUs, but
it doesn't take a crystal ball to see that RISC-V very soon wants to
play in ARM A53 and A72 country.
At DAC'19, my #1 Cheesy Must See thing is anything RISC-V. Namely:
SiFive is the current king of the RISC-V IP core world. Go to their
booth and start asking them a ton of practical design questions about
their RISC-V cores. How are they made? Are they testable? What do
you have in actual real silicon on NOW? You get smaller than ARM
cores by trimming out what's not used -- how do you verify such a
heavily pruned architecture? Can you do scan insertion? What about
PnR? Can I choose a specific footprint? What about on-chip security?
(You get the idea.) Be brutal. Why? DAC is a shopping trip and it's
where you can get these questioned answered quickly WITHOUT the SiFive
sales army coming in to your workplace to woo your management.
(booth 1037) Ask for Naveed Sherwani. Freebie: answers
Imperas RISC-V Developer Suite does timing driven RISC-V custom
instruction design and optimization, plus OVPsim is now updated to
latest ratified RISC-V specifications. Compliance, ISS verification.
(booth 1030) Ask for Larry Lapides. Freebie: pens
OneSpin RISC-V Verification App exhaustively verifies that RISC-V
cores have zero bug escapes and guarantees full ISA compliance.
(booth 308) Ask for Raik Brinkmann. Freebie: beer mugs
Will RISC-V stay at the Raspberry Pi hobbyist level? Or will it be
the open source CPU IP that eventually kills/cripples ARM?
P.S. And whoever at ARM who decided to *not* show at DAC'19 deserves
special recognition for giving SiFive and RISC-V a big public platform
to reach thousands of serious chip designers unopposed! (D'oh!)
IR-DROP / NOISE / THERMAL / POWER
2.) NEW! -- Cadence Tempus-PI (Project Virtus) -- last year was Anirudh's
combined attack on both John Lee's Redhawk IR-drop along with Aart's
Primetime STA empires. Since high local resistance at 7nm changes
how wire delay calcs need to be done, Project Virtus was Anirudh's R&D
welding together his Voltus (IR-drop) with his Tempus (STA) into one
new timing tool. (See ESNUG 584 #3) Unlike RedHawk, Virtus does
switching instead of vectorless IR-drop. "has Machine Learning, too!"
Claims found timing fatals on 3 user chips Redhawk plus PT had missed.
(booth 915) Ask for Marc Swinnen. Freebie: Denali party tix
NEW! -- Cadence Clarity is Anirudh's assault against the Ansys HFSS
full wave solver empire. With cloud, massive parallelization, plus
a "breakthrough new way to solve the matrix", Clarity is getting 10X
faster speed using 12x to 32x less memory! (ESNUG 586 #5) Which puts
Ajei Gopal in a defensive war. Users Teradyne, HiSilicon, Socionext.
(booth 915) Ask for Ben Gu. Freebie: Denali party tix
WTF??? -- this year there's NO Primetime SIG at the Las Vegas DAC???
(booth 367) Ask for James Chuang. Freebie: pens
Ansys Gear SeaScape ("Gear") is machine learning guidance RedHawk for
best QoR. Claims reduce die size by 5%. Problem is SeaScape/RedHawk
got inconsistant results. (ESNUG 563 #10 and 583 #5) Fixed now?
RedHawk-SC is built on SeaScape ("Gear") to give it elastic compute
and last claims "IR-drop in 6 hours on a 1 billion gate chip on a
16G machine" and "does 1000 scenarios overnight". 16/14/10/7/5nm.
Recent weird PR had Mellanox use it at 7nm but with unknown capacity.
(booth 935) Ask for John "Jolly" Lee. Freebie: stuffed animal
Ansys Apache RedHawk is full-chip/3d-IC power integrity analysis and
sign-off, transients, simultaneous switching noise package/PCB with
distributed processing. It is NOT built on SeaScape ("Gear"); it's
the original Apache RedHawk with the huge loyal customer base. But
it's struggling. Last reported scalable to 32 machines (256 cores).
"500M insts with 8B resistors plus keeping flat simulation accuracy".
Vector-based and vectorless. Clock jitter. TSMC 16/10nm FinFET.
Rivals claim RedHawk is sold under a RedHawk-SC wrapper as PR game?
RedHawk Analysis Fusion is a super tight integration of RedHawk-SC
within Primetime-SI to work inside Aart's IC Compiler II plus his
new Fusion Compiler -- plus have the Gear SeaScape Big Data stuff
there, too. That's 2 EDA vendors having 4 different db's under one
hood. Taxicab mode. Heard so far only SNPS employees can run FC.
(booth 935) Ask for John "Jolly" Lee. Freebie: stuffed animal
Cadence Voltus does full-chip signoff, IR-drop, Power-Grid-Views.
Massively parallel XP "scales up to 1,024 CPUs" 1 B insts over 100s
of compute CPUs. Have done 18 billion node circuits. Does ECO's.
Works with Tempus and Sigrity chip/package/board and Innovus PnR.
Heard rumors Facebook/Google/Amazon use it for AI chips. Voltus is
TSMC 5nm certified, but RedHawk-SC is always "will be in 3 months."
"Has multiple 5nm tapeouts. All good silicon. Customers happy."
Now in TSMC 5nm ref flow. HiSilicon, Juniper, TI, ARM, Nvidia, NXP,
TSMC, GF, Samsung, STM, ON Semi, Spreadtrum, Mellanox, Renesas, ADI.
Voltus-Fi does transistor-level noise/power signoff with Quantus QRC
and MMSIM inside Virtuoso. Both Voltus & Voltus-Fi are TSMC 10/7nm.
Apache Totem and Synopsys HSim-PWRA both compete against Voltus-Fi.
(booth 915) Ask for Jerry Zhao. Freebie: Denali party tickets
Magwel CDMi also does CDM ESD analysis like Apache Pathfinder ESD.
Checks all possible shunt paths during event; fewer false positives.
It can now handle chips as big as 10x10 mm^2 on up to 1000 pins.
Magwel PTM-TR uses a 3D field solver to do fast-but-accurate transient
Spectre simulation of power transistor circuits. Used for switching
power loss, check current crowding, device reliability.
(booth 844) Ask for Dundar Dumlugol. Freebie: none
Silicon Frontline ESRA-Decimm is the only ESD tool that simulates ESD
events with both FEM and spice models. Maxim, Analog Devices, SiLabs
Silicon Frontline P2P-XL does IR-drop with multiple FSDB files for
activity concurrently and perform pre-LVS clean analysis. No need
for vector creation. Do IR-drop at any stage during design.
(booth 312) Ask for Yuri Feinberg. Freebie: none
NEW SCHOOL RTL SIMULATORS
3.) Metrics Montana VPU's are custom tuned System Verilog IEEE 1800-2012
processors. "One of my Montana VPUs can take 100 M gates and run
5X to 20X faster than Cadence Rocketick or Synopsys Cheetah VCS. At
a capacity of 4 Billion gates, it goes even faster", says Joe. It's
NOT FPGA so no HAPS/Zebu/Protium super long compile time issue.
(booth 1219) Ask for Joe Costello. Freebie: playing cards
Cadence Xcelium (Rocketick RocketSim) is parallelized System Verilog
across 100's of Intel CPUs. Benched 23X faster vs. VCS, Incisive,
Questa. Does gate and RTL sims. Compiles 1 B gates in 2 hours.
Got #3 User's Best of in 2016. (DAC'16 #3) "It's in AWS and
Azure clouds now!" Xcelium comes in 1K cloud packs at a discount.
SystemC, e/Specman, VHDL, low power. Customers Intel & Nvidia.
ARM sees 5X speed-up for RTL/gate; STmicro at 8X for DFT simulation.
(booth 915) Ask for Uri Tal. Freebie: Denali party tix
Synopsys VCS FGP used to be called Cheetah. It's Aart's home grown
answer to Lip-Bu's 2016 Rocketick acquistion, also based on X86 CPUs.
Fine-grained parallelism. RTL 8X speed-up on 20 cores. Gates 12X
speed up on 20 cores. X-prop. Low power. Verdi integration.
(booth 367) Ask for Michael Sanie. Freebie: pens
COMPLETE CDC SIGN-OFF
4.) Normally I would put all the CDC tools under "bug hunters", but the
101-unrelated-clocks-in-my-chip signoff problem has become too messy.
MULTIMODE CDC "covers all scenarios in a single run". Real Intent,
Synopsys Atrenta, and Mentor all have had RTL single mode CDC for
years. Now they all claim RTL multimode CDC. To meet deadlines,
projects with a lot of modes typically only run a few select modes.
Meaning they can miss failures by skipping other modes.
GATE-LEVEL CDC matters because RTL logic synthesis and power opto
netlist changes can introduce new CDC errors in some designs.
(i.e. new registers or clock gating cells.) Even timing opto can
change the logic organization. All adding glitchy situations you
got to be on the lookout for.
Real Intent Meridian CDC for low noise RTL CDC. Samsung used it's
hierarchical flow and cut # of CDC violations to review by 95-98%
and engineering time by 70%. Claims runtime cut by 8X, and memory
cut by 4X for 800M gate chip with 103 clock domains. New data
model cuts memory by 25%, noise by 5-10X. Dynamic CDC protocols.
Real Intent Verix CDC is the only one that runs all clock modes at
the same time i.e. "true multimode". Mentor and Synopsys do a
worst-case setup for multi-mode using single-mode analysis, which
makes noisy reports that need a lot of waivers to deal with. Both
SpyGlass CDC and Questa CDC cope by running multiple modes serially.
Did CDC of 3.6 B gate design in 50 hrs. Compared to Spyglass or
Questa, saves 3.3x CPU time and 5x engineering time per iteration.
Real Intent Verix PCDC does gate-level netlist CDC sign-off with
glitch checking. Eliminates gate level CDC failures from synthesis
or power reduction after RTL CDC sign off. Usess SDC constraints
and RTL CDC results for fast incremental sign-off of all pathways.
1B+ gate designs have fast throughput using parallel processing.
(Booth 816) Ask for Prakash Narain. Freebie: LED Pen.
Mentor Questa CDC post-implementation, gate-level CDC analysis and
glitch detection for signoff. Low noise results due to focus on
implementation-based causes. High QoR, high scalability. ISO 26262.
Has gate-level stuff for FPGAs. Mediatek, Marvell, Cypress, AMD.
(Booth 334). Ask for Chris Giles. Freebie: plinko
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 623) Ask for Stanley Hyduke. Freebie: pens
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. 500 M inst with 1000 clocks in
8 hours. GUI user does full tracing. Handles flop duplication,
retiming and merging. Qualcomm, Nvidia, Broadcom, Mediatek, ARM
(booth 333) Ask for Sam Appleton. Freebie: frisbee
Cadence JasperGold has 14 formal Apps. One of them does CDC.
(booth 915) Ask for Pete Hardee. Freebie: Denali party tickets
Mentor Questa Formal has 11 formal Apps. One of them does CDC.
(booth 334) Ask for Joe Hupcey. Freebie: plinko
SPICE / AMS / CHARACTERIZATION
5.) If you look at prior Cheesy Lists, for close to a decade I would tell
readers to "Go see BDA AFS *first* if you're looking at SPICEs". Why?
Because AFS had a long detailed history of benchmarking faster than
Cadence Spectre. (ESNUG 494 #9, 495 #4, 538 #9 and even from 2 weeks
ago DAC'18 #6) But in a story I scooped 4 days ago in ESNUG 587 #3,
Cadence has just now launched a totally new rewrite of their SPICE
called "Spectre-X" which they claim is 10X faster vs. old Spectre!
So this year I must break my tradition and instead say...
SCOOP! -- Cadence Spectre-X claims to be 10x faster than old Spectre
thus, if true, totally disrupting the entire SPICE ecosystem. For
any analog guy his is easily the primary Must See for DAC'19. It does
massive distrubuted computing plus lots of cloud -- plus Aniridh is
claiming he's found a totally unique new way to solve the matrix that
is why Spectre-X (and his new Clarity tool, too) is 10X faster.
(booth 915) Ask for Tom Beckley. Freebie: Denali party tickets
Mentor BDA AFS claims is 2x faster than parallel SPICE simulators.
20+ M elements. TSMC 5nm certified. 2X faster. Now with Solido,
has 10x faster throughput for OCV vs. other SPICEs. BDA ACE for
analog characterization runs. AFS Mega does SPICE of 100+ M element
mega arrays like memories. Samsung, MediaTek, Intel, Broadcom,
Qualcomm, NXP, SiLabs, Fujitsu, ADI, Sony, LG, Magnachip, Skyworks.
(booth 334) Ask for Giuseppe Oliva. Freebie: plinko for prizes.
Silvaco SmartSpice Pro is Dave Dutton's push into the memory
fastSPICE market. Claims "true SPICE behavior but with much faster
generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
designs with better waveform overlay results than other simulators."
Does 28/16/14/10/7nm. SmartSpice (golden), SmartSpice HPP (parallel).
Samsung and LG are users. SmartSpice PRO for SRAM simulation.
(booth 953) Ask for Colin Shaw. Freebie: mouse
Empyrean ALPS before claimed "on average 2-5X speedup vs. 3 other
true SPICE simulators" which I guess are MENT BDA AFS, Spectre APS,
HSPICE. 3 million transistors and 30 million RCs. (ESNUG 572 #6)
Recent benchmarks confirm ALPS is at 2x to 5x faster. (DAC'18 #6)
ALPS' rep is full SPICE high capacity. Claims 10 million devices
NEW! -- Empyrean ALPS GT is industry's first GPU powered SPICE.
HiSilicon, Kilopass, Monolithic Power Systems, Ricoh, Toshiba
(booth 651) Ask for Jason Xing. Freebie: fluffy animal
ProPlus NanoSpice Giga big ass high capacity fast SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. Does 1+ B elements for 16/14/10/7nm FinFET or 28nm
FD-SOI. 10X faster vs. parallel SPICE. Samsung, Micron, eSilicon
(booth 354) Ask for Lianfeng Yang. Freebie: USB light
Mentor Solido ML Characterization Generator uses machine learning to
cut characterization time by 30-70% by generating Liberty models at
new conditions from prior Liberty data at different PVT conditions,
Vt families, supplies, channel lengths, model revs. NLDM, CCS, CCSN,
waveforms, ECSM, AOCV, LVF. Now has new GUI for customization.
Mentor Solido PVTMC Verifier uses machine learning to simulate across
full combinatorial of process variation and operating conditions
together, at 100X speed, for interactions statistical variation & PVTs
interactions, ensuring full variation-aware design coverage.
(booth 334) Ask for Amit Gupta. Freebie: plinko prizes
Cadence Liberate Trio now does cloud library characterization. Rivals
are Siliconsmart (SNPS), Kronos, and Predictor (Mentor). Maxlinear,
ARM, GF, Huawei, Dialog, Surecore, LG, Microchip all use Liberate.
(booth 915) Ask for Seena Shankar. Freebie: Denali party tickets
LibTech TurboChar competes against SiliconSmart and Liberate to
do std cell, IO, and SRAM characterization and modeling. Has
"massive parallelism", fast LVF/AOCV, improved auto-configuration.
Claims it improves linearly with more CPS, "does not level off like
queueing methods". (booth 916) Ask for Mehmet Cirit.
ProPlus ME-Pro lets you benchmark fab processes and devices.
Compare multiple foundries/multi-processes down to 7nm. No scripts
nor SPICE licenses needed to do 100's of comparisons! Qualcomm
(booth 354) Ask for Lianfeng Yang. Freebie: USB light
Silvaco Jivaro does netlist reduction for SPICE sim acceleration.
Multithreaded for DSPF/SPF netlists. Speeds up Spectre by 3X. More
accuracy. OA DM5 is supported. Silvaco Viso does quick analysis
of interconnect parasitics. Tight with Virtuoso. Silvaco Belledonne
does extracted netlist comparison -- for PDK optimization.
(booth 953) Ask for Jean-Pierre Goujon. Freebie: mouse
Mentor Solido Variation Designer does variation-aware design for PVT
corners, 3 to 9-sigma Monte Carlo, hierarchical and sensitivity
analysis. Big thing is it cuts waaaaaaaay down on how many SPICE
runs you need. Good for memory, standard cell, analog/RF, custom
digital. TSMC, Broadcom, Nvidia, Huawei, Cypress, ARM, IBM users.
(booth 334) Ask for Amit Gupta. Freebie: plinko prizes
Silvaco VarMan does Monte Carlo 3 to 8 sigma. Supports non-Gaussian.
Batch mode characteration of 100's of cells for you. 28nm FDSOI,
40 cells, 100 corners, Monte Carlo at each corner, 100's of measures,
took 173 mins using brute force MC and only 19 mins on VarMan. It
increases linearly to 6 sigma while claims Solido explodes hundreds
of times more to 6 sigma. ST Micro, Faraday, and Dolphin Integration.
(booth 953) Ask for Johnny Pham. Freebie: mouse
MunEDA WiCkeD analyzes SRAM cell/column/array, std cell, and analog
circuits for local variation to 9-sigma. Hierarchical and WCA.
FinFET, Bulk, Bipolar, BiCMOS. ST Micro and MunEDA published
silicon & bit cell analysis of 14nm FDSOI statistical BTI effects.
Samsung, SK Hynix, Infineon, Sanyo, Toshiba, and Altera users.
(booth 852) Ask for Andreas Ripp. Freebie: pens
ProPlus NanoYield is variation analysis on yield vs. PPA trade-off.
It does High Sigma Monte Carlo. Licensed from IBM nine years ago.
Can handle 10,000+ variables and does up to 7-sigma. Used by SMIC.
(booth 354) Ask for Lianfeng Yang. Freebie: cell phone clip
Empyrean XTime uses Big Data analysis to do "much faster accurate
Monte Carlo silicon timing sign-off." Does critical path, low
power and sensitivity analysis. Used for design margin recovery.
(booth 651) Ask for Jason Xing. Freebie: cellphone kickstand
PORTABLE STIMULUS
6.) Portable Stimulus (PSS) promises UVM reuse from HW all the way to SW.
UVM Simulation ==> HW/SW Emulation ==> final post-Silicon
For a good detailed tech primer on PSS, see ESNUG 578 #1, #2, #3.
Breker TrekSoC has slipped way behind CDNS Perspec in "Best of 2018"
(See DAC'18 #2b) But I still recommend seeing them at DAC'19
because you can easily see Perspec at all the CDNlive events.
Last year Breker added DSL input, and better synthesis to UVM.
Breker's strength is it's output is easy to make into testbenches.
Users Huawei, Broadcom, IBM, Nvidia, Altera/Intel, ADI, SiFive
(booth 611) Ask for Adnan Hamid. Freebie: chord kit
Cadence Perspec is on the not-C++ but DSL side. It's a multi-core
ARM verification library/tool for cache coherency, distributed virtual
memory, low power. "We're swimming in ARM cores, John!!! Swimming!"
Perspec voted #2 overall by users as "Best of 2018". (See DAC'18 #2a)
Qualcomm, Samsung, Mediatek, Renesas, ST, TI, Infineon are users.
(booth 915) Ask for Sharon Rosenberg. Freebie: Denali party tickets
Mentor Questa InFact "achieves System Verilog coverage 25X faster
than old school constrained random test." Imports SV constraints and
generates SV IP level tests & system level C/C++ tests. Dropped
proprietary input to be 100% PSS 1.0. Pre-PSS, InFact users like its
coverage space pruner getting 30X sim speed-up. (ESNUG 581 #3.)
Users are Qualcomm, Applied Micro, Ciena, Microsoft, Microsemi.
(booth 334) Ask for Mark Olen. Freebie: plinko
Synopsys still isn't showing a PSS tool. Rumor is they're still
looking at acquiring Breker to fill that hole.
DIGITAL P&R
7.) Avatar Aprisa 19.1 is spliting its flows. For 7nm and below chips,
they added a very clever (and patented) "Sibling Routing" where slow
high resistive wires are double routed with two different paths to
make for a lower resistance faster signal. TSMC 7FF certified.
Samsung, Broadcom, Xilinx, Inphi, Mellanox, Cypress, and eSilicon
For IoT designs, Aprisa PowerFirst does PnR where standby and active
power are the #1 PnR constraints, then timing, then area. Rumor is
SiFive and Avatar are working on cost-per-use portal for RISC-V cores.
I go see Avatar at DAC, because I see ICC2/Innovus at SNUG/CDNlive.
(booth 967) Ask for Chi-Ping Hsu. Freebie: stuffed lion
Cadence Innovus claims "over 100 7nm tapeouts!" and "best choice for
5nm!" For 7nm, users loved Innovus-Voltus uber tightness DAC'16 #7;
(Innovus + Voltus did ECOs with 93% less victims) which is a direct
threat to the Synopsys/Redhawk 7nm IR-drop patch in ESNUG 584 #3.
Genus/Modus/Innovus/Tempus full flow beat DC/ICC2/PT full flow and
Fusion Compiler/PT full flow in user benchmark in ESNUG 587 #1.
The other pain point for Aart is digital Innovus is uber tight with
full custom Virtuoso. Meaning lots of A/d, D/a chips Aart's missing.
So no surprise that Qualcomm, Nvidia, ST, Faraday, GF, HiSilicon,
Broadcom, Toshiba, Freescale, Juniper, Renesas, ARM, Maxlinear,
Spreadtrum, Silicon Labs, MediaTek, Cypress, ImgTec, Realtek, NXP
Intel, (and one very big and very quiet "other") all use Innovus.
New this year: AI/ML for trim design, bus planning, mixed-placer does
concurrent macros and std cells placement. "We're on AWS and Azure!"
(booth 915) Ask for Rod Metcalfe. Freebie: Denali party tickets
Oasys-RTL/Nitro-SoC combo for RTL to GDSII. Siemens invested into
Badru's team "to help companies in AI, autonomous vehicles, smart and
smart cities and infrastructure to implement ultralow power chips."
Ask Badru Agarwala how his flow combined with Catapult, Tessent, and
Calibre can get your QoR in weeks where others spend months.
(booth 334) Ask for Badru Agarwala. Freebie: Plinko for prizes.
Synopsys IC Compiler II 2019 claims to have beaten Cadence Innovus is
4 user benchmarks but won't give any details. "please don't hesitate
to reach out to your Synopsys sales representitive". 100 tapeouts.
If true, not bad after gutting its R&D two years ago in ESNUG 579 #2.
(booth 367) Ask for Shankar Krishnamoorthy. Freebie: promises
FPGA STUFF
8.) OneSpin 360 EC-FPGA does equivalency checking RTL vs. post-synthesis
netlists for FPGA's. Why? Because Brett Cline told me "holy, crap,
you won't believe how much Raik sells in FPGA equivalency tools!"
EC RTL vs. gates. now supports Stratix 10, Arria 10, and Cyclone V.
(booth 308) Ask for Raik Brinkmann. Freebie: party tickets
Blue Pearl VV Suite lets FPGA engineers visually verify by way of
graphical FSMs, CDC and false path viewers with cross probing to RTL,
with forward and reverse tracing, and linting message filtering.
Upgraded its simultaneous clock and reset domain analysis CDC stuff.
New this year reads and obfuscate encrypted IP to IEEE 1735. Lets
encrypted IP to be used during clock domain crossing analysis.
Microsoft, Lockheed, Bechtel, Raytheon, Thales, Navy Research Lab,
Harris, Ricoh, GE Medical, MBDA, BAE, Fujitsu, NEC, Bechtel, GE.
Blue Pearl HDL Creator is an editor with 2000 real-time checks to fix
issues as you code, such as compilation and missing dependencies.
(booth 345) Ask for Ellis Smith. Freebie: t shirt
Menta eFPGA Origami is a unique tool that lets ASIC/SoC designers
create their own TSMC 28HPC+ or GF 14LPP embedded custom FPGA IP blocks.
(booth 626) Ask for Yoan Dupret. Freebie: ment candy
Mentor Precision Hi-Rel does synthesis-based automated single event
effect mitigation methods such as triple modular redundancy (TMR),
fault-detect and fault-tolerant FSM encoding in FPGA's. ISO 26262,
DO-254, and IEC 61508. Rivals SNPS Synplify Premier. LEC flow for
datapath FPGA designs. Customers "have small black helicopters."
(booth 334) Ask for Badru Agarwala. Freebie: plinko
BUGHUNTERS
9.) Cadence JasperGold has 14 formal Apps. 2X capacity and 5X speed
in last 12 months. "Our new machine learning kicks ass!" Jasper
finds bugs 1000's of cycles deep. Tight with Xcelium and vManager.
Tons of users gushing about it (DAC'16 #1, DAC'17 #11, DAC'18 #7)
Samsung, HiSilicon, Nvidia, Qualcomm, TI, Broadcom, Marvell, ARM,
Analog Devices, HPE, NXP, RealTek, ST Microelectronics, Toshiba.
(booth 915) Ask for Pete Hardee. Freebie: Denali party tickets
OneSpin is very fruit salad this year. It does niches that Jasper
and Questa Formal doesn't do. 360 Verify does property checking
with coverage. 360 Quantify does a full formal coverage of your
code and SVAs. 360 Safety injects faults into device code to see
if it recovers from an operational fault in the field, and still
works. SystemC App Connectivity XL App sees if your 1 billion
gate chip is interconnected properly. Their Trust tool sees if any
HW security holes. PortableCoverage App measures coverage. FPU App
does formal on IEEE 754 floating point. 26262 FMEDA tool does safety
metrics (SPFM, LFM, PMHF). And their RISC-V Verification App does
zero bug escapes and guarantees full compliance with the ISA. Nokia,
Renesas, Infineon, Xilinx, Microsemi, Western Digital, Bosch, Maxsim.
(booth 308) Ask for Raik Brinkmann. Freebie: beer mug, pretzels
Mentor Questa Formal has 10 formal Apps. X-checking, RTL checks,
coverage, assertion checks, property generation, connectivity checks,
post-Silicon, register checks, CDC, unreachability -- plus SLEC for
safety-critical designs. "ISO 26262, baby!" Marvell, JPL,
Samsung, Cypress, Microsoft, Microsemi, Mediatek, AMD, and Rambus.
(booth 2621) Ask for Joe Hupcey. Freebie: plinko prizes
Real Intent Ascent Lint RTL & netlist rule checking & sign off. new
certified by TUV SUD for ISO-26262 (TCL2). Has high impact rules for
syntax, semantic, & style checks for low noise & ease of debug.
Integrated debugger. Rule configuration editor has severity config
& annotations, categories, filters and searches.
Real Intent Ascent AutoFormal identifies RTL design bugs early. 10X
speedup & 3 million gate capacity. It extracts RTL "implied intent"
checks, runs formal analysis, & determines root cause errors.
Detects FSM deadlocks, dead code & range violations, etc.
(booth 816) Ask for Lisa Piper. Freebie: LED pen
Amiq Verissimo is like a Spyglass linter but just for System Verilog
testbench code. "50+ new checks in assertions, dead code, language
pitfalls, code maintainability, and UVM methodology guidelines."
Samsung, Cisco, Qualcomm, Xilinx, Toshiba, Broadcom, Nvidea, NXP.
(booth 854) Ask for Cristian Amitroaie. Freebie: chocolates
Synopsys Atrenta Spyglass plays heavily in killer linters, but I
don't know if they got space in the Synopsys booth this year.
Excellicon ConMan formally crafts hierarchical constraints for
multi/merged mode SDC, promotion, clocking analysis. Rivals Ausdia
and Fishtail. 500+ M inst. Concert EQ is equivalence checking for
Top2Block, Top2Top (1D2S, 2D2S, 2D1S, SDC2ETM checking). Does ECO
changes, cloning, decloning, logical restructuring etc.
Excellicon ConTree does pre-CTS analysis of clocking structure for
proper clock skew groups, automatic creation of anchor buffers and
creation of CTS file. In post-CTS phase, verifies CTS for lowered
clock latency and skew.
Excellicon ConCert verifies timing intent & structural exceptions
using SVA+/formal. SDC, CTS, demotion, equiv checking. They added
timing budgeting and exceptions toolboxes to ConCert this year.
LG, Samsung, Marvell, Renesas, Qualcomm, Western Digital, Maxim, ST.
(booth 552) Ask for Himanshu Bhatnagar. Freebie: dice cups
Real Intent Meridian RDC finds messy reset metastability & glitch
problems. Categorizes violations, has minimum noise. Claims in
benchmark vs. rival it had MUCH few violations (200 vs 500,000),
and was 8X faster (45 min vs 6 hours). Parallel & hierarchical.
Rivals SpyGlass RDC, Questa RDC. 200M gate full RDC in 9 hrs.
(booth 816) Ask for Oren Katzir. Freebie: LED pens
FishTail Confirm verifies if your asynchronous resets are glitch
safe using formal and AVB. Requires just SDC & RTL. SDC EC verifies
if constraints are correctly moved up/down design hierarchy. Runs
40M gate design in 7 hrs. FishTail Focus SDC constraints cut PnR
runtimes by 3x. Mediatek, Invecas, Qualcomm, Xilinx, Infinera,
(booth 511) Ask for Ajay Daga. Freebie: an iPhone X's
Ausdia Timevision SOC Budgeter handles the SDC time budgetting
across hierarchical boundaries. Uses SDFs, timing reports and physical
data (LEF/DEF) to produce and manage accurate timing budgets for the
blocks used in hierarchical implementation flows.
Timevision SdcCheck does 200 checks. "your SDC + checking it's intent."
MMMC constraints, Verilog/SystemVerilog/VHDL, IEEE P.1735 encrypted RTL.
Precise file/line backtracking pinpoint in your source RTL/SDC issues.
(booth 333) Ask for Sam Appleton. Freebie: frisbee
Arcadia Innovation TimeHawk Constraints finds SDC patches that used
to be found during placement and CTS iterations. Claims saves 3 to
4 weeks of design iterations. Also does full chip SDC debug. Added
"advanced" EC. CTS finds SDC patches w/o placement & CTS iterations.
Claims 200 million inst designs are "run in 2 hours."
(booth 361) Ask for Joey Lin. Freebie: pens
Real Intent Verix SimFix detects & corrects X-pessimism in gate-level
sims, enabling gate-level functional sign-off. Did 100M to 350M nets.
Real Intent Meridian RXV does X-impact analysis on RTL to avoid
messes with reset schemes, diverse IPs. Shows X-optimism causing
design errors. NO simulation vectors, nor coverage analysis nor
simulation. Rivals are VCS Xprop, JasperGold.
(booth 816) Ask for Sanjay Thatte. Freebie: LED pens
Avery SimXACT automatically find X bugs in RTL and eliminates false
X's in gate-level simulation. Has gated clock X pessimism analysis
and auto generated fix deposits. Verdi, SimVision, Questa SIM Wave.
"Gate simulation bring-up productivity is more than fixing false Xs!"
Broadcom, Qualcomm, Nvidia, Western Digital, HPE, Cavium, MediaTek.
(booth 808) Ask for Chris Browy. Freebie: caramels
Cadence Conformal LEC does both gates-gates and RTL-gate logical
equivalence checking. The #1 selling LEC in Synopsys design flows
because it's wise to have a checker from outside your flow. Now has
does adaptive proofs, 4X average TAT with 4 CPUs, 20X with more CPUs.
Intel, Xilinx, Broadcom, LG, Qualcomm, ARM, Samsung, NXP, HiSilicon
(booth 915) Ask for Avinash Palepu. Freebie: Denali party tickets
Mentor Visualizer Debug is Sawicki's debug answer to Cadence SimVision
Debug Analyzer and Synopsys DVE/Verdi. Visualizer debugs RTL, gates
and testbenches, automatic tracing to "pinpoint cause of errors".
(booth 334) Ask for Mark Olen. Freebie: plinko prizes
Cadence Indago is Lip-Bu's answer to Aart's Verdi3 empire. Indago
debug works by adding Big Data Capture to Root Cause Analysis -- in
order to data mine your CDNS tool run logs -- to "highlight causality"
and correlations causing your bug in the first place. Does HW/SW bug
hunting. Analog Devices, TI, Bosch, Broadcom, Renesas, Siemens, ST.
(booth 915) Ask Larry Melling. Freebie: Denali tix
Mentor Austemper KaleidoScope does mixed-signal fault injection as
functional safety tool. ISO26262 automotive stuff from OneSpin.
(booth 334) Ask for Bryan Ramirez. Freebie: plinko prizes
CALIBRE, STAR-RC, & RIVALS
10.) Mentor Calibre nmDRC the undisputed DRC king shows kickass scaling
extends to the public cloud. At DAC, Sawicki invited Anirudh to the
lunch where AMD used 4,140 Microsoft Azure CPUs for full chip DRC/LVS
of 12 billion 7nm transistors in just 10 hours! (ESNUG 587 #2)
Mentor Calibre LVS is king of layout vs. schematic physical tools.
Tightly linked with both Calibre nmDRC and Calibre xRC.
(booth 334) Ask for John Ferguson. Freebie: plinko prizes
NEW! -- Mentor Calibre Recon does early (i.e. "dirty") chip design
physical verification out of Innovus/ICC2/Avatar PnR for both
interactive and batch Calibre use models within Calibre RealTime
Digital/Calibre nmDRC. TSMC, Samsung, GlobalFoundries, ST.
(booth 334) Ask for John Ferguson. Freebie: plinko prizes
Calibre Pattern Matching replaces text-based design rules with visual
geometry capture and compare. SRAM checking for TSMC 7/5nm are based
on it. Removes design patterns that are "yield detractors." Aimed
at 10/7/5nm designs. Also core to Samsung's Closed Loop DFM for
faster yield ramps. TSMC, Samsung, GlobalFoundries, SMIC, UMC.
(booth 334) Ask for Michael White. Freebie: plinko prizes
Cadence Pegasus DRC "massively parallel DRC engine" runs "100's CPUs".
Claims 8X/12X faster than old Calibre. For Innovus PnR, Pegasus does
signoff DRC, incremental DRCs, signoff metal fill, incremental metal
fill, timing-aware metal fill, and MPT decomposition for FinFETs. Over
the years Sawicki had fun torturing Anirudh about there being no TSMC
certified runsets (ESNUG 576 #1, 585 #1); but that changed April 2019
when TSMC put out certified Pegasus runsets for both 7nm and 5nm. Will
Sawicki now be losing sleep on this? Texas Instruments and Microsemi.
(booth 915) Ask for Manoj Chacko. Freebie: Denali party tix
Cadence Quantus QRC competes with Star-RCXT and Calibre-xACT. Does
multi-corner/statistical/inductance RLCK extraction, 16/14/10/7/5nm
Modeling, distributed processing, netlist reduction, SNA. Double
patterning, 3D-IC. 41 FinFET customers and 3 FD-SOI. Reliability.
Constraint validation. Works "in-design" in Innovus and Virtuoso.
Last year Quantus was in Amazon AWS and Microsoft Azure clouds.
(booth 915) Ask for Hitendra Divecha. Freebie: Denali party tix
Mentor Calibre-xACT does massively parallel full chip RLC parasitic
extraction without tiling. Processes entire net on a dedicated CPU.
No boundary and halo effects. "Attofarad accuracy with multi-million
instance digital or custom designs." Hybrid MOL/BEOL solver good to
7nm. Multi-patterning. Decks from TSMC, Samsung, GF available.
(booth 334) Ask for Carey Robertson. Freebie: plinko prizes
Ansys Helic Exalto does 3D electro-magnetic (EM) crosstalk analysis
and signoff. Has killer capacity/speed/accuracy. 12 Ghz chip with EM
coupling through PWR/GND. 2.8mm X 700u, with AP, M12-M7. Extracted
in 36 hours on 20 cores. Exalto is the only EM sign-off tool that
can handle designs with 2,000 ports doing full RLCK extraction in
40 hrs with 16 CPUs and 150GB of RAM. With 32 CPUs, under 1 day.
Exalto works with Star-RC, Quantus, Calibre-xACT. Huawei, Qualcomm.
Ansys Helic Pharos does EM risk-analysis. Analyzes EM isolation
between selected victim nets and all potential aggressors; does up to
100 billion pairs. Pharos does 2,000 ports vs. HFSS 30 ports. Gives
EM isolation "heat maps" with GHz frequency sweeps. Nothing like it
before. With Star-RC, Quantus QRC, Calibre-xACT. See ESNUG 584 #4.
(booth 935) Ask Yorgos Koutsoyiannopoulos. Freebies: pens
Synopsys Star-RC competes in extraction; unknown if showing at DAC'19.
Lorentz PeakView does 3D EM extraction and modeling. Has vertical
inductance, multi-sheet extraction, and chip-package EM co-simulation.
Competes with Ansys HFSS. Users are Qualcomm, TI, TSMC, GF, Samsung.
(booth 528) Ask for Jinsong Zhao. Freebie: mugs
Silvaco (Infiniscale) TechModeler takes IV curves from silicon or 3D
parasitic extraction and uses a neural network to make very accurate
behavioral Verilog-A models from a small sample size that can be
simulated in SPICE. It competes with Keysight's NeuroFET.
(booth 953) Ask for Bogdan Tudor. Freebie: mouse
Silvaco Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
Now 2x faster and can compare 5 different netlists at the same time.
(booth 953) Ask for Jean-Pierre Goujon. Freebie: mouse
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. 22nm - 3nm.
(booth 832) Ask for Coby Zelnik. Freebie: pens
Mentor Calibre YieldEnhancer fills both low nodes and complex analog
blocks. Has push button ECO Fill solution. Synopsys IC Validator
and Cadence Pegasus and PVS are competitors. TSMC, Samsung, GF.
(booth 334) Ask for Jeff Wilson. Freebie: plinko prizes
Mentor Calibre PERC does circuit reliability verification, and is in
cell, block, and full-chip 3rd party sign-off flows to check for
common electrical failures such as Electrostatic Discharge (ESD),
Latch-Up, and Electrical Overstress (EOS). Has extensions to
Calibre YieldEnhancer for net-aware and orientation-aware metal fill.
PERC end users are Xilinx, Broadcom, ST, ARM, Silicon labs. Foundries
that support PERC are TSMC, GlobalFoundries, Samsung, TowerJazz, UMC.
(booth 334) Ask for Carey Robertson. Freebie: plinko prizes
Silicon Frontline R3D-DDM automatically generates a distributed model
of power devices for transient analysis. Rivals Star-RC, Quantus QRC
(booth 312) Ask for Yuri Feinberg. Freebie: none
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process in 3-D. Virtual fabrication. To test
fab effects. It rivals Synopsys Sentaurus and Silvaco Victory.
Has "Big Data" analytics. GlobalFoundries, Micron, IBM, Imec
Coventor MP creates finite element & reduced order models for MEMS
to go into MatLab, Simulink, Virtuoso, or Verilog-A SPICE.
(booth 835) Ask for Timothy Yang. Freebie: laser pointer
EMULATION / ACCELERATION / PROTOTYPING
11.) Cadence Palladium Z1 has 3x faster Build-Allocate-Run-Debug loop,
2X faster downloads, parallel partitioning compiles 3X faster with
incremental synthesis (incremental and parallel up to 64 cores.)
Offline debug for 100s of SW developers. Scales to 9.2B ASIC gates
for 2,304 simultaneous users in data center, water or air cooled.
Cavium, Fujitsu, Huawei/HiSilicon, ARM, Innovium, Marvell, Mellanox,
MicroSemi, Intel, Nvidia, Renesas, Socionext, Xilinx, Realtek.
(booth 915) Ask Frank Schirrmeister. Freebie: Denali party tix
Mentor Veloce Strato claims whopping 15 billion gates capacity from
its Crystal3 chip. (ESNUG 567 #1, 567 #3) 64 users. 50 kW.
Last year's Sarokal buy adds emulation muscle in Automotive. It's
baby brother, StratoT, does 40 M to 1.25 B gates, 32 users, 17 kW.
NEW! -- Mentor Veloce Siemens PAVE360 for autonomous vehicle design!
Adds Mentor Veloce to Siemens Simcenter PreScan and Simcenter AMESIM.
Mentor Veloce 2 does 50+ MHz embedded SW execution with Warpcore and
Codelink. VirtuaLAB peripherals: 256-port Ethernet, PCIe Gen3, USB-3,
SATA, SAS, VJTAG. RTL-waveform debugger. Does ICE and Virtual.
Jean-Marie gloats Veloce 2 is 1st emulator on Cloud. (ESNUG 583 #4)
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon use Veloce 2.
(booth 334) Ask for Jean-Marie Brunet. Freebie: plinko prizes
Mentor Veloce Apps are tight with Ansys Apache PowerArtist. Its RTL
power reduction analysis is 4.5X faster. There 8 other Veloce Apps:
Coverage, Assertion, Deterministic ICE, ICE, Power, SW Debug, DFT,
and Ixia Virtual Network App. ST, Broadcom, Mitsubishi, HiSilicon.
(booth 334) Ask for Vijay Chobisa. Freebie: plinko prizes
Synopsys EVE ZeBu-4 has 2X faster than legacy Palladium and Veloce
boxes. It's based on same 20nm Xilinx Vertex UltraScale VU440 that
the old Cadence Protium-S1 uses. Zebu Server 4 claims 19 B gate
capacity. TLMs, power-aware, sim acceleration, ICE, synthesizable
testbench. Samsung and Intel. "Hey, we got ZeBu Cloud now, too!"
(booth 367) Ask for Manoj Gandhi. Freebie: pens
NEW! -- Cadence Protium-X1 is an FPGA-based prototyper that can do
38 billion gates, 1,536 users, sweet spot "5 MHz for a billion gate
designs -- nobody else can do this!" X1 is Lip-bu extending his
Protium S1 to go beyond SNPS HAPS. Auto ASIC-to-FPGA memory con-
version, auto clock synchronization to avoid hold-time violations
and FPGA-specific limits, pre-P&R model validation. "quick bring
up in 1-2 weeks vs. 3-4 months." SCE-MI transaction interface,
memory back-doors, start-stop-clock control, scripting for SW
developers. Protium-X1 takes in Palladium Z1 QTDB database to run
3X faster. Nvidia, Mellanox, Microsemi, Marvell, Medtronic, Xilinx.
(booth 915) Ask for Juergen Jaeger. Freebie: Denali party tix
Aldec HES-DVM is the poor man's HAPS. Uses UltraScale U440's. Claims
633 M gates. Auto partitioning, ASIC-to-FPGA clock conversion,
static/dynamic probes, memory viewer, HW breakpoints. Ethernet, USB,
USB-OTG, HDMI, I2C, SPI, RS232, GPIO, ARM Debug & JTAG. Users are
Qualcomm, Samsung, Fuji-Xerox. Now HES-DVM Cloud does does System
Verilog DPI-C TLM's, virtual SW, and ICE in the Amazon AWS cloud.
(booth 623) Ask for Stanley Hyduke. Freebie: pens
ProDesign proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Stratix 10. 600 M ASIC gates.
20 Gbps. In 5 years ProDesign shipped 1251 units to 121 customers.
(booth 635) Ask for Gunnar Scholl. Freebie: USB chargers
S2C Prodigy can debug across up to 8 FPGAs simultaneously and capture
up to 32K signals per FPGA of 4K probes each without FPGA re-compile.
(booth 952) Ask for Jimmy Chen. Freebie: candies
Synopsys HAPS-80 and ProtoCompiler claims 1.6 billion ASIC gates
at 100 Mhz speeds from 64 total Xilinx Virtex UltraScale VU440's.
(booth 367) Ask for Joachim Kunkel. Freebie: pens
Dini Group DNVUF4A -- ASIC prototype 4 Virtex UltraScale XCVU440's,
each with capacity of 116 million ASIC gates. Seamless stack 8 or
more of these boards to prototype 1 billion ASIC gates. 2,892 BGA.
16 GbE with no external Phy needed. GEN3 PCIe, SATA III, USB 3.0.
Dini Group DN_ReadBacker lets you read back the complete status
of your FPGA registers for debug. "No one else does this, John!!!"
(booth 539) Ask for Mike Dini. Freebie: grumpy Mike sayings
MARGINs & ECOs
12.) Easy-Logic ECO Surgery does a new rewiring based functional ECO's
that super crazy small. "Minimized patching!" and "new ECO
patches sized just 1/100 to 1/1000 of manual". These guys won the
ICCAD CAD Contest three years in a row (2012, 2013, 2014) on this.
(booth 1019) Ask for David Wu or Sean Wei. Freebie: candies
Dorado Tweaker is a family of physically-aware ECO tools:
Dorado Tweaker-T1 vs. PrimeTime-ECO vs. Cadence Tempus-ECO
Dorado Tweaker-F1 vs. Cadence Conformal ECO
Static/dynamic power ECO's. 50 M inst. 16/14/10/7nm FinFET. Now
hierachical/timing/CPU/IR-drop ECO flows. Intel/GF/Samsung/TSMC
Broadcom, Qualcomm, LG, TSMC, Mediatek, Samsung, Xilinx users.
(booth 520) Ask for JJ Hsiao. Freebie: ECO magnet
Empyrean XTop physical MCMM timing ECO tool. PBA timing fixes,
route-based timing fix. 16/14/10/7nm 100M inst. 5X faster.
ClockExplorer does CTS clock analysis and constraint generation.
It helps cuts clock insertion delay. Marvell, HiSilicon users.
(booth 651) Ask for Jason Xing. Freebie: fluffy animal
Cadence Conformal ECO Designer generates "congestion-aware ECO"
for "last-minute difficult ECO areas" for pre- and post-mask layout.
New fast setup, new 10X TAT and new scan chain preservation stuff.
Users Broadcom, Qualcomm, ST, Samsung, Toshiba, AMD, Mediatek
(booth 915) Ask Avinash Palepu. Freebie: Denali party tix
Synopsys PrimeTime ADV is all about distributed MCMM timing ECO's.
(booth 367) Ask for James Chuang. Freebie: pens
PRIMETIME & RIVALS
13.) Cadence Tempus does auto-partitioning of STA runs it calls DSTA.
"Does concurrent MMMC just like a regular Tempus STA run." Does
1 B inst production chips flat using <1 T byte machines. "ML!"
5x faster vs Primetime. ECO's, SI/crosstalk, too. 500+ tapeouts.
"We added Tempus-PI (Project Virtus) for 7nm IR-drop aware timing!"
Samsung, HiSilicon, ARM, TI, Inphi, NXP, Maxlinear, Cypress, LG,
TSMC, GlobalFoundries, Intel, Analog Devices, Marvell, Qualcomm.
(booth 915) Ask for Marc Swinnen. Freebie: Denali party tix
Synopsys PrimeTime also has machine learning, which it's calling
artificial intelligence. 5X faster overall and power ECOs are 4X
faster. Renesas on 40nm chips. PrimeTime-ADV does physically
-aware ECO's for timing, DRC, power recovery, POCV. PrimeTime-SI
claims killer crosstalk delay analysis with Ansys RedHawk/SeaScape
super tight integration. PT is the 25 year King of STA tools.
Very weirdly Aart cancelled his popular Primetime-SIG this year.
(booth 367) Ask for James Chuang. Freebie: pens
Arcadia TimeHawk STA last year claimed was first commercial timer to
bring artificial intelligence to timing signoff. Timing ECOs, MMMC,
SI/crosstalk at 2 M inst-per-minute, with 2 billion inst capacity.
New hierarchical/structural/quality analysis for physical synthesis.
(booth 361) Ask for Joey Lin. Freebie: pens
VIRTUOSO & RIVALS
14.) Virtuoso 18.1 is a 2nd revamp. At CDNlive'16 Tom Beckley launched
his first revamp that where ADE Explorer was the old ADE-L, but had
nominal/corners/sweeps/monte carlo/spec comparison are in one tool.
ADE Assembler had multiple tests/statistical (from GXL). Problem
was his ADE Verifier -- Beckley was trying to get circuit designers
to do planning and design against design goals in analog/custom
design -- something they do NOT trust! (See ESNUG 560 #1)
Now with this 2nd revamp launched at CDNlive'18, his Virtuoso 18.1
"has new automation technologies with simulation-driven layout" and
"now does 5nm". Beckley really is pushing this design-against-goals
approach to the circuit designers yet again this year. Bosch user.
Beckley is now throwing in Sigrity into Virtuoso 18.1 to woo the
chip/package/PCB design flow guys -- an "It Does Everything" sale.
(booth 915) Ask for Yuval Shay. Freebie: Denali party tix
Virtuoso + Innovus integration is a strong CDNS selling point against
Aart and Sawicki for those doing analog plus digital designs. Digital
on top / Analog on top approaches. "Both analog & digital in 5nm!"
(booth 915) Ask for Yuval Shay. Freebie: Denali party tix
Mentor Calibre RealTime Custom does instantaneous sign-off DRC checks
and fixes inside Virtuoso, Laker3, Custom Compiler. Same deck, same
results as batch Calibre. 2-5X productivity improvement when fixing
DRCs in 180-7nm nodes. Double/triple patterning, preferred metal
direction, density checks, pattern matching and voltage-aware DRC.
Has cells/blocks-to-macros DRCs to automatically launching batch
Calibre jobs. Rivals Cadence iPVS. Qualcomm, Broadcom, SiLabs.
(booth 334) Ask for Srinivas Velivala. Freebie: plinko prizes
NEW! -- Mentor Calibre RealTime Digital does instantaneous sign-off
DRC checking and fixing inside Innovus and ICC2. Same deck, same
engine and same results as batch Calibre. Like CDNS PVS (or Pegasus)
Interactive and SNPS ICV, but it's 40% to 85% faster. ESNUG 584 #1.
(booth 334) Ask for Srinivas Velivala. Freebie: plinko prizes
Synopsys Custom Compiler is Aart's 2nd attempt on Lip-Bu's Virtuoso
monopoly. The 1st try was Custom Designer (which flopped.) CC runs
the old Laker3 router plus the Ciranova Helix plus some "assistant
features" to generate many different layouts of one circuit.
(booth 367) Ask for Dave Reed. Freebie: pens
Silvaco Expert is a hierarchical IC layout editor. Schmatic driven.
10 Gig GDSII loads in "minutes". Uses Calibre Interactive for DRC
"on the fly". Rapid pan/zoom. Equal resistance router. OA and
interop PDKs (iPDK) makes design migration easier. And WTF???!!
Silicon Creations uses it for 7/5nm FinFET? Silvaco doing 7/5nm?!?
Also Silvaco Clever 3D RC field solver BEOL/MEOL parasitic extract.
(booth 953) Ask Dave Dutton. Freebie: mice
Pulsic Animate does automatic layout of analog (transistor level)
designs, with no constraints, no scripting, no programming required.
Multi-threaded. Makes 100's of fully PnR-ed layouts in minutes from
an OpenAccess schematic (vs. 2-3 weeks single layout in Virtuoso).
Did a 40% reduction in cell block implementation time for Ricoh.
(booth 936) Ask for Paul Clewes. Freebie: stuffed racoon
Mentor Tanner is OA-based S-Edit schematic capture, L-Edit custom
layout, and T-Spice SPICE. Founded 1988. "Cost effective" prices.
The old HiPer Verify DRC was replaced by Calibre DRC. Pyxis in it,
too. They target MEMS designers like Obsidian, Microgen, Innotime,
Lewyn Consulting, Velankani, Eesy IC, Microdul AG, PragmatIC
(booth 334) Ask for Jeff Miller. Freebie: plinko prizes
Silvaco NanGate Cello fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 16/14/10/7nm.
Also does coloring, self aligned MOL, template based cell creation.
(booth 953) Ask for Jens Michelsen. Freebie: mice
LibTech LibChar does std cell, IO, SRAM characterization & modeling.
Now does PLLs. (booth 916) Ask for Mehmet Cirit.
Movellus PLL/DLL/LDO Generator is kind of weird because it creates
*digital* versions of *analog* IP. In this case, it's PLL's, DLL's,
and LDO's. Why? Because then you can use *digital* synthesis, STA,
PnR on your PLL/DLL/LDO -- making them portable across nodes, and
you can do scan/ATPG/DFT on your PLL/DLL/LDO, too! (See ESNUG 582 #2)
So far at TSMC 16nm and Mo is working on 7nm. Intel Capital funded.
(booth 567) Ask for Mo Faisal. Freebie: chocolates
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Work with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Intel, Broadcom, Qualcomm, Infineon, Bosch, Marvell, Toshiba, TSMC.
(booth 927) Ask for Ranjit Adhikary. Freebie: ear buds
MunEDA WiCked CMT converts analog/mixed-signal/RF circuits across
different foundries/processes. Transistor resizing, optimization,
and verification for best performance, area, low-power/low-voltage,
robustness against process variation and mismatch. Qualified for
FinFET, Bulk, Bipolar, BiCMOS, and FDSOI. New GUI for migration
and yield optimizer, faster PVT corner runs and MC sampling.
WiCked Circuit Suite does transitor resizing for PPA, too. Users
ST, GF, SMIC, Novatek, Infineon, Fraunhofer, Chipus, Perceptia.
(booth 852) Ask for Michael Pronath. Freebie: pens
Empyrean Skipper does super fast layout review, analysis, debug,
layout IP protection. 1TB GDSII. Marvel, Hisilicon, Sandisk.
(booth 651) Ask for Jason Xing. Freebie: fluffy toy
Keysight ADS and GoldenGate is for silicon RFIC design & simulation
New iPDK PyCell & TSMC iRCX support, more intuitive layout, does
electro-thermal on windows, harmonic balance & circuit envelope
converges faster. Qorvo, Skyworks, Broadcom/Avago, Qualcomm users.
(booth 838) Ask for Nilesh Kamdar. Freebie: none
ClioSoft SOS ADS does design data management for RF engineers using
Keysight Agilent ADS. Northrop, IDT, Quorvo, Rohde & Schwarz, Inphi
(booth 927) Ask for Ranjit Adhikary. Freebie: ear buds
Intento ID-Xplore resizing/biasing/migration of analog/AMS circuits.
(booth 517) Ask for Ramy Iskander. Freebie: stickers
DESIGN COMPILER & RIVALS
15.) Mentor Oasys-RTL does crazy fast RTL synthesis floorplanning, design
space exploration from "place first methodology". 3-hour runtimes
synth to floorplan a 2M inst chip 4G of machine memory. Synth-ed
and floorplanned 14nm 3M inst in 8 hours. 3.8M 28nm in 12 hours.
Designers can look at different views (logical, physical, timing).
New built-in memory exploration cockpit to find the best mem config
in your chip. Has integrated SQL dd to root-cause faulty RTL revs.
TI, Broadcom, Juniper, Qualcomm use Oasys. Xilinx Vivado is Oasys.
(booth 334) Ask for Badru Agarwala. Freebie: plinko prizes
Cadence Genus RTL is an attack on Aart's 30 year Design Compiler
franchise. It's Anirudh's home-grown, massively parallel RTL and
physical synthesis tool that's "5X faster" than Design Compiler,
"1/2 iterations between unit and block/chip-level synthesis".
Genus got #4 "Best of 2017" with users in DAC'17 #4 and won a
user benchmark vs. DC-Graphical in ESNUG 582 #1. Broadcom, Texas
Instruments, Cienna, MaxLinear, Broadcom, Cisco, ImgTec are users.
"Hey, everyone! Genus RTL is on AWS and Azure clouds now, too!"
(booth 915) Ask for Kam Kittrell. Freebie: Denali party tix
Synopsys Design Compiler NXT is now 2.5x faster than old Design
Compiler Topo. "We beat Genus in benchmarks!" In production with
8 customers. Claims improved backend (ICC2) correlation at 5/3nm.
(booth 367) Ask for Sassine Ghazi. Freebie: pens
RTL & GATE POWER
16.) Calypto PowerPro does RTL power optimization. Users see 9% to 12%
general Verilog RTL power savings. 37% cut in sequential logic power
saving in ESNUG 535 #2. Chatting up their "What If" ability with
to quickly understand power effects of potential mode, operating
environment or design changes "saving hours of turn-around-time".
PowerPro is only tool that's tight with Calypto SLEC-Pro sequential
EC. Verifies low power RTL tweaks are equivalent to original RTL.
Users gush about Calypto PowerPro, but quiet about Ansys PowerArtist,
or Synopsys SpyGlass Low Power, or Cadence Joules in DAC'16 #9.
Has ~85% correlation against gate-level. 16/14/10nm FinFET.
Qualcomm, TI, Samsung, ARM, HiSilicon, Google, Freescale users.
(booth 334) Ask for Badru Agarwala. Freebie: plinko prizes
Apache PowerArtist users saw 3% to 10% reductions. Does automatic
and guided. Sequential and combinational clock-gating constructs,
memory light/deep sleep modes, and wasted power in datapath logic.
RTL power accuracy within 15% of sign-off. 10 M gates in an hour.
16/14/10/7nm. Handles 100M+ instances. Hooks with RedHawk for
power grid integrity. Also peak power & thermal hotspot analysis.
Has tight hooks into MENT Veloce emulation and Power App. Activity
streaming 10X faster vs. old slow FSDB for millisecs of activity.
Users are Broadcom, Nvidia, Samsung, ST, NXP, Toshiba, ARM, Ciena.
(booth 935) Ask for Vic Kulkarni. Freebie: stuffed animal
Synopsys Atrenta Spyglass Power users got 9% to 16% power cut on
Verilog RTL. RTL, gate-level, or post-layout. FSDB, VCD, SAIF
and vectorless. Does ECO's, CPF, UPF, mem in sleep mode. ERC
checks on P/G netlist. Power modeling and coarse clock gating.
(booth 367) Ask for Piyush Sancheti. Freebie: pens
Cadence Joules is an RTL power calculator. Estimates power at RTL
to 15% of signoff power, time-based power up to 20X faster. It has
as "power scrubbers". Joules works with Genus RTL and Palladium.
"Hey, everyone! Joules is on AWS and Azure clouds now, too!"
ARM, Broadcom, TI, Socionext, Renesas, Microsemi, Analog Devices
(booth 915) Ask Rob Knoth. Freebie: Denali party tix
Baum PowerBaum does static & dynamic RTL power analysis that's up to
"100X to 200X faster" vs. PowerPro/PowerArtist/Spyglass. "We couldn't
find a fast/accurate tool to do this, so we built one of our own!"
(booth 960) Ask for Andy Ladd. Freebie: none
CDNS JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks to
see any issues the after the insertion of power management circuitry.
(booth 915) Ask Pete Hardee. Freebie: Denali party tickets
Mirabilis VisualSim Power v2.0 measures system level power on
your SoC or uP model. Does power gating and sleep modes. Users
are China Auto, IBM, Analog Devices, AMD, and Sandia Labs
(booth 866) Ask for Deepak Shankar. Freebie: glasses cloth
RTL ENVIRONMENTS/SIMULATORS/TOOLS
17.) Metrics MCS is a System Verilog simulator written from the ground up
to be run in the cloud. It's fully compliant to the IEEE 2012 SV
spec, too. First user review at ESNUG 580 #2. These hockey loving
Canadians are pioneering the 4-cents-a-minute SaaS price model in EDA.
First known EDA tool on Google Cloud. Joe Costello is with them!
(booth 1219) Ask for Doug Letcher. Freebie: playing cards
Synopsys Verdi is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 367) Ask for Thomas Li. Freebie: pens
Verifyter PinDown auto debugs regression failures by IDing the
commits that cause the test failures and automatically assigns bug
reports to the engineers who made these commits. PinDown debugs
down to the exact line of code. Now instantly detect high-risk
code changes without any simulation. Samsung, Broadcom, Synopsys.
(booth 620) Ask for Daniel Hansson. Freebie: chocolate kisses
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 667) Ask for Chouki Aktouf. Freebie: candy
Mentor Questa Sim bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, formal in one big smudgy bundle.
ISO 26262 certification, real number modeling, P1735 encryption.
(booth 334) Ask for Mark Olen. Freebie: plinko prizes
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
The Plot Viewer does simple/polar/vector graph and image/color map.
Python support using Cocotb GPI. This enables terse, readable,
maintainable code while providing easy Python abstraction to RTL.
(booth 623) Ask for Stanley Hyduke. Freebie: pens
Amiq Eclipse DVT IDE is an add-on to VCS/Questa/Incisive that lets
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta like Visual C stuff.
Samsung, Intel, Broadcom, Qualcomm, Toshiba, SK Hynix, Micron.
(booth 854) Ask for Cristian Amitroaie. Freebie: chocolates
Sigasi Studio is much like Amiq DVT. System Verilog & VHDL support.
Last year added Visual respresentation and GUIs for documentation.
NXP, UTC, ASML, Thales Group, Thales Alenia Space, Airbus, Philips,
Rohde & Schwarz, Bosch, Siemens, Facebook, MacLaren, Easics, Harris,
Prodrive, Johnson & Johnson, SCD, ABB, Saab, BAE, EPSON, GE, Dolby
Laboratories, CERN, Fraunhofer Institute, Heidenhain uses it.
(booth 646) Ask for Bart Brosens. Freebie: Belgian chocolates
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for registers/sequences into UVM/RTL. NASA, Intrinsix,
HGST, Icron, Conexant, Wipro, Conexant, John Deere, CERN uses Agnisys.
(booth 812) Ask for Sameer Rahurkar. Freebie: stress balls
SystemC/C/C++/TLM STUFF
18.) Out of nowhere, Brett Cline of Cadence SystemC (and chicken suit) fame
just left Cadence and instead joins OneSpin? (You know, that OneSpin
that does formal tools???) WTF?
OneSpin 360-SystemC auto checks array overflow, underflows, array
bound errors, uninitialized variables, divide-by-zero, illegal shifts
in SystemC stuff. "Brett, what the eff are you doing at OneSpin???"
(booth 308) Ask for Brett Cline. Freebie: beer mugs
Mentor Catapult HLS synthesizes C++/SystemC into Verilog/VHDL to
target either FPGA or ASIC. Kicks ass at developing designs that
accelerate machine vision or do machine learning. Does top-down
and bottom up, cuts project times in half and verification costs by
80%. C->RTL visualizer. Has libs and I/O for Xilinx and Altera
to crank clock frequency, plus hooks into Mentor Oasys-RTL.
Partnership with Synopsys for better correlation and QoR. New
toolkits for AI/Machine Learning (YOLO Tiny) and complicated math.
AC_data_types open source on GitHub and still way faster than
SystemC types with none of the ambiguities.
Catapult Checker & Coverage does formal/lint checks on synthesizable
SystemC and C++ to prevent ambiguous or bad logic mistakes. Coverage
covers C statement, branch, toggle, expression, and array indexing; all
done hundreds of times faster than RTL simulation coverage. Qualcomm,
Nvidia, ST, Google, FotoNation, SeeCubic, Bosch, Fujitsu, Toshiba.
(booth 334) Ask for Badru Agarwala. Freebie: plinko prizes
Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
RTL that Design Compiler or CDNS Genus can easily digest. Can do both
control logic and datapaths. Claims better accuracy than Catapult.
Hooks into CDNS Genus RTL synth, Joules low power, and Innovus PnR.
Supposedly can see PnR congestion issues in your SystemC/C/C++ source
HiSilicon, NXP, Bosch, Samsung, LG, Realtek, Toshiba, Fujitsu, Ricoh
At one time Brett owned the C synth space, but Badru stole his crown.
(booth 915) Ask for Dave Pursley. Freebie: Denali party tix
Synopsys Synphony C plays here but probably not showing at this DAC.
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Rivals Synopsys Hector and Jasper EC.
Runs "bottom up" partitions. LSF support. Nvidia, Google, ARM users
(booth 334) Ask for Badru Agarwala. Freebie: plinko prizes
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. It competes against Cadence
Virtual, Synopsys Virtualizer, Mentor Vista, and Wind River Simics.
NoCs. Fault injection. Linux, FreeRTOS, OpenRTOS, uC/OS, MQX, eCoS.
Now Imperas OVP has 40 EPKs, 170 CPU models of ARM, MIPS, RISC-V.
Users are ImgTec, Renesas, Recore, Altera, Audi, AMD, Nagravision.
(booth 1030) Ask for Larry Lapides. Freebie: USB charger
VERIFICATION IP
19.) Mentor Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet (400G, 100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I3C, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); FLASH Family (SDCard4.2,
SDIO4.1, eMMc5.1, ONFI4.0, Toggle, UFS, Parallel NOR, Serial NOR);
Display (CDC, DisplayPort, eDP, V-by-One, HDMI 2.1, HDMI 2.0,
HDMI 1.4, HDCP 1.4); HyperBus (Hyperram, Hyperflash); Auto (CAN,
CAN-FD, LIN); Mil-Aero (Spacewire, 1553b, PCI); 5G (JESD204B,
CPRI); Storage Family (SATA); NVMe over Fabric, Interlaken, I3C.
Now added PCIe 5, USB 3.2, DDR 5, LPDDR 5, UXSGMII, Ethernet Base T
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, Marvell, ST users.
"Oh, don't forget we have 1700 combinations of memory models, too!"
(booth 334 or 617) Ask for Bryan Ramirez. Freebie: plinko
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2, Ethernet 25G/50G, HBM, HMC,
MIPI DSI-2, WiFi MAC, CCIX, BLE5, DDR5" -- plus new "PCIe 5, HBM2,
LPDDR5, MVMe 1.3, CHI-B, UFS 3, USB 3.2, USB Type-C, DSI 2.0, I3C."
Now added USB-4, DisplayPort 2.0, CCIX, LPDDR5, DDR5, PCIe Gen5
Denali-style API, all simulated VIP runs on VCS, Questa and Incisive.
"VCS or Questa customers do not need Specman e". TripleCheck.
Broadcom, HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung.
"CDNS VIP runs 2x faster vs. SNPS VIP due to optimized VIP C cores!"
(booth 915) Ask Moshik Rubin. Freebie: Denali party tix
Avery Verification IP (VIP) does PCIe 5.0, DDR5, HBM2E, CXL, CCIX,
Gen-Z, Ethernet 400G, CSI/DSI, I3C; ARM and RISC-V. "Use all 59 VIPs
with one license!" HiSilicon, Samsung, Broadcom, Xilinx, Marvell.
(booth 808) Ask for Chris Browy. Freebie: cellphone mount
SmartDV VIP claims "many VIP and sim acceleration IPs." (booth 514)
HARD & SOFT IP
20.) Talk about a corporate eff up! ARM decided to not show at DAC, thus
yeilding the mindshare over to their RISC-V rivals! D'oh!
SCOOP! -- SiFive RISC-V is hot news of DAC'19. Scroll up to #1.
SCOOP! -- scroll up to "Virtuoso & Rivals" section of this list to
see the Movellus PLL Generator, DLL Generator, LDO Generator tools.
Silvaco Samsung Foundry IP -- holy crap! How did Iliya's little tiny
company manage to get the rights to sell Samsung Foundry design IP for
their 14nm, 11nm, 10nm, 8nm FinFet and 28nm FD-SOI process nodes???
PCIe, DDR/LPDDR, MIPI PHY, Ethernet, HDMI, USB3.1, DisplayPort,
V-by-One; along with data converters, PLLs and other analog IP.
(booth 953) Ask for Dave Dutton. Freebie: mouse
Synopsys is showing its Virage DW ARC 600 & 700 cores, plus its
mem IP, plus std cell libs; that all directly compete against ARM.
DW ARC HS4x and HS4xD processors. 6000 DMIPS per core. Security.
ARC now has 226 customers. DW ARC comes in low power and audio.
"Hey! You engineers! STOP looking at those damn RISC-V cores!"
(booth 367) Ask for Mike Thompson. Freebie: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
Last year says it has new fully verified/certified PCIe 5.0 rev 0.7.
(booth 915) Ask for Rishi Chugh. Freebie: Denali party tix
Silvaco Xena scans a chip-level database to list all detected IP and
versions of that IP. Works for embedded SW, too. It scores the
extent to which IP exists in the chip, from its entirety to fragments.
(booth 953) Ask for Hiren Mistry. Freebie: mouse
Silvaco NanGate IoT Std Cell Libs are "IoT optimized" full custom
libraries. 9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm silicon
proven. Cut area by 8-14%. "Our 8T 28nm GF lib got 55% higher raw
gate density." (booth 953) Ask for Jens Michelsen.
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precisionv clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 311) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 encoders, JPEG IP. New Geon "secure" uP, J2716, MIL-STD 1553.
(booth 810) Ask Nikos Zervas. Freebie: stylus pen
Omni Design sells ADCs, DACs, bandgaps, oscillators, LDOs, temp
sensors. 28nm to 180nm. For IoT. (booth 549) Ask Denis Daly
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". Now multiple proven 7nm PLLs this year.
"We have 5nm PLLs, too!" TSMC, SMIC, UMC, GF, Samsung, ARM, Toshiba
(booth 525) Ask for Andrew Cole. Freebie: USB car chargers
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 7FF+. (booth 553) As for John Maneatis.
BIG DATA & ANALYTICS
21.) IC Manage Envision is a tapeout predictor based on Big Data. It was
the #1 Cheesy Tool of DAC'15. After data mining 2 years company-wide
man-hours and 28nm EDA tool run logs, Xilinx used Envision to predict
their Zynq 20nm migration tapeout to within +/- 1 week. ESNUG 550 #1.
Verification Dashboard of job submissions to LSF, with real-time job
monitoring, results parsing, historical analysis, aggregated
analytics. Dynamic Graphs, custom field expansion.
Envision Analytics uses big data for real-time analytics for multi-
vendor verification environments. It's like Cadence Indago but
it lets you add in non-CDNS tools, too. 10-100X speed up. Visual,
interactive reporting for regressions, bugs, and coverage. Results
linked to relevant design activity to help ID & resolve bottlenecks.
(Booth 325) Ask for Steve Klass. Freebie: chocolates
TEST/SCAN/BIST/JTAG/FAULTS
22.) Here's why Sawicki's test brainiacs beat out Aart in ATPG/scan test.
Mentor TestKompress does hierarchical ATPG. Patterns are generated
independently for each core. Can be retargeted at chip top-level.
10x faster generate time and 1/10th CPU time of Synopsys TetraMAX.
Pattern count is 1/2, so less test time. Also this core-level ATPG
means no wait for whole design to be done before ATPG generation.
TestKompress does end-to-end hierarchical, which takes DFT out
of the critical path, reduces ATPG and diagnosis runtime by 10X,
and pattern count by another 2X. Users are Broadcom, NXP, Renesas,
On Semi, Intel, NXP, Mediatek, Spreadtrum, and Annapurna Labs.
(booth 334) Ask for Geir Eide. Freebie: plinko for prizes
Cadence Modus Test does scan insertion, compression, ATPG, logic
and memory BIST. Physically aware 2D elastic compression cuts test
logic wirelength by 2.6X. Compression ratios 400X. Takes 1/3rd
tester time. Works with Genus RTL synthesis and because of hooks
into Innovus/Genus it has lower routing congestion, fast yield ramp.
Texas Instruments, GlobalFoundries, Microsemi, Sequans users.
(booth 915) Ask for Rob Knoth. Freebie: Denali party tix
Mentor Tessent MissionMode does hardware functional safety stuff by
system-level low latency access to on-chip test resources for on-
line test and diagnosis. Non-destrictive memory tests, too. Works
with Tessent LogicBIST and MemoryBIST or other IJTAG test IP.
Mentor Tessent ScanPro places test points in netlist for compression.
Adding 1%-2% area for a 3X to 4X reduction in ATPG test patterns.
If 100X compression with Synopsys TestKompress, Mentor ScanPro gets
300X to 400X. VersaPoints for hybrid ATPG/BIST coverage. OCC
insertion, X-bounding for logic BIST. Improves logic BIST coverage
by 2%-4% and gets to 90% coverage 8x faster. ISO 26262 likes this.
(booth 334) Ask for Geir Eide. Freebie: plinko for prizes.
Synopsys SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
(booth 367) Ask Kiran Vittal. Freebie: pens
Mentor Tessent DefectSim does transistor-level fault simulation for
analog, mixed-signal, and non-scan digital circuits when test quality
must be measured, or improved, or maintained while test cost is cut.
It automatically calculates all necessary ISO 26262 hardware safety
metrics like SPFM, LFM, DC and PMHF. Users are On Semi, AMS AG.
(booth 334) Ask for Matthew Knowles. Freebie: plinko for prizes
Mentor Tessent Diagnosis and YieldInsight uses failing test data to
find logic & physical layout yield problems "in days, not months."
Spots systematic yield issues at transistor level. Samsung, Cypress.
Mentor SiliconInsight used to be limited to desktop setup for
memory/logic BIST diagnosis and ATPG. Now with new ATE-Connect
directly connects to ATE (Teradyne and Advantest). It's a common
bring up platform from simulation to desktop to ATE. Speeds up
IJTAG debug "from weeks to days". Users are Graphcore, Cypress.
(booth 334) Ask for Matthew Knowles. Freebie: Plinko for prizes
ROLL-YOUR-OWN EDA SOFTWARE STUFF
23.) Verific sells System Verilog, VHDL, UPF parsers with C++ interfaces
to EDA developers. Perl and python APIs. Synopsys, Cadence,
Mentor, Ansys, Xilinx, Altera, AMD, Nvidia, Infineon, Samsung,
AMD users. Has Invio, a collection of high-level Python APIs that
make it easier to interface with their core Verific parsers.
(booth 638) Ask for Michiel Ligthart. Freebie: stuffed giraffe
Mirabilis Collaborator generates docs and javascript for executing
models within a web browser. Used as specification or a customer
demonstration tool. Does parameter/algorithmic/topology changes.
(booth 866) Ask for Deepak Shankar. Freebie: glasses cloth
OneSpin 360 LaunchPad lets companies with no formal tools develop
and deliver formal-based apps inside their own in-house EDA SW.
(booth 308) Ask for Raik Brinkmann. Freebie: Monday party tix
WORKSPACE, DESIGN DATA MANAGMENT, & IP TOOLS
24.) OpenText (Hummingbird) TurboX gives you secure remote access to UNIX
or Windows apps in datacenters. Competes against VNC, RDP. ETX has
20-50% faster response time than VNC for most UNIX apps. Can handle
high latency access (up to 165 msec) pain free for the EDA tool user.
Support for Nvidia GRID-optimized virtual desktop infrastructure.
(booth 1117) Ask for Rod Simon. Freebie: ear buds
ClioSoft designHUB is a data management tool where project engineers
can create and upload IPs, browse, search, and compare available IPs,
easily track the IP lineage, issues, defects and their resolutions.
"A one-stop-shop for all designs within your company immaterial of
where the design data is physically located." Claims SOS, Perforce,
Git, SubVersion "or any network storage." Skyworks uses designHUB.
(booth 927) Ask Ranjit Adhikary. Freebie: pens
IC Manage GDP design & IP data management system lets digital/custom
designers find, modify, release & track design data through tapeout.
Bug interdependency management. Multi-tier web stuff. Samsung, AMD,
Intel, Xilinx, Nvidia, Nokia, Northrop Grumman, Viasat, Aquantia.
IC Manage GDP-XL adds the following features to GDP: Customizable
schemas by project or component, with easily extendable templates.
Supports central, distributed & hybrid development. Web UI, REST API
(booth 325) Ask for Alex Tumanov. Freebie: candy
IC Manage PeerCache for "hybrid cloud bursting & HPC cloud apps". Run
existing jobs in cloud in minutes, with minimum cloud storage costs.
PeerCache dynamically determines exact data needed by a job for fast
upload, with no data duplication or synch needed. ESNUG 582 #8. Also
supports pure cloud apps. Delivers scale out I/O. On-prem & cloud
infrastructure-compatible. Got top 5 "Best of 2017". (DAC'17 #5)
(booth 325) Ask for Mike Whalen. Freebie: candy
ClioSoft SOS7 does HW configuration management and rev control for
Virtuoso, Laker, Pyxis, Custom Compiler, Keysight ADS. Built-in IP
management and reuse. Does soft integrations with in-house flows.
Better security, improved IP traceability, Jenkins integrations.
"SOS7 now supports the cloud, too!" Hooks to JIRA, Trac, Bugzilla.
Huawei, Google, Analog Devices, Infineon, Toshiba, Marvell, TSMC
(booth 927) Ask for Ranjit Adhikary. Freebie: pens
Mentor Questa VRM is verification run management system that combines
coverage metrics from formal, CDC, simulation, and emulation engines.
Accellera UCIS standard, and Jenkins regressions. Nokia & Micron.
(booth 334) Ask for Mark Olen. Freebie: plinko prizes
Cadence vManager is just like Questa VRM, but has an API bug systems,
source systems, or agile development systems. Very verificationy.
Deep hooks with Cadence Incisive, Palladium, Xcelium, and JasperGold.
Fujitsu, Analog Devices, ST, Qualcomm, Allegro, Infineon, Teradyne.
"Hey, everyone! vManager is on both AWS and Azure clouds now, too!"
(booth 915) Ask for Matt Graham. Freebie: Denali party tickets
Methodics Percipient is a "graph database providing customers 5X
performance improvement in IP data management and analytics." It
also does "issue and defect management and requirements management".
Samsung, Micron, Silicon Labs, Cirrus Logic all use Percipient.
(booth 945) Ask for Simon Butler. Freebie: cellphone wallets
Fractal Crossfire does format consistency checks on hard IP? Huh?
(booth 561) Ask for Felipe Schneider, Freebie: none
Empyrean Qualib also does format consistency checks on hard IP?
But whatever it is, Marvell, SMIC, and HiSilicon use Qualib.
(booth 651) Ask for Jason Xing. Freebie: fluffy animal
Univa Grid Engine does data center resource management like LSF. Has
a licence orchestrator built-in, too. (booth 1233) Ask Neil Bendov.
Amazon AWS is easily the #1 host for EDA, but not showing at DAC.
Microsoft Azure is now the #2 host for EDA tools. (booth 1215)
Google Cloud is a distant #3 host for EDA tools. (booth 1216)
IBM Cloud is very distant #4 mostly for IBM tools. (booth 1220)
Alibaba Cloud only in China and is unknown in EDA. Not at DAC.
Anyway, I hope this helps! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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