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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2012"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this as an unofficial guide to the
San Francisco DAC exhibit floor. List ranked in order of importance.
RTL POWER REDUCTION
1.) This year's #1 "must see" is a 3-way tie between (alphabetical order)
Apache PowerArtist, Atrenta Spyglass Power, and Calypto RTL PowerPro.
Why? To quote recent user discussions "because PrimeTime-PX is too
late." (i.e. doing power reductions at gate-level doesn't cut it.)
Calypto is mostly known for SystemC/C/C++ EC. Yet Calypto PowerPro
got recent user notice in ESNUG 500 #5 & 501 #5 where users reported
9% to 12% power reduction on their Verilog RTL. At DAC'12 Calypto
will claim "better/faster QoR". TI, AMD, STARC, Ikanos uses them.
(booth 1226) Ask for Shawn McCloud. Freebies: M&M's and tatoos
Atrenta Spyglass Power is well known here and got recent user notice
in ESNUG 500 #4 & 501 #4 where users got 9% to 16% power reduction on
their Verilog RTL. At DAC they'll chat up CDC-aware power reduction,
CPF, UPF, mem power reduction, 2X improvement. Cisco, TI, Ericsson,
Juniper, Marvell, Samsung, Infinera, Ricoh, Olympus, Renesas uses it.
(booth 2230) Ask for Kiran Vittal. Freebie: "cool" t-shirt
Apache PowerArtist was discussed in ESNUG 502 #2 & 505 #8 where users
saw 3% to 10% reductions. At DAC its "30X faster than cycle-based RTL
power analysis" and pre-synth power grid floorplans. AMD, Exar, LSI,
Samsung, Sigma uses it. Was originally Sequence PowerArtist until the
$5.3 M merger in 2009. Perhaps Vic Kulkarni sold Sequence too soon?
(booth 1813) Ask for Will Ruby. Freebie: stuffed animals
PRIMETIME ALTERNATIVES
2.) Due to the Extreme DA lawsuit & forced $17 million merger, plus the
1/2 billion $$$ Magma acquisition, plus a do-nothing FTC, means Aart's
PrimeTime keeps its sweeeeeeet near-monopoly lock in STA signoff.
In reaction, sudden interest in Cadence Encounter ETS as a possible
alternative. This year ETS was rewritten with a new analysis engine
that does CeltIC-accurate SI analysis at 10 M inst/hr (up to 30 M),
"physically aware concurrent MCMM analysis & optimization" plus it
comprehends existing cell placement and does legal placement ECOs.
Examples: 2 M inst block, 32 views, 700 hold viol fixed in 1 hour;
17 M inst block, 48 views, 3,000 hold violations fixed in 8 hours.
Also shows TSMC/ARM/CDNS ETS for 20 nm. Samsung, ST, Freescale user.
(booth 1930) Ask for Ruben Molina. Freebie: Denali party tickets
At SNPS, see Extreme GoldTime rebranded as faster PrimeTime, AOCV,
"clock reconvergence pessimism removal" and PT-SIG dinner. Question
what of Magma Tekton they kept? (booth 1130) Ask for Sunil Walia.
CHECK THIS OUT: Dorado Tweaker is a family of ECO tools. Mapped here:
Functional ECO / Timing ECO / Power ECO / Metal ECO / Clock ECO
Tweaker-F1 / Tweaker-T1 / Tweaker-P1 / Tweaker-M1 / Tweaker-C1
Synopsys PrimeTime-ECO vs. Tweaker-T1
Cadence Conformal-ECO vs. Tweaker-F1
Tweaker is physical aware. Does ICC, SOC Encounter, Atoptech, Magma.
Everything in Tweaker is incremental, partial, with ECO algorithms.
Tweaker-T1 runs 5.5 hours to clean 97% of (400 K+) hold violations for
1.55 M instance block with 72 scenarios with only ONE license and one
CPU. Now multi-CPU is ready. Tweaker-F1 does pre/post mask ECO with
old/new RTL plus post-layout netlist. There's US patented algorithm
for very small ECO size. New method for minimizing the size of ECO
logic will be show at DAC. Tweaker-P1 does netlist leakage power
reduction by vt-swap & sizing. Broadcom, TSMC, Mediatek, Samsung users.
(booth 2717) Ask for JJ Hsiao. Freebie: leftover ECO gates & metal
Cadence Conformal ECO Designer does "big ECOs that may seem impossible
to implement." New for DAC "streamlining ECO analysis/implementation"
and "one customer said ECO implementation time from 8 days to 1 day
using our new hierarchical ECO flow." Cisco, ST, FreeScale are users.
(booth 1930) Ask for Kenneth Chang. Freebie: Denali party tickets
CLK-DA AOCV FX makes volt/temp/constraint derate tables for PrimeTime.
Build derate db for one corner for 1000 cells in 1.2 hr using 100 CPU.
"all load/slews, all arcs for all cell types." AMD, TSMC, CSR users.
CLK-DA Path FX does derate for paths in PrimeTime. Added distribution
and capacity. Corner delay "takes 1 sec per path, corner statistical
takes 4-8 sec, and full statistical 10 to 20 seconds." Results are
within 2% of SPICE for nominal and nominal plus 3 sigma.
NEW TOOL: CLK-DA Margin FX analyzes available timing margin and tunes
static timing derates. Evaluate different timing derates for process
variance, temperature and voltage on slack and delay in minutes. Has
diff tool for different STA corner runs. Works with PrimeTime.
(booth 430) Ask for Isadore Katz. Freebie: candy & mints
IP TOOLS
3.) IC Manage IP Central maximizes a company's internal IP reuse; can be
a mix of homebrew and purchased IP. Trace bug dependencies. Fixes
across all IP versions and designs. Bug history can be viewed. IP
is searchable. Was a Top 5 DAC'11 #5 pick. Broadcom uses it.
(booth 1914) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
Atrenta SpyGlass IP Kit checks soft IP for problems, plus definitions
of the rules to run, scripts to automate the process, documentation,
and a test design to make sure everything is installed correctly.
This year added routing congestion analysis and Cyclomatic complexity
scores -- a measure of the number of paths through a piece of code.
Atrenta GenSys Assembly does IP integration, chip assembly, automated
RTL generation. Competes vs. Synopsys CoreAssembler or Duolog Weaver.
Live hookup error checking. Generates RTL netlist. Does hierarchy
manipulation, group/ungroup IP, IP movement while preserving existing
connectivity. SDC validation. Physical congestion and timing.
Texas Instruments, Broadcom, ST Microelectronics, LG, Canon, Renesas.
(booth 2230) Ask for Mike Gianfagna. Freebie: t-shirt
BUGHUNTERS
4.) Mentor Questa Static will be making its first public appearance at
this DAC. It competes with Jasper, RealIntent, CDNS IFV, and appears
to be 3rd gen 0-in. Automatic code coverage closure, X-prop checks,
SoC connectivity checking, 1000x faster formal prop checking, 10x
faster/bigger CDC. 150 M gates CDC analyzed 8 hours in a flat run.
43 K formal properties in 30 minutes. AMD, Qualcomm, Infineon users.
(booth 1530) Ask for Mark Eslinger. Freebie: diet Coke
NEW IDEA: Jasper DA has made one common db of its formal bughunter
stuff and you add specialized JasperGold Apps on top. They have apps
for "formal property verification, x-propagation, connectivity,
executable specs, behavioral property synthesis, structural property
synthesis, RTL development, architectural models, etc." No need for
formal experts! Nvidia, Juniper, Microsoft, AMD, Qualcomm, ST users.
(booth 830) Ask for Rajeev Ranjan. Freebie: Starbucks gift card
NextOp BugScope creates assertion synthesis and functional coverage
properties. Now has "apps" for IP/SOC integration, UVM migration, and
functional coverage reports. Marvell, Nvidia, Samsung, AMD users.
(booth 900) Ask for Yunshan Zhu. Freebie: weird wire thingys
RealIntent Ascent XV does a "fast static hazard analysis to identify
X-sources and nets susceptible to X-issues. X-optimism functional
bugs are isolated during RTL simulation. At netlist, X-pessimism is
identified and corrected. Now does initialization optimization and
low power." Ascent Lint is "now faster and has 50 new System Verilog,
Verilog, VHDL, netlist rules." Nvidia, Dialog Semi, Agilent users.
RealIntent Meridian CDC does "timing analysis SDC data to validate
complete clock coverage." New front-end, faster and "did 50 M gates,
155 clock domains in 4 hours." Nvidia, Cavium, Magnum users.
(booth 926) Ask for Lisa Piper. Freebie: pocket multi-tool
Atrenta SpyGlass Lint now does "Fast Lint", a smaller set of critical
lint checks 5-10x faster than default checks. Cyclomatic Complexity
metrics. SpyGlass CDC has a new abstraction-based hierarchical CDC
methodology that is 6-8x faster SoC level runs vs. running flat.
Qualcomm, Cisco, TI, ST, Renesas, Panasonic, Intel, Infineon users.
(booth 2230) Ask for Sean O'Donohue. Freebie: t-shirt
FishTail Confirm formally verifies design constraints. "Generates
less false warnings" and "we've added formal CDC verification, too."
NEAT TOOL: FishTail Focus "take functional, tft, shift and capture
mode constraints and collapse them into a single super mode on 500 K
inst design in 2 hours no loss of accuracy for signoff STA (SI on,
SPEF loaded)" and "cut P&R runtimes 50%". TI, Broadcom, STARC users.
(booth 328) Ask for Ajay Daga. Freebie: none
Amiq Verissimo SV TB Linter performs code linting for generic System
Verilog code and UVM. (booth 1804) Ask for Cristian Amitroaie.
SpringSoft Verdi 3 is a "major rewrite of Verdi product that delivers
2x performance increase and 30% smaller files" and new Qt-based GUI.
(booth 1030) Ask for Thomas Li. Freebie: iPad/tablet cases
NEW TOOL: Avery SimXACT "eliminates X pessimism in gate-level sim,
resolves gated-clock X issues, and does sequential X backtracing
reporting" and "finds X optimism that causes non-determinism."
Now works directly in VCS, NC-Sim, and Questa. Broadcom uses it.
Avery PSYN does assertion synthesis for baseline verification metrics.
Extracts microarchitectures. "now over 15 microarchitecture functions
and over 60 assertions, cover properties, and covergroups supported."
(booth 1117) Ask for Kai-hui Chang. Freebie: LED flashlight
Vennsa OnPoint 2.0 "now cuts debug time by 70% or more, using new
path-based debug features and forward-thinking analysis." Increased
capacity, performance and language support. Hitachi uses it.
(booth 1901) Ask for Sean Safarpour. Freebie: maple candies
Blue Pearl Software Suite speeds FPGA design with RTL analysis, CDC
checks and automatic SDC generation. Gives feedback for validating
automatically generated pre-synthesis longest paths and SDCs.
(booth 714) Ask for Shakeel Jeeawoody. Freebie: mouse Pad
Cadence IFV doing a "It's the bundled deal, baby!" pitch this year.
(booth 1930) Ask for Joseph Hupcey. Freebie: yawns
Synopsys Magellan competes in formal, but I don't know if it's
showing anything new at this DAC.
SYNTHESIS
5.) Like last year (but with new $6 M in Series B funding) Oasys RealTime
takes your RTL and floorplan to placed-gates "10X to 60X faster than
Synopsys DC-Graphical can." Verilog, VHDL, System Verilog, MCMM
synthesis, DFT, UPF/CPF low power design. "Now we've done 28 nm
tape-outs!" TI, Juniper, Netlogic, Qualcomm, Intel, Xilinx uses it.
(booth 530) Ask for Paul van Besouw. Freebie: keyring flashlight
Cadence RTL Compiler does physical aware and low power optimized
synthesis of RTL to placed gates. Competes vs. Design Compiler.
Incremental congestion prevention. Physical aware logic & DFT. LP
synthesis (PSO, MSV, SRPG), leakage optimization via MVt, and RTL
power estimation. New multi-bit cell inferencing and physical
clock gating. Texas Instruments, Netronome, Imagination users.
(booth 1930) Ask for David Stratman. Freebie: Denali party tix
Xilinx is chatting up its new Vivado Design Suite at this DAC, which
I've heard is a combination of AutoESL (which they bought for $25 M
back in early 2011) for SystemC/C/C++ synthesis, and Oasys RealTime
(which they helped with $6 M financing) for Verilog/VHDL synthesis
down to placed-FPGA-gates. Vivado's needed for the new honking big
28 nm Xilinx chips that TSMC's supposed to deliver "any day now".
AMBA AXI4 interconnect, IP-XACT IP, Synopsys SDC, hierarchical chip
planner and partitioner, System Verilog. P&R for "timing, wire
length and routing congestion." ECO's, power aware, Tcl. 3X faster
RTL simulation, 100X faster HW co-sim. "Scales up to 100 million
ASIC equivalent gates." Broadcom Europe, National Instruments,
Synopsys, Oki, Hardent, Aliathon uses it. "Why bother with ASIC?"
(booth 730) Ask for Tom Feist. Freebie: USB stick pen
ACCELERATION / EMULATION / PROTOTYPING
6.) Cadence Palladium XP will have AMD discussing In-Circuit-Emulation.
Claims full ICE 10x speed improvement into Mhz range without loss
of analysis data. CPF acceleration, code coverage, dynamic power
analysis in acceleration mode. Sharp, Renesas, TI, LSI, PMC users.
(booth 1930). Ask for Raj Mathur. Freebie: Denali party tickets
Mentor Veloce 2 will get its first public showing at this DAC.
MENT's 2nd gen emulator based on their full custom emulation IC.
2X faster and 2X capacity of old Veloce. Backwards compatible.
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon uses it.
MENT also announces Veloce VirtuLAB, "an alternative to ICE".
(booth 1530) Ask for Jim Kenney. Freebie: diet Coke
EVE ZeBu is now power-aware, does post-run debugging, has 10G
Ethernet and PCIe 3.0 16x lanes transactors, and FLASH models.
Lib of "30 transactors, virtual bridges and ICE speed-rate adapters".
Fujitsu, TI, Konica-Minolta, Sony, LG, Ricoh, Broadcom, ST uses it.
(booth 1926) Ask Lauro Rizzatti. Freebie: tote bags.
Rocketick RocketSim loads your Verilog source into 100's of GPUs and
runs as a co-sim to Cadence NC-Sim, Synopsys VCS, Mentor ModelSim.
Scales to multiple-GPUs. "Compile 1 billion-gate design in 2 hours"
Now 4-state-logic for X-propagation. Got $2.5 M funding. Nvidea,
Mellanox, PMC-Sierra users. Ironically Nvidea uses current GPUs to
verify future GPUs! (booth 606) Ask Uri Tal. Freebie: chocolates
Synopsys HAPS Deep Trace Debug is what's new for SNPS in FPGA
emulation. (Synopsys ChipIt fell off the news radar after SNPS
bought it from ProDesign in 2008.) Synopsys HAPS may or may not be
at this DAC. They won't say. (booth 1130) Ask for John Koeter.
Cadence Rapid Prototyping Platform "models your SoC in FPGAs for
early SW development" and "6 Altera Stratix-4's for 30 M ASIC gates"
and "couple MHz up to 30 MHz" and "two x Gigabit Ethernet ports,
USB 2.0, 4-lane PCIe, JTAG and multiple UARTs" and "quick bring up
is in 4-6 weeks instead of 3-4 months." ARM and Nvidia users.
(booth 1930). Ask for Juergen Jaeger. Freebie: Denali party tickets
BEEcube miniBEE seems to be an FPGA system focused on military signal
processing for "MIMO, radar, SDR, and signal intelligence". Works
with Simulink and IP-Stitcher. (booth 519) Ask Rob Brodersen.
Gidel PROC_SoC10 is an FPGA-based prototyping system that does 120 M
ASIC gates each; and can be connected to do 360 M ASIC gates. System
clock up to 300 Mhz. (booth 1802) Ask for Reuven Wientraub.
Aldec HES is emulation SW for off-the-shelf FPGA prototyping boards
or custom in-house FPGA boards. Automatic partitioning, ASIC-to-FPGA
clock conversion, static/dynamic probes, memory viewer, triggering,
HW breakpoints. Claims 10 MHz on 100 M gate ASIC. System Verilog
transactors with DPI-C function calls. Fuji-Xerox, Sandia, Textron.
(booth 2126) Ask for Peter Czak. Freebie: 4 GB USB flash drive
NEW TOOL: SpringSoft ProtoLink Probe Visualizer "increases real-time
design visibility by up to 1000X and simplifies RTL debug of pre-fab
and custom-made FPGA prototype boards" and "add/change signals in
minutes with fast probe ECO flow." Works with SpringSoft Verdi 3.
(booth 1030) Ask for Howard Mao. Freebie: iPad/tablet cases
Flexras Wasga Compiler does timing driven partitioning for FPGA-based
rapid prototyping of ASICs. Virtex-6. Wasga Architect input HDL
design, interfaces, speed. Output a custom FPGA-based board netlist.
(booth 2810) Ask for Matthieu Tuna. Freebie: none
Dini Group says "V7 is here". (booth 1010) Ask for Mike Dini.
VERIFICATION IP
7.) Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
It's big collection -- why CDNS brags "come see why twice as many
customers use Cadence VIP than all other commercial VIP combined!"
- have VIP for "AMBA4 ACE, DDR4, eMMC 4.5, Ethernet 40/100G,
LPDDR3, LRDIMM, MIPI LLI, MIPI CSI-3, NVM Express, ONFi 3.0,
SATA 6G, SD Card 4, SSIC, UFS, Wide I/O."
- added a Denali-style API, all simulated VIP now runs on VCS,
Questa and Incisive. "VCS or Questa customers do not need
Specman, as support for the e language is built into our
simulator interface."
- Accelerated VIP runs "blazing fast on Palladium XP."
- TripleCheck, their IP validation tool is in its 3rd rev.
- "We have assertion-based VIP for the AMBA protocols and OCP."
Works with Cadence IFV.
Apple, ARM, Broadcom, Canon, Ericsson, HP, IBM, Intel, Hitachi, LSI,
Marvell, Qualcomm, Samsung, ST Microelectronics all use Cadence VIP.
(booth 1930) Ask for Erik Panu. Freebie: VIP ball cap
Synopsys Discovery Verification IP (VIP) is "100% System Verilog with
native UVM, OVM, VMM support" and "superior ease-of-use" because
Cadence VIP uses "wrapping layers that significantly hamper" run
times. Broadcom, Cavium, Freescale, Qualcomm , ST-Ericsson users.
Will also show Synopsys Protocol Analyzer, a "new simulator-neutral
debug environ" for protocols like USB, PCI Express, AMBA, OCP, etc.
(booth 1130) Ask for Neill Mullinger. Freebie: pens
Avery MIPI-Xactor is MIPI UniPro/M-PHY and UFS VIP. AMBA-Xactor is
AXI3/4, ACE, and AHB VIP. DDR-Xactor is DDR4, DDR3, LPDDR3, LPDDR2
SDRAM, RDIMM and DFI-PHY DDR PHY VIP. NVME-Xactor is NVM Express VIP.
Phison, Mercury Computer, GDA, Broadcom, SunPlus, TSMC use them.
(booth 1117) Ask for Zhihong Zeng. Freebie: LED flashlight
DIGITAL P&R
8.) Synopsys IC Compiler will have IC Validator (DRC) and Zroute handling
double patterning at 20 nm. SNPS evasive on who's using it at 20 nm.
If bored, ask what parts of Magma Talus and Quartz DRC they kept.
(booth 1130) Ask for Mark Bollar. Freebie: pens
Cadence Encounter Digital will be doing:
- combined physical-aware synthesis and optimization "for faster
timing closure" and "CCOpt (Azuro) that optimizes clocks and
data-path simultaneously" and claiming 10% faster chips.
- floorplanning now "handles designs of 100 million instances".
- "Silicon-proven, foundry-certified 20-nm flow with a unique
correct-by-construction double-patterning" and ECOs and area.
"Cadence Encounter Digital is the first and only ARM Cortex A15 tape-
out at TSMC 20 nm" -- the CDNS/ARM way of saying "%$#* you, SNPS!"
ST Micro, Samsung, TI, Fujitsu, Spreadtrum, Marvell uses this P&R.
(booth 1930) Ask for Rahul Deokar. Freebie: Denali party tickets
Mentor Olympus-SoC with be showing for 20 nm:
- Double patterning, native coloring, global conflict resolution,
"auto fix double patterning violations during routing" and "DP
prevention during placement using groups and spacing rules, color
anchoring, pre-coloring, coloring-aware extraction, and DRC/DP
Calibre signoff inside Olympus".
- Increasing wire resistance for lower metal layers. "optimizes
for high resistance across the design" and "interconnect
re-synthesis using layer promotion" and "via optimization and
critical path straightening"
Mentor Olympus Design Planning does a pseudo flat flow and automatic
macro placement. Whacks "inter-block timing modeling inaccuracies"
and makes "power-efficient clock trees". ST, Nvidia, AMD, Sondrel
users. (booth 1530) Ask for Sudhakar Jilla. Freebie: diet Coke
AtopTech Aprisa will be showing block-level P&R and Apogee will be
doing top level floor planning and chip assembly. "20 nm foundries
and design rules (multiple tape-outs)" and "Advanced OCV and POCV-
based optimization." Dynamic scenario selection lets you optimize
with all your sign off scenarios and "far fewer ECO loops". Broadcom,
PMC Sierra, Xilinx, Avago, PLX Tech, Cypress, Clariphy, Faraday users.
"We're #1 on Gary's list!" -- wrong. Gary orders list by DAC booth #.
(booth 322) Ask for Daniel Maung. Freebie: stuffed lion
Calibre nmDRC and Calibre Multi-Patterning "now include more complex
equation-based/voltage-based/double patterning DRC checks on 20 nm
golden sign-off decks (e.g. N20 and 20LPM)". Calibre PERC does "ESD,
Electrical Overstress (EOS), latch-up, voltage dependent DRC, and
multi-power domain verification." Calibre Yield Enhancer SmartFill
does intelligent, multi-layer metal fill for "perimeter and density
variation constraints, rapid thermal annealing, etch rates, stress."
Freescale, IBM, ST, Infineon, TSMC, MStar, SMIC, GF uses Calibre XXX.
(booth 1530) Ask for Carey Robertson. Freebie: diet Coke
ICScape TimingExplorer is a physically-aware MCMM timing ECO tool.
"ECOs done 50% faster." ClockExplorer does CTS with latency, OCV,
buffer level, buffer count and power. Both add-ons to ICC, Encounter.
Part of a 300 employee co in China called Huada Empyran Software.
(booth 1602) Ask for Steve Yang or Jason Xing. Freebie: water bottle
Pulsic Unity Custom Digital Placer is a "guided flow for placement of
custom and std cells with hierarchical clustering, extraction, ECO,
and STA." Their Unity Custom Digital Router is a "guided flow for
custom digital routing of extreme aspect ratios, top and block-level
routing and chip finishing. Full editing, DRC check and fixing.
Samsung, Micron, Hynix, Toshiba, NEC users. (HUH? CUSTOM DIGITAL??)
(booth 1908) Ask for Steve Ferguson. Freebie: LED keychain
FABS
9.) Before DAC'11, TSMC gave out hard copies of 250 slides they showed at
Technology Symposium'11. This year before DAC'12, at their symposium
they would NOT give out ANY slides whatsoever. Huh? (Word is Hsinchu
ordered a weird Samsung-style crackdown on all TSMC data to starve the
patent trolls who've been pestering them lately.) Also, I'm not sure
what TSMC will show at DAC'12, but I do know to NOT question 28 nm.
(booth 2430) Ask for Suk Lee. Freebie: "WHAT *$%&-ing 28nm PROBLEM?"
GlobalFoundries is dropping big $$$ in a marketing push on the DAC
exhibit floor to say that they're a fantastic alternative to TSMC.
Right next to the big-ass DAC pavillion is the big-ass GloFlo suite;
showing their love-fest with SNPS/MENT/CDNS plus AMD, Apache, Aragio,
Catena, ChipEstimate, Infinisim, Lorentz, Gradient, Socie, Uniquify.
"We've shipped well over 250,000 HKMG wafers" -- more than TSMC has.
(booth 303) Ask for Richard Trihy. Freebie: "We make 28 nm, too!"
Samsung Semiconductor made $1 billion worth of chips for a tiny little
company called "Apple" last year. Fabbing 32/28 nm now; 20 nm next.
ARM, AnalogBits, CDNS, SNPS, MENT, Uniquify will dance in their booth.
New packaging strategy. TSVs, 3D-IC, Wide I/O. "We make 28 nm, too!"
(booth 2001) Ask Benson Chenug or Yongjoo Jeon. Freebie: USB charger
TowerJazz does iPDK's for its volume 130 nm digital & AMS customers.
(booth 1105) Ask for David Postula or Russell Ellwanger.
MOSIS combines many companies' designs into one wafer run for low
volume and prototyping production. GF, IBM, TSMC. (booth 1119)
IMEC Europractice does low cost ASIC prototyping and small volume
production. 0.8 um to 40 nm from ON, IHP, TSMC, UMC. (booth 1709)
CMP does prototyping and low volume IC production. CMOS, SiGe,
BiCMOS from ST. CEA-LETI 20 nm FDSOI. GloFlo 3D-IC. (booth 1826)
TSMC spin-off, Global UniChip Corp. is a $300 million fabless ASIC
design company that designs and sells TSMC chips. (booth 2007)
VIRTUOSO & RIVALS
10.) Cadence Virtuoso will focus on layout dependant effects & color-aware
20 nm custom layout. "Live demos, not slideware!" ST Modgen talk.
"Real-time verification as layout is created!" Ask for John Stabenow.
Virtuoso Schematic Editor can now read and write CPF macro models to
enable formal low power verification using Conformal Low Power.
Used by HiSilicon, TI, Qualcomm, NXP, Fujitsu. Ask for Pete Hardee.
Virtuoso IPVS does on-the-fly signoff DRC checks as you design. 20 nm
double patterning. "can detect coloring loops real-time on foundry
rules." "Customers from 130 nm to 20 nm." Ask for Tianhao Zhang.
Cadence Constraint Validator (PVS-CV) is a "new" tool for full custom
designers. "automatic tracking of design intent in layout" and "can
validate the generated layout vs. specified constraints in schematic"
and "halo" check for errors by caused object symmetry for shapes
within a specified halo and its "neighbor parasitic effect."
(booth 1930) Ask for John Ahearn. Freebie: Denali party tickets
Cadence QRC Extraction SNA does substrate noise analysis for "full
block or full chip extraction for mixed-signal designs" and "predict
noise propagation between blocks not connected through power domains
or directly connected." Substrate PDKs, SOI substrate. Cadence QRC
Extraction Power is "only tool that can do PowerMOS embedded LSIs."
Both SNA and Power work well in CDNS Encounter Digital and Virtuoso.
(booth 1930) Ask Stewart Williams. Freebie: Denali party tickets
Synopsys Custom Designer seems to be emphasizing using a whole SNPS
flow "It's the bundled deal, baby!!!" and some new 3D-IC stuff.
Bored? Ask what parts of Titan ALX, Titan ALX, Titan ALX they kept.
(booth 1130) Ask for Andy Biddle. Freebie: pens
SpringSoft Laker 3 is a "new interactive, front-to-back" OA rewrite of
Laker for 28/20 nm. STARC and Toshiba users. Laker Blitz is a layout
editor for chip finishing for "IP merging, SoC assembly, and full-chip
DRC." Fast loading. "20 GB GDSII in 55 sec on 16 CPU machine" and
"On typical machine 16 GB in 6.5 min." Laker Analog Prototyping Tool
automates analog placement and gives feedback on layout parasitics.
(booth 1030) Ask for Dave Reed. Freebie: iPad/tablet cases
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Now hierarchical.
Also now works in DesignSync DM. Marvell, Toshiba, TSMC, ADI users.
(booth 2426) Ask for Karim Khalfan. Freebie: gym duffel bag
ICScape Skipper does chip finishing. "Layout viewing, editing, rapid
layout comparison, built-in DRC/LVS debugging, massive IP merge, SEM
image processing, focused ion beam (FIB) and 3D layout views, etc."
Part of a 300 employee co in China called Huada Empyran Software.
(booth 1602) Ask for Steve Yang or Jason Xing. Freebie: none
NEW TOOL: Solido Low Power+ uses Fast PVT meta-simulation for coverage
across power states, PVT corners, and layout RC corners. Nvidia uses.
Solido Analog+ is a Virtuoso sim add-on for worst-case PVT corners
and extracted n-sigma statistical corners. 10x efficiency increase
for PVT signoff, Monte Carlo analysis with multiple stop-on-yield
criteria, fast extraction of statistical corners at a target sigma,
and efficient, intuitive, interactive design sizing. Huawei uses.
(booth 2410) Ask for Amit Gupta. Freebie: none
Tanner EDA sells S-Edit schematic capture, L-Edit custom layout,
HiPer Verify DRC, and T-Spice SPICE. Founded in 1988, and known
for their "cost effective" pricing. Not bad for the cheap seats.
(booth 1126) Ask for John Zuk. Freebie: soft-grip pen
CHECK THIS OUT: Synopsys IC Compiler Custom Co-Design lets "design
teams to easily move between digital and custom implementation flows,
while maintaining design data integrity" and it does "DRC/LVS-correct
interactive mixed-signal auto-routing and DRC-aware custom editing."
It's big D, little A. Despite their usual marketing BS, this caught
my eye! Smells like Magma Titan. ST and Proteus Biomedical uses it.
(booth 1130) Ask for Ed Lechner. Freebie: pens
CLOUD SCAMS
11.) Synopsys asks "Any rubes wanna rent our EDA cloud space?" (booth 1130)
Cadence asks "Any rubes wanna rent our EDA cloud space?" (booth 1930)
Mentor asks "Any rubes wanna rent our EDA cloud space?" (booth 1530)
Aldec asks "Any rubes wanna rent our EDA cloud space?" (booth 2126)
Imera asks "Any rubes wanna rent our EDA cloud space?" (booth 1710)
Nimbic asks "Any rubes wanna rent our EDA cloud space?" (booth 2526)
Netlist asks "Any rubes wanna rent our EDA cloud space?" (booth 2707)
OpenText asks "Any rubes wanna rent our EDA cloud space?" (booth 2610)
Platform asks "Any rubes wanna rent our EDA cloud space?" (booth 2708)
Plunify asks "Any rubes wanna rent our EDA cloud space?" (talk 6U.6)
StarNet asks "Any rubes wanna rent our EDA cloud space?" (booth 1724)
Univa asks "Any rubes wanna rent our EDA cloud space?" (booth 1503)
"And, yes, we're the first in EDA to ever do anything like this!"
ANALOG / MIXED SIGNAL
12.) Cadence AMS Designer now has metric-driven assertion verification,
Real Number modeling and UVM-MS. Now supports CPF. Constraints
sharing using OA in an integrated Virtuoso and Encounter flow. Uses
'wreal' models and Spectre APS for performance on the pure SPICE side.
Fujitsu, HiSilicon, LSI, Texas Instruments, ST-Ericsson, IBM users
(booth 1930) Ask for Ahmed Elzeftawi. Freebie: Denali party tickets
For AMS, Synopsys will be discussing how they mixed SNPS/AVNT/LAVA
Custom Designer, HSPICE, CustomSim, FineSim and SiliconSmart ACE.
"It's the bundled deal, baby!!!" with cell/SRAM characterization.
(booth 1130) Ask for Geoffrey Ying. Freebie: pens
Pulsic Unity Analog Router is a "guided, intuitive, step-by-step
interactive or fully-automatic flow for Analog routing (NOT Custom,
but true Analog!) with a built-in DRC checker." Renesas uses it.
(booth 1908) Ask for Steve Ferguson. Freebie: LED keychain
Symica AMS Design Suite "integrates all the tools for mixed-signal
circuit design and simulation". SymSpice Turbo is fast-SPICE where
simulation time is reduced by factor 3x to 10x for a typical analog
design. "Can 10x- 15x by using hierarchical simulation config view
where a user can specify RUN_LEVEL (accuracy) option for each block."
(booth 702) Ask for Sergey Makarov or Vlad Potanin.
Analog Rails sells a "complete automated native OA MS design environ
with optimizer, router, schematic and correct-by-construction layout
always synchronized." Now does differential-aware density fill, power
grid mesh routing, bipolar support, and tighter layouts. No VC $$$!
(booth 2815) Ask for Cliff Wiener. Freebie: stolen CDNS pens
Ciranova Helix automatic custom layout. Now does LDE and density
optimization. Demo on a 28 nm, 40,000 device AMS layout in 8 days.
(booth 1608) Ask for Dave Millman. Freebie: sunglasses
Berkeley Analog FastSPICE "produces identical results to Spectre and
HSPICE (guaranteed)" and "AFS is 5x-10x faster than everyone on single
core and 2x faster on up to 8 cores" and "10 M-element capacity."
"accuracy is additional 5-15 dB dynamic range in transient analysis."
Qualcomm, Fujitsu, NXP, Samsung, Sony, LG, TSMC, UMC, Motorola users.
(booth 2509) Ask for Roshan D'sa. Freebie: disco light pen
NEW TOOL: Solido Memory+ ups yield by billions of Monte Carlo runs to
6-sigma. HSPICE/FineSim/CustomSim, Spectre/APS, BDA AFS. Nvidia uses.
Solido Standard Cell+ optimizes variation effects on std cells libs.
For efficient migration. CLI or batch operation. Huawei uses it.
(booth 2410) Ask for Amit Gupta. Freebie: none
NEW TOOL: Infiniscale IClys does 30x fast Monte Carlo, variability
and high-sigma analysis. "did 35,000 local variability parameters"
(booth 2713) Ask for Yoann Courant. Freebie: none
Cadence Characterization Altos Liberate cell library characterizer
Liberty SI, ECSM and CCS (timing and noise). Competes against Magma
SiliconSmart and Synopsys NCX. Altos just did native integration
with Spectre. "Customers will see more than 2x times the throughput
of our competitors." (booth 1930) Ask for Jim McCanny.
Cadence QRC Extraction parasitic extraction does "gate, RF, analog,
mixed-signal, custom digital, and LCD-TFT." It competes directly with
Synopsys Star-RCXT (plus Magma Quartz RC) and Mentor Calibre-XRC.
CDNS QRC does "RLCK extraction, 20 nm modeling, multi-corner and
statistical extraction, distributed processing, netlist reduction,
substrate noise extraction (SNA), inductance extraction" and works
well with Encounter Digital. "In 28nm benchmark, QRC did 3.2X better
TAT comparing a single interconnect corner vs 5 corners using 4 CPUs."
(booth 1930) Ask Stewart Williams. Freebie: Denali party tickets
NEW TOOL: EDXACT Belledonne qualifies layout parasitic extraction
flows. "It takes two extracted netlists and compares the content
without mercy and very quickly. Can compare different versions or
different settings of the same extraction tool, or compare netlists
from different tools." EDXACT Jivaro does RLCK reduction of
parasitics, generated by post-layout extraction tools. Cuts sim
time and mem footprint. Mediatek, TSMC, ST-Ericsson are users.
(booth 1002) Ask for Mathias Silvant. Freebie: none
NEW TOOL: Sagantec NMigrate migration and DRC correction of 28 nm and
20 nm layout. Competes vs. Cadence VLM. "Few tools exhist for 20 nm
library layout. Prolific was acquired and Cadabra isn't supported
anymore. Check how compaction deals with 20 nm rules at our booth."
(booth 1402) Ask for Simon Klaver. Freebie: none
Tela Innovations sells Tela Leakage Optimizer which cuts leakage
power in 90 nm to 28 nm. (booth 704) Ask for Scott Becker.
Integrand EMX is a 3D EM simulator for modeling on-chip passives
and interconnect. It can now generate RLCK spice models for arbitrary
N-port structures. TSMC, GloFlo, UMC, IBM, Samsung, Huawei users.
(booth 2814) Ask for Sharad Kapur. Freebie: none
IROC Tech TFIT predicts soft error FIT rate on CMOS digital cells.
TSMC 40G, 28HP, GF 40LP. "Within 15% of Si rad tests, simulation
lasts 3 min for 6T SRAM, 20 min for FF." Renesas, TSMC, GF uses it.
(booth 2926) Ask for Olivier Lauzeral. Freebie: USB stick
DESIGN DATA MANAGMENT
13.) NEW TOOL: IC Manage Views and Zero-Time Sync lets engineers get their
tools populated very quickly. Claims a "1 gigabyte, 10,000 file work-
space in 1 second to populate." Broadcom benchmark saw 2 GB in 15 sec
in ESNUG 505 #5. Allows memory-piggy tools to run immediately! Wow!
IC Manage GDP does data management for digital and custom designers to
find, modify, release and track design data through to tapeout. Now
showing even more new bug dependency management system at this DAC.
Cypress, Maxim, Nvidia, AMD, Broadcom, CSR, GlobalFoundries users.
(booth 1914) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
ClioSoft SOS does HW configuration management & rev control for full
custom Virtuoso, Laker, Pyxis, and Synopsys Custom Designer. Built-in
IP management. Can do soft integrations with in-house flows, too.
ADI, Dongbu, Huawei, Lattice, Oracle, Marvell, Toshiba, TSMC users.
(booth 2426) Ask for Karim Khalfan. Freebie: gym duffel bag
C STUFF
14.) Forte Cynthesizer synthesizes SystemC to Verilog RTL. This DAC they
will "show an entire bus-based system with complex interfaces in pin
and TLM with highly abstract coding styles, pipelined memories,
untimed and timed code, and full SystemC support." NEW will be
showing their line of SystemC IP a new tool called IFGen that
"automatically creates SystemC interface IP for line buffers."
Sony, Realtek, Samsung, Toshiba, Ricoh, Fujitsu, Sanyo uses them.
(booth 1430) Ask for Brett Cline. Freebie: beer
Calypto Catapult LP synthesizes SystemC/C/C++ to Verilog RTL -- but
it's the "only C synth tool that embeds low power analysis and
optimization from C++/SystemC." ST, Toshiba, Fujitsu, Fuji Xerox.
(booth 1226) Ask for Shawn McCloud. Freebie: M&M's and tatoos
Cadence C-to-Silicon Compiler does untimed SystemC to Verilog RTL.
"2X TAT vs. a standard RTL design flow!". Now does IP & verification.
I'd say ask for Mike McNamara, but he's been missing recently. :)
(booth 1930) Ask for Jack Erickson. Freebie: Denali party tickets
Synopsys Synfora also does some C synth but I'm unsure if they
will be showing it at this DAC.
Calypto SLEC HLS formally proves C-to-RTL functional equivalence.
No better with Forte & Cadence C tools. Renesas, ST users. SLEC RTL
is Calypto entering into RTL EC game. Competes vs. CDNS Conformal.
(booth 1226) Ask for Shawn McCloud. Freebie: M&M's and tatoos
Due to the TSMC 28 nm "problem", Cadence Virtual System Platform made
a TLM of the Zinq-7000 EPP chip -- a new family of Xilinx 28 nm chips
with a dual-core Cortex-A9 MPCore inside. "VSP lets you write SW for
the chip even though it's not available yet!" Was done 3 months before
1st samples. Runs 2X faster than the actual chip - if you can get one.
(booth 1930) Ask for Larry Melling. Freebie: Denali party tickets
Bluespec ARM Synthesizable SVP is an ARM SOC subsystem (synthesizable
models of an ARM ISS, memory, peripherals and AMBA interconnect) that
runs in emulation & simulation. Can add RTL IP. For firmware.
Fujitsu, STMicroelectronics, IBM, Intel, Hitachi, Qualcomm users.
(booth 1014) Ask for George Harper. Freebie: Bluespec books
Carbon Performance Analysis Kits are pre-built virtual prototypes and
software for ARM Cortex-A9, Cortex-A15, Cortex-A7 and big.LITTLE in
a bare metal form. Linux and Android versions shortly.
(booth 517) Ask for Bill Neifert. Freebie: none
Breker TrekSoC verifies chips with embedded processors by generating
self-verifying C test cases for multi-threaded SoCs. "We do mean,
obnoxious things to a chip to get it fixed before tapeout."
(booth 2501) Ask for Tom Anderson. Freebie: tote bags
Codasip System does rapid custom processors prototyping using CodAL
architecture description language. Generates C/C++ compiler, etc.
(booth 1006) Ask for Karel Masarik. Freebie: none
Vayavya DDGen generates device drivers in ANSI-C froma high level spec
device & software specifications - for Linux or other OSs. IP-XACT.
(booth 710) Ask for Sandeep Pendarkhar. Freebie: handshakes :)
RTL SIMULATORS
15.) Cadence Incisive does "UVM for System Verilog, SystemC, Specman 'e',
mixed-signal and low-power. 30% speed-up. Better setup and runtime
for accurate RTL low-power sims. Updated coverage analysis. New
debug Analyzer automates getting to the root cause of design bugs.
(booth 1930) Ask Adam Sherer. Freebie: Denali party tickets
Synopsys VCS and Mentor ModelSim compete here, but I'm unsure if
they're showing anything new at this DAC.
Mentor Questa Intelligent Testbench "coverage 10 to 100 times faster
than anything else." Imports System Verilog constraints. UVM.
(booth 1530) Ask for Mark Olen. Freebie: diet Coke
Cadence Specman "e" is a high-level functional testbench language.
Supports UVM. Advanced Option features like reseeding and dynamic
loading boost verification by 50%. Xilinx, Intel, HP, Infineon users.
(booth 1930) Ask Kishore Karnane. Freebie: Denali party tickets
Axiom MPSim is an "industry proven System Verilog simulator and debug
environ." Now with worldwide unlimited licensing; use it anywhere!
(booth 1625) Ask for Tarak Parikh. Freebie: magnifying glass
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
Now does constrained and coverage-driven randomization and functional
coverage by OS-VVM for VHDL designers. SynthWorks somehow involved.
(booth 2126) Ask for Jerry Kaczynski. Freebie: 4 GB USB flash drive
Amiq DVT Eclipse IDE provides IDE for design and verification
languages like "e", System Verilog, VHDL. Visual C like stuff.
Capacity. "Took one customer's 15 M lines of code, no problem."
(booth 1804) Ask for Cristian Amitroaie. Freebie: none
WinterLogic Z01X does gate and RTL fault simulation. RTL fault is
new. Competes vs. SpringSoft Certitude. NVIDIA, Freescale, Infineon.
(booth 1114) Ask for Jason Campbell. Freebie: hexbug ant
Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA tool developers. Perl interface. Parsers for UPF, PSL, EDIF.
Synopsys, Magma, Apache, EVE, SpringSoft, IBM, Infineon, NXP user
(booth 1807) Ask for Michiel Ligthart. Freebie: stuffed giraffe
3D-IC
16.) Cadence 3D-IC Co-Design System does TSV, interposer, OA, analog,
digital, package, DFT, 3D exploration, 3D floorplanning, custom edits
to the TSV and bumps. Wide I/O mem controller IP integration.
(booth 1930) Ask for Tom Whipple. Freebie: Denali party tickets
SNOOP ALERT: Mentor Olympus-SoC will give a "sneak peek into their
3D-IC cockpit that enables chip, package and board level co-design."
(booth 1530) Ask for Sudhakar Jilla. Freebie: diet Coke
Apache RedHawk-3DX analyzes the effects of simultaneous switching
noise, decoupling capacitance (intentional and intrinsic), on-chip
and off-chip (package) inductance for 3D-IC's. TSMC 28/20 nm power.
Sentinel-SSO does full-I/O bank timing and jitter analysis considering
cross-talk and power noise. Looks at I/O ring, RDL, package and PCB.
PathFinder predicts ESD failure pathways and identifies junctions and
wires likely to fail during an ESD event. CDM or HBM transints.
(booth 1813) Ask for Karan Sahni. Freebie: stuffed animals
Docea Aceplorer does power and thermal dynamic simulation and opto at
the architectural level of a chip. Tool is for SoC power architects.
It's for die, I/O, packages, etc. ST-Ericsson, Nokia, Huawei users.
(booth 1912) Ask for Philippe Garrault. Freebie: French candy
Mirabilis VisualSim Architect Power Modeler estimates power and
evaluates power management based on a model of your "thing" in their
proprietary power language language. It can "size batteries and create
finite state machines of your power conservative algorithms."
Power of things like cell phones. Boeing, Qualcomm, GM users.
(booth 1906) Ask for Robert Juliano. Freebie: candy
IP
17.) On the DAC floor this year you'll see ARM Holdings, PLC in a monster
big $$$ marketing blitz to drive home that 950 companies "from
design to manufacture and end use" are in bed with big momma ARM.
It's A-to-Z in the 8 dwarves orgy -- Apache, Atrenta, Carbon, EVE,
Jasper, SpaceStudio, VWorks, Zolcalo -- plus the EDA Big 3: Synopsys,
Mentor, Cadence all taking turns in the money shots. (booth 802)
On the technical, non-marketing-blitz side, ARM, Inc. is showing its
same old 32-bit RISC CPU, mem IP, and std cell libs. (booth 1414)
Synopsys sells Virage DW ARC 600 & 700 family of cores, plus Virage
mem IP, plus Virage InChip std cell libs that all directly compete
against ARM. Unsure if Synopsys Virage at this DAC. (booth 1130)
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 2830) Ask for Mahesh Tirupattur. Freebie: none
Arasan does digital IP cores for PHY, SD, SDIO, eMMC, ONFI and UFS.
Mixed signal MIPI, ONFI, SD, USB. (booth 701) Ask for Andy Haines.
Cambridge Analog Tech sells ultra-low power ADCs, DACs, PLLs, TDCs,
analog front ends. (booth 2804) Ask for Kush Gulati.
ChipStart aggregates other company's mem IP, analog IP, ESD IP, and
their own "system level" IP. (booth 1810) Ask for Howard Pakosh.
Cortus SA sells ultra low power 32-bit microcontoller IP cores; four
types: RISC to floating point. (booth 304) Ask Michael Chapman.
Dolphin Integration sells CMOS IP for audo, std cell libs, memories,
power regulators, 8051's. (booth 706) Ask for Michel Depeyrot.
Ensilica Ltd. sells configurable 16/32-bit eSi-RISC, eSi-Crypto,
eSi-Comms, eSi-Connect. (booth 2827) Ask for Ian Lankshear.
Mixel sells "Legorithmic" mixed-signal mobile IP like SERDES, MIPI
D-PHY, LVDS, and M-PHYSM. (booth 2719) Ask for Ashraf Takla.
PLDA sells IP for SuperSpeed USB, PCI Express, PCI-X, 10Gb TCPIP
for ASICs and FPGAs. (booth 2714) Ask for Jean-Yves Brena.
Posedge sells 802.11n/ac, FLASH, Security, and SD IP. (booth 2802)
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". (booth 2817) Ask for Micke Wersall.
Tela Innovations sells libs for "restricted design rules", double
patterns, FinFET 32/14 nm. (booth 704) Ask for Scott Becker.
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180 nm to 28 nm. (booth 2726) As for John Maneatis.
Uniquify sells DDR Memory Controller subsystem IP. Has dynamic
self-calibrating logic. (booth 1902) Ask for Mahesh Gopalan.
Forte CellMath Floating Point IP competes vs. Synopsys Designware on
high-level math functions like: IEEE rounded functions: add, mul, div,
and sqrt; Non-IEEE rounded functions: add, mul, dot-product; Single
input combinational functions: recip, recip-sqrt, log, exp, sin, cos,
and sqrt. Wide range of precision, rounding modes, and bitwidths.
(booth 1430) Ask for Nick Atkinson. Freebie: beer
SEE YOU AT DAC
18.) If you're at DAC and you want to hook up to talk trash, on DAC Sunday
I'll be at Gary Smith's pre-DAC talk at:
Sunday 7:00-8:00 pm, Marriott Hotel, Salon 6
and on DAC Monday, I'll be moderating my DAC Troublemakers Panel at:
Monday, 3:00-4:00 pm, DAC meeting room #256
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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