!!! "It's not a BUG, 
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\ - / INDUSTRY GADFLY: "Maybe the Third Time is a Charm?"
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by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
I grinned to myself while reading that rah-rah press release. "Synopsys, a
world leader in blah blah blah..." had acquired Virtio HW/SW co-design for
an undisclosed price. (I later heard it was a $15 million cash deal.)
Anyway, my initial response to the Virtio news was: "Maybe the third time
around will be the charm for Synopsys here. Maybe."
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One of the big advantages of having lived through EDA history as it happened
is that you don't get sucked into the false enthusiasm of a press release
that's pimping an olde idea as a "new" approach. In this case, it's renaming
good olde fashioned HW/SW co-design as a "virtual prototyping platform".
Since the dawn of chip design, the software/firmware guys have always been
howling "WHEN CAN YOU GET THE PROTOTYPE DONE SO WE CAN TEST OUR SOFTWARE?!!"
It wasn't pretty. Not only was your management on your ass about getting the
chip done; the SW guys were agreeing with them! Something had to be done.
The first cut toward fixing this mess came with the birth HW/SW co-design.
It was when the HW guys gave the firmware guys a Verilog model of the chip
with a PLI interface. This shut up those surly firmware guys because they
could now run their C SW through the PLI to interact directly with your chip.
A clever little start-up called Logic Modeling Corp (LMC) came along offering
12,000 software IC models -- which worked nicely in this happy Verilog PLI
world -- so nicely that in 1993 Synopsys bought them for $116 million.
LMC is what I call The First Synopsys Foray Into HW/SW Co-design.
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Life was good. Now the biggest complaint we had with the EDA vendors was how
much faster could they get Verilog to run. Compiled code Chronologic VCS was
born, greatly embarrassing Cadence's dog slow interpreted Verilog-XL. A sly
Viewlogic then acquired Chronologic in 1994 for around $26 million; beating
out Synopsys to the punch. Then in a 1995 lawsuit the Chronologic founding
fathers tried unsuccessfully to get a divorce from Viewlogic.
Smelling the blood and probably still pissed off about not getting VCS the
first time around, in 1997 Synopsys bought all of Viewlogic for $540 million.
Hungry mostly for ASIC tools, the Synopsys Borg assimulated Chronologic VCS,
Quad Motive, Sunrise TestGen, and in an odd impulse, Eagle Eagle-i. It then
spat out the remaining shards of PCB and schematic tools as "Innoveda".
Eagle Eagle-i, though not what I suspect was a primary acquisition target at
the time, is what I call The Second Synopsys Foray Into HW/SW Co-design.
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While LMC was really just a library of SW models that eventually got absorbed
into the Synopsys DesignWare offering, Eagle-i was a true, bonafide HW/SW
co-design tool. It directly competed against Mentor Seamless and (Cadence)
CoWare SPW/N2C/ConvergenSC. The problem was that it sucked as a tool. The
first hint at Eagle-i's suckage was:
"We saw a real need for HW/SW co-design. We had the Mentor Seamless
and Synopsys Eagle-i guys come in to pitch their tools. As a test,
we set up two teams in house using both tools. Each team consisted
of two HW engineers and one SW engineer. For a few weeks, they used
either Eagle-i or Seamless to develope a PowerPC based testbench. We
then had each team switch to using the other tool. In the end, the
two tools were very close but our conclusion was to choose Mentor
Seamless because it was more mature, it allowed granular and dynamic
optimization control of memories, they had working Denali memory
models (Synopsys MemPro was yet unworkable), and it ran on HPUX
(Eaglei only runs on Suns and we're a HP house.) Price was a
non-issue because they were so close."
- Hugh Blair of Honeywell Space Systems (ESNUG 329 #18)
"Synopsys Eagle-i. Mentor has taken the correct approach by purchasing
Microtech a few years back. Will Synopsys buy Wind River? I don't
think so. Will Eagle-i prevail in the marketplace? Not without such
an acquisition. Transmodeling - a cool graphical front end to manage
C/RTL distributed simulations, etc. Cadence/Synopsys or someone needs
to buy them."
- an anon EDA salesman (DAC 00 #6)
Then it got not so subtle:
"We got an eval copy of Eagle-i in our company. Eagle-i ran so slow,
it was useless for our software guys. They didn't like it at all.
Now, in our design process we write Verilog. When our SW guys need
what we're working on for their simulations, we tranlate it over
to C, bottom up. SystemC works, but it's ugly. It's a solution in
search of a problem we don't have. We'd rather do our hardware
design in Verilog and then translate it to C at the last minute when
it's needed by the SW guys. Verilog is much more graceful for
hardware design. Translating it to C is easy.
I don't think HW/SW co-design is a driving force in design today.
HW/SW co-design's approach is to blurr the line between what's
going to be done in HW and what's going to be done in SW. In every
situation I've seen, everyone knows where the SW ends and the HW
begins. System designers clear know how to partition HW and SW
from the very beginning of their projects. You don't need HW/SW
co-design tools like Eagle-i."
- Martin Gravenstein of TDK Semiconductor (SNUG 01 #26)
And 3 months later, Synopsys pulled Eagle-i from the market:
"We were informed, shortly after purchasing the tool, that Eagle-i
is no longer being offered to new customers. Nor are new processor
models being developed, although Synopsys claims that current
customers will be supported.
The product appears to be well on it's way to end-of-life."
- An Anon Engineer (DAC 01 #10)
Although I can't remember any user reporting that Synopsys sent them an
end-of-life notice for Eagle-i, I presume the tool is long dead because
it's nowhere on the current Synopsys.com product listings web page.
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So now that you understand my "third-time-around-might-be-the-charm" reaction
to this Synopsys Virtio acquisition, to be fair and complete, there's a good
part of me that thinks it might *not* be the charm. I'm not going to belabor
the point here, instead I'll just point you to 2 years worth of survey data
in DVcon 04 #12 and DVcon 05 #16 and let that do the talking.
In the end, there's only 3 ways the Virtio purchase can go:
1.) The world has changed and Virtio is the right tool at the right
place at the right time with the users -- like what I discovered
when I wrote that First Encounter "Shock and Awe" column.
2.) For some inexplicable reason, Virtio goes crypto ambiguous where
the Synopsys employees gush about how great it is, but its users
are Da Vinci Code elusive like IC Compiler in SNUG 05 #14.
3.) After a few marketing pushes, press releases, mentions in Aart's
speeches, etc. -- customer lack of interest causes Virtio to die
like the silent death of Behavioral Compiler in SNUG 02 #12.
On the outside looking in, my gut says it's going to be 1 or 3 -- but that's
just my gut speaking. When it comes to real life, I'm not a big believer in
dodgy crypto ambiguous Da Vinci Code conspiracies.
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John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
or (508) 429-4357.
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