I was happy to see on the TSMC and UMC web sites last week reports claiming
that they both got the Cadence (Simplex) X Architecture working at 65 nm.

Like most engineers, I've been one of the quiet fence sitters waiting to see
if this new type of layout was actually going to work or not.  What's worst
was the rumor that I had heard right after Cadence had acquired Simplex in
2002, that the X Initiative was a bogus technology crafted to artificially
pump up the $300 million Simplex sale price.

It was a nasty thing.  I couldn't ask Penny Herscher, the CEO of Simplex,
about it because it was a "when-are-you-going-to-stop-beating-your-husband"
type of question.  No matter how she'd answer, she'd be seen as wrong.  And
I'd be wrong to stupidly ask it.  I respected Penny too much to fall for
this trap rumor, so I just sat back and let time determine the truth here.
Sure enough, over the years the X Initiative marched on; and even after Penny
left Cadence, the X Initiative still marched on!

I'm glad I didn't pursue that false rumor then, but I still have my doubts
about the so-called "benefits" the X Architecture is claiming.  From their
own "benefits" web page:

    "The X Architecture's pervasive use of diagonal routing reduces
     wirelength by an average of 20 percent and via count on diagonal
     layers by an average of 30 percent"

For those who don't know, in the X Architecture, m4 and m5 are rotated 45
degrees to enable diagonal routes (as opposed to purely Manhattan routing.)
Let's say you have two points you want to connect: one point at 0,0 and the
other point at 1,1.  In Manhattan routing, the net will be 1 + 1 = 2 units
long.  One leg of the net goes from 0,0 to 0,1 and the second leg goes from
0,1 to 1,1.  In diagonal routing, the net goes directly from 0,0 to 1,1, so
it will be only sqrt(1 + 1) = 1.4 units long = a savings of 29 percent.

That 29 percent savings for diagonal routes is a "best case" situation that
only comes about if all your points are perfectly diagonal to each other.
That is, a diagonal route saves nothing if you're routing from 0,0 to any
of 0,1 or 0,45 or 1,0 or 23,0 or 0,-12 or any points that are *not* diagonal
to 0,0.  In this "worst case" the savings are 0 percent.

So assuming a random distribution of routing points, you'll get an overall
of (29 + 0)/2 = 14.5 percent net length savings using the X Architecture.

Therefore in my book, any savings claims above 14.5 percent are the results
of cooked benchmarks where they cherry picked non-random routing points to
make the X Architecture look better than it is; or its the relative measure
of the inefficiencies of the various routing software tool(s) used.  In other
words, their 20% wire reduction claim is notably inflated, but it's at least
somewhere in the expected 14.5% ballpark.  It's what EDA marketing people do.

On the other hand, concerning that 30% via count reduction claim, assuming
they're comparing gridless rotes, other than the one rare 45 degree case, I
can't even concoct *one* single point-to-point net where the diagonal route
has fewer vias than its Manhattan route.  (Try it & you'll see what I mean.)
So I'll have to call bullshit on their 30% via count reduction claim.

Lying aside, a 14.5% average wirelength reduction is worth checking out.

I guess the biggest truthful indicator that the X Architecture is still stuck
in debug mode is that so far there's only been one company, ATI, who has made
one non-test chip in it.  (And judging from the "collaboration" tone of their
June 2005 press release, I have some question as to how much of that chip was
done at ATI and how much was done at Cadence.  Over the years I've found that
in EDA speak the word "collaboration" is just another polite euphemism for
"Oh-my-God-we-are-so-drowning-in-bugs-here".)  Also this ATI X chip was done
12 months ago.  What this tells me is there are obviously some messy gotchas
we've not been told about, otherwise ATI would have gone great guns into the
X Architecture by now.  Since ATI hasn't, plus the fact that last month's
Cadence/Teranetics X press release swam with the "collaboration" word, it's
pretty clear that the X Architecture is still not ready to fly on its own yet.

In short, the X Architecture is still in "taxicab mode"; you can't really use
it without renting the car plus hiring the driver from Cadence to drive it.
But when it is finally debugged, that 14.5% wirelength reduction will be
nothing to sneeze at.  Until then, expect more "collaboration".  :)