Editor's Note: Hey, folks, I'd like to publically apologise for one error
in my "Magma Desperados" column earlier this week. I wrote:
"And those supposed $80 million in bookings Rajeev has? In his S-1,
it's really just $6.9 million deferred revenue. Oops. Ouch."
It turns out that deferred revenue and bookings are two very different
fiscal creatures. (See Item 1 below.) But I stand behind everything
else I wrote in that column. Magma has burned through $87 million for
just $8.4 million in revenues since it's founding. Two different sources
confirmed Magma had talked with Cadence, Synopsys, Mentor, and Avanti
about a possible buyout. Gary Smith did say he's heard that Blast Fusion
doesn't work on designs over 200 Mhz. Jessica Kourakos did say she
thought this was a pre-mature IPO and Jay Vleeschhouwer did comment about
Magma's $3 million a month burn rate and Magma's appetite for cash. And
I did find only 3 tape-outs by Magma customers 6 months ago.
But, in order to do the right thing, I've decided to do another tape-out
count of Magma designs. Instead of holding Magma to a count they had
6 months ago, I feel it does *everyone* a service to know where Magma
is with user tape-outs *today*. So, if you've done a tape-out using
Magma, please get in touch with me within the next 5 days. Thanks.
- John Cooley
the ESNUG guy
( ESNUG 373 Subjects ) ------------------------------------------ [06/07/01]
Item 1 : Cooley Spanked For Confusing Magma Bookings & "Deferred Revenue"
Item 2 : One User's Embarassing SystemC vs. SuperLog vs. Verilog Benchmark
Item 3 : ( ESNUG 372 #2 ) Processors, Motherboards, Version Of Linux We Use
Item 4 : ( ESNUG 372 #13 ) Horse Hockey! Avanti Holds Customers Hostage!
Item 5 : ( ESNUG 372 #8 ) User Pissed About Late EDA Support For VHDL'93
Item 6 : Help! DC 99.10-6 Keeps Putting 2 Inverters In My Reset Paths!
Item 7 : ( ESNUG 372 #3 ) PhysOpt Can't Handle Designs With 100+ SRAMS
Item 8 : One Designer's Sun Solaris 7.0 To Red Hat 6.2 Linux PC Benchmark
Item 9 : ( ESNUG 370 #15 ) Mentor's FormalPro Is *Very* Memory Efficient
Item 10 : ( ESNUG 371 #1 ) PhysOpt's Placement Of Clock Gating Cells
Item 11 : What About Rivals To Simplex In Electromigration Analysis Tools?
Item 12 : Zimmer's vim Syntax File For PrimeTime Is In DeepChip "Downloads"
Item 13 : User Pissed That DC 00.11-SP1 Suddenly Doesn't Have auto_ungroup!
Item 14 : Wanting DC To E-mail Every Hour Instead Of In Between DC Commands
Item 15 : Hey? Wasn't SystemC Going To Replace HDLs with free C Compilers??
Item 16 : ( ESNUG 372 #4 ) PhysOpt Rival Agrees Congestion Is Pain In Ass
Item 17 : ( ESNUG 372 #7 ) More React To The Avanti/Cadence Lawsuit New
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 373 Item 1 ) -------------------------------------------- [06/07/01]
Subject: Cooley Spanked For Confusing Magma Bookings & "Deferred Revenue"
> Three months ago, around DATE, Synopsys claimed to have $56 million in
> physical synthesis bookings, Cadence claimed $110 million, and Magma
> claimed $80 million in bookings. Something seemed odd here. I had done
> a physical synthesis tape-out census 3 months prior, and Synopsys had 65
> vs. Cadence's 7 vs. Magma's 3 tape-outs. Synopsys was winning by a 10X
> to 20X lead over Cadence and Magma -- yet Synopsys bookings were roughly
> half Cadence's and Magma's bookings. Huh?
>
> - from "The Magma Desperados"
From: Hank Walker <walker@cs.tamu.edu>
As usual, extremely interesting, John. Presumably Cadence is counting a
bunch of regular P&R revenue.
Do you have any update on Monterey? They had the most technically
challenging and interesting approach to an academic like myself. But I've
lost track of whether Monterey has ever shown a stable product that could
be run without FAEs in taxicab mode.
- Hank Walker
Texas A&M University College Station, TX
---- ---- ---- ---- ---- ---- ----
From: Jay Vleeschhouwer <Jay_Vleeschhouwer@ml.com>
Hi, John,
I found your article on Magma interesting, but you made two errors in it.
One error was minor. The other was much more serious.
First, the minor error. It's important for you to to understand the
distinction between "bookings", "deferred revenues", and "revenues" in
the Magma S-1 filing. Bookings refer to Magma's customer orders coming in
the door for their technology and services. How those bookings are
recognized as actual revenues on their income statement depends on Magma's
revenue recognition model and its obligations to its customers. Some or
all of Magma's bookings are recognized "ratably" over the (typically 3
year) life of their sales contract with a customer. Therefore, on average,
they should see only 1/12th of their total bookings per quarter as revenue;
so the timing of the orders - earlier or later in the fiscal year - will
affect how much can be shown a revenues over the course of the year.
Deferred revenue is an amount that depends on the value of the "undelivered
elements" of a customer agreement, such as upgrades or services. Deferred
revenues are distinct from revenues, along with costs and expenses,
operating profits (or in Magma's case, losses), interest income, and so on.
You can't assume that $80 million in Magma bookings appears as $80 million
in deferred revenue on their S-1. You can't use these financial terms
interchangeably.
The more egregious error in your article was that you you got 1/13th of my
name wrong! I'm a VleeschhouWer, not a VleeschhouSer!!! The former is an
honorable Dutch family name; the latter - well, never mind. What if you
had gotten 1/13th of your tape-out survey wrong?
Anyway, see you at DAC.
- Jay Vleeschhouwer
Merrill Lynch New York, NY
P.S. In any event it's my understanding that for this last fiscal year,
Magma's bookings came in below expectations, though they were well
above their March 2000 fiscal year orders.
---- ---- ---- ---- ---- ---- ----
From: Bill Frerichs <BFrerichs@dadco.com>
Hi, John,
Accounting buffs will point out to you that "deferred revenue" is the
billed components of term software licenses. It does not include
unbilled components. For example, if an EDA company were to sell a three
year deal but only bill for the first three months, the unbilled portion
would go into backlog, but not deferred revenue.
- Bill Frerichs,
Financial Analyst
D.A. Davidson & Co.
---- ---- ---- ---- ---- ---- ----
Editor's Note: Again I wish to apologize for that Deferred Revenue
vs. Bookings error in that column. In my mind, Rajeev's $80 million
bookings translated to $27 million per year Deferred Revenue. I've now
learned that isn't the way the accounting works. Sorry. - John
---- ---- ---- ---- ---- ---- ----
From: <GO_Stock_Boy@yahoo.com>
Do the simple numbers from S-1
90 Million or so in VC investment
80 Million already spent (loss)
10 Million left
3 Million/month burn rate after revenues (maybe 2M with layoffs and
increased revenues)
OK - maybe some minor line of credit ..
3-5 months left to live without additional capital
= Avoid bankruptcy IPO !!
- GO_Stock_Boy (msg 9528 on the Yahoo CDN chat board)
---- ---- ---- ---- ---- ---- ----
> "At the end of the day, it's tape-outs and follow-on customer orders are
> what count." concluded Jessica. And you know what? She's right.
From: [ Elvis Lives! ]
Hello Mr. Cooley,
I have not used Magma or Synopsys PhysOpt myself yet. It something that you
start to use and find that either you love it or hate it! But, I agree,
it's the number of right-first-time tape-outs counts.
> Magma's tools are hurting, too. From what Gary Smith of Dataquest and I
> have heard from customers, Blast Fusion can only handle blocks, not full
> designs. Magma's struggling with synthesis and Gary says he's heard that
> Blast Fusion doesn't work on designs over 200 Mhz.
Your chain of narration is weak, you said, Gary Smith heard from so and so,
and you heard from Gary, so who did Gary hear from in the first place?
Anonymous.
- [ Elvis Lives! ]
---- ---- ---- ---- ---- ---- ----
From: [ The Man In The Iron Mask ]
John,
I'd love to comment (especially since I'm a former employee) but I cannot
legally do so... if you know what I mean. As always -> ANONYMOUS
- [ The Man In The Iron Mask ]
---- ---- ---- ---- ---- ---- ----
From: [ My Lips Are Sealed ]
John,
I agree with the jist of your column. Any word on surplus Magma Hawaiian
shirts hitting the vintage clothing market soon? Anon.
- [ My Lips Are Sealed ]
---- ---- ---- ---- ---- ---- ----
From: [ Death Before Dishonor ]
John,
I don't work for any of these EDA companies, but we could use any of them.
I don't have a bias, I just want working chips.
IMHO, you have gone over the edge on this one. Telling the facts is good,
but picking out as many negative things a possible and presenting those goes
over the edge. Spreading rumors and options without facts is very low. If
you don't have facts, don't write it. If they are dieing, let them die in
peace. Please don't spiral into the blackhole of EDA underground marketing.
Please keep my name and company anonymous. Thanks.
- [ Death Before Dishonor ]
---- ---- ---- ---- ---- ---- ----
From: Shankar Hemmady <hemmady@pharmquest.com>
Hi John,
You are blunt!
BTW, even S-1 filings do not always tell the truth. Sometimes, S-1s are
well done accounting gimmicks. For instance, many B2C and B2B outfits
booked as revenues all that was transacted on their exchanges. They even
added the UPS or FedEx costs as revenues, even if it was credited to
customers! That is, until the SEC got tough with them and started asking
them to re-write revenues only to what the exchanges had title to...
IMHO, although Magma has burned so much cash -- in dot.com fashion -- I
suspect Rajeev has a lot more to show than your typical eCommerce site.
You've got to give credit to all of them EDA companies. Most of them are
real, not virtual, companies! More real than the dot.gones.
- Shankar Hemmady, CEO
PharmQuest Corporation
(and ex-EDA guy)
( ESNUG 373 Item 2 ) -------------------------------------------- [06/07/01]
From: [ The Emperor Has No Clothes ]
Subject: One User's Embarassing SystemC vs. SuperLog vs. Verilog Benchmark
Hi John.
Please keep me anonymous.
I have been using Superlog at our company and I am getting quite impressed
it. However I couldn't ignore the hype about SystemC, so I downloaded the
latest version from their ".org" website and made a quick benchmark based
on your old Verilog vs. VHDL design contest from a few years back. As
you did in that contest, I created two up-by-3/down-by-5 9-bit loadable
counters with parity -- one in SystemC and the other in SuperLog.
My SuperLog code:
module upDown ( input bit clk, up, down, bit[8:0] data_in,
output bit parity_out, carry_out, borrow_out,
bit[8:0] count_out );
bit[9:0] cnt_up, cnt_dn;
bit[8:0] count_nxt;
bit load;
always @(posedge clk) begin
cnt_dn = count_out - 5;
cnt_up = count_out + 3;
load = 1;
case ({up,down})
0: count_nxt = data_in;
1: count_nxt = cnt_dn;
2: count_nxt = cnt_up;
3: load = 0;
endcase
if(load) begin
parity_out <= ^count_nxt;
carry_out <= up & cnt_up[9];
borrow_out <= down & cnt_dn[9];
count_out <= count_nxt;
end
end
endmodule
My SystemC code (header):
#ifndef systemc_upDown_h_INCLUDED
#define systemc_upDown_h_INCLUDED
SC_MODULE(upDown)
{
sc_in clk;
sc_in up;
sc_in down;
sc_in > data_in;
sc_out parity_out;
sc_out carry_out;
sc_out borrow_out;
sc_out > count_out;
sc_uint<9> save_count_out;
sc_uint<10> cnt_up, cnt_dn;
sc_uint<9> count_nxt;
sc_uint<1> load;
SC_CTOR(upDown)
{
SC_METHOD(entry);
sensitive_pos(clk);
}
void entry();
};
#endif
My SystemC (body)
#include "systemc.h"
#include "upDown.h++"
void upDown::entry()
{
cnt_dn = save_count_out - 5;
cnt_up = save_count_out + 3;
load = 1;
if (up == 0 && down == 0)
count_nxt = data_in;
else if (up == 0 && down == 1)
count_nxt = cnt_dn;
else if (up == 1 && down == 0)
count_nxt = cnt_up;
else if (up == 1 && down == 1)
load = 0;
if (load) {
sc_bool_vector tmp(9);
tmp = (sc_bv<9>) count_nxt;
save_count_out = count_nxt;
parity_out.write(tmp.xor_reduce());
carry_out.write(up & cnt_up[9]);
borrow_out.write(down & cnt_dn[9]);
count_out.write( (sc_bv<9>) tmp);
}
}
Considering SystemC is compiled C++ code and Superlog is a parsed and
interpreted language, the results were quite astonishing.
Around these design units I prepared a testbench in SuperLog and SystemC,
for 1 and for 10 instances of the counter, running for 1 million clock
cycles. What I obtained on a Sun at 750MHz (in cpu sec):
counter
instances: 1x 10x
---------- -------- ---------
SystemC 13.3 sec 114.4 sec
SuperLog 2.9 12.2
The SystemC results are abysmal. Worse, they scale badly as the number
of instances linearly increased. The cpu times were measured by the Unix
"time" command, so they include the initial parse time of the SuperLog.
They do not include the time taken by the C++ compiler to compile the
SystemC code. This was an additional 20 seconds. In fact, SystemC was
even beaten by old Verilog-XL on the original Verilog RTL version of the
benchmark. Verilog-XL required 101.5 sec for the 10x benchmark, with XL
simulating 0,1,X,Z reg types and SystemC abstract 0,1 sc_bv types.
So what is this hype about SystemC as the future language of design!?!
Speed - not satisfied here - but it is a main issue for system
design for my work.
Readability - much more verbose than Verilog and separating facets of
the design across 2 files doesn't help. C language
issues obscure the system/hardware/RTL design.
Quality - only C++ compiler syntax traps are available to capture
errors in the design semantics. Like trying to write a
compiled program and relying on the linker to hint at program
bugs. Run time traps are used to indicate some semantic
errors in the design - when bad statements are reached.
Superlog, like other HDLs, analyses the design before the
simulation starts and tells you your design errors, rather
than complaining about the syntax of the native language
simulating the design.
Software CoDesign - SystemC should have an advantage as it is running
as native C++. However SuperLog can transparently
invoke C or Verilog or shareable libraries of
compiled C, C++ and other langauges aswell, without
using a PLI unlike other HDL simulators.
IP - seems there is a lot of hype that models for IP vending and
System-on-a-Chip could be tendered in systemC. If that happens
then SuperLog is OK, since it can invoke the systemC C++ model.
However the majority of IP worldwide is Verilog, and it can also
be invoked directly from SuperLog. The converse is NOT true for
SystemC.
Freeware - SystemC is free on the net - but beware of the adage "pay
now or pay later" since apart from the overheads of using
this package in its raw form, SystemC would require
considerable investment to generate a design. With SuperLog
a design can be extracted that is consumable by DC for
synthesis. For systemC there seems to be a lot of effort to
get Behavioral Compiler as the synthesis tool. BC high level
synthesis is not necessarily good for design.
I think SystemC is the free bait to hook users into an expensive toolset.
- [ The Emperor Has No Clothes ]
( ESNUG 373 Item 3 ) -------------------------------------------- [06/07/01]
Subject: ( ESNUG 372 #2 ) Processors, Motherboards, Version Of Linux We Use
> We're _exclusively_ a Sun (1000's of 'em) house, a decree from on high,
> because [ reason deleted to preserve anonymity]. Moving to Linux/PC
> hardware is a very hot political potato at this company. I don't want
> to attract any heat. Just looking for some information.
>
> I hope you can understand my position and keep me anonymous.
>
> I'm interested in what Linux hardware people are running:
>
> 1.) Which Processors, motherboards, amount of memory, are you using?
> 2.) Which flavor of Linux are they running?
> 3.) Single/multi-processor boxes?
>
> Can you organise a poll, John?
>
> - [ Chicken Little ]
From: Dan Moritz <dmoritz@lsil.com>
John,
We're using Dell PowerEdge Dual P3-800 running Redhat 6.1 and IBM Thinkpad
T20 Single P3-700 running Redhat 7.1.
- Dan Moritz
LSI Logic Bloomington, MN
---- ---- ---- ---- ---- ---- ----
From: Tony Laundrie <atl@sgi.com>
John,
Our Physical Design group is using a collection of about a dozen SGI 1200
systems, 2 CPU, 700 MHz, 512-1536 MBytes RAM each, mostly running PhysOpt
jobs. Red Hat Linux release 6.2. Great performers over our Sun machines.
Some people also have Linux workstations on their desktop, running Cadence
DFII on a remote Sun and displaying back. We are anxiously awaiting
Cadence support for 24-bit graphics display to Linux machines (coming in
a few months). In the mean time, we use 8-bit mode for VNC or X to run
Cadence DFII.
- Tony Laundrie
SGI
---- ---- ---- ---- ---- ---- ----
From: Kris Monsen <monsen@mobilygen.com>
Hi, John,
Other than a couple of Sun's for tools that don't yet run under Linux, all
of our engineering team use:
RedHat Linux 6.2
ASUS P3V4X Motherboard
733MHz-1GHz P3 (single processor)
256MB - 512MB PC133 Memory (actually, one has 1GB)
always lots of swap space (usually 1GB)
We've got about a dozen such boxes (hey, we're a startup company), and we've
had very few problems with them (uptimes of months). We run VCS, Design
Compiler, Surelint, etc. on them (mostly front-end stuff).
- Kris Monsen
Mobilygen Corp. Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: [ Major Tom To Ground Control ]
John, anon please.
We use: Dell hardware 2550 server 2GB of memory dual 1Ghz PIII Xeon
processors. Redhat 6.2, 7.0 and 7.1
Dell hardware CPxJ 650Mhz Latitude Desktop Redhat 6.1, 6.2, 7.0 and 7.1
(still debugging it)
The Synopsys tools that I've used work best right now on 6.2. Linux 7.0
is a 'red flag' due to C compiler issues (which can be resolved by
downloading the latest rpms for the C complier and libs) and 7.1 support
is still a bit early. (Although prelim tests seem to indicate that some
things will run.
Biggest issue is in GUI's. Linux 6.2 is the only RedHat version officially
'blessed' to use with VCS, Covermeter, Vera, Designware and soon Scirocco,
and Design Compiler.
I would LOVE to get Mac OS X support!
- [ Major Tom To Ground Control ]
---- ---- ---- ---- ---- ---- ----
From: Rudolf Usselmann <rudi@asics.ws>
John,
Here is what I use in my (only 4) compute servers:
- ASUS motherboards (various)
- One AMD Thunderbird CPU per system, 1.33ghz
- 512 MB of memory (seems an overkill, my simulations up to 500K gates
tend to never even reach 256Mb).
- everything else is basic cheap stuff: D-Link 100BT Ethernet, the
cheapest video card I can find like Creative Graphics Blaster, or
GE Force 2 MX (a bit more complex to set up under Linux), etc.
- I started with Mandrake, switched to RedHat, just upgraded to 7.1
- Tools: Cadence NC-Verilog
These systems run me about $1200.
- Rudolf Usselmann
( ESNUG 373 Item 4 ) -------------------------------------------- [06/07/01]
Subject: ( ESNUG 372 #13 ) Horse Hockey! Avanti Holds Customers Hostage!
> Lately I have been reading in ESNUG users having trouble interfacing to
> Avanti tools. Interfacing any two tools is difficult, but I do not think
> that interfacing to Avanti is any harder than to other tools. ... The
> PDEF3 translator worked great for me on a recent tapeout using Synopsys
> PhysOpt with Avanti Apollo. ... If you need more data from Milkyway, you
> can extract it using Scheme. When someone needed a PDEF3 translator,
> they just wrote one. I see no unsurmountable problems here.
>
> - John McGehee
> Voom, Inc. Los Altos, CA
From: Dale Lomelino <dale.lomelino@philips.com>
Hi John,
I appreciate McGehee's thoughts, but I believe we have different
perspectives on the subject. My job is NOT to develop flows, but to
tape-out working silicon. Yes, I realize that it is possible to write
Scheme scripts to delve into the Avanti Milkyway database (like *Synopsys*
did with dumpPDEF3.scm, dumpPLIB.scm, and readPDEF3.scm), but my
observation was that Avanti does not actively support "standard" design
formats like LEF/DEF or PDEF.
What caused my original snide comments was that credit for the Scheme
scripts had mistakenly been given to Avanti -- instead of Synopsys. My
point was that Synopsys is making an effort to "play well with other EDA
vendors." I have not seen similar support coming from Avanti.
Here's a simple example. When you look for Avanti functions that support
LEF, you get:
functions "Lef"
auLefIn
#t
This omits the "getClash" commands, which one might have guessed should
have been named "auLefOut". Perhaps the "Clash" predicted in the command
name is the Cadence lawsuit that's in today's news? ;-)
- Dale Lomelino
Philips Semiconductors Cary, NC
( ESNUG 373 Item 5 ) -------------------------------------------- [06/07/01]
Subject: ( ESNUG 372 #8 ) User Pissed About Late EDA Support For VHDL'93
> ... In addition, VHDL93 support (same subset as DC) will be available
> with the Formality 2001.08 release in August. ...
>
> - [ A Formality CAE ]
From: Greg Bell <gbell@magisnetworks.com>
John,
Its 2001... WHAT'S THE HURRY IN SUPPORTING 1993 EXTENSIONS TO VHDL????
Am I going to have to wait until 2008 for Verilog2000 support from vendors?
This kind of snail's pace "innovation" in the EDA industry is what makes me
fantasize about jumping tracks and becoming a software engineer - healthy
competition means they never have to put up with this type of crap. Every
time I see the features and stability of the tools they get to use, I'm just
amazed at how poor our ASIC tools are in comparision.
- Greg Bell
Magis Networks
( ESNUG 373 Item 6 ) -------------------------------------------- [06/07/01]
From: Rajendra Marulkar <Rajendra.Marulkar@InviscidNetworks.com>
Subject: Help! DC 99.10-6 Keeps Putting 2 Inverters In My Reset Paths!
Hello, John,
I am using DC 99.10-6. We are doing a million gate bottom up synthesis.
We are planning to use CTS both for the reset and clock networks. We put
following constraints on clk and reset:
set_drive 0 clock_grp
set_dont_touch_network clock_grp
set_drive 0 rst_l
set_dont_touch_network rst_l
But still DC puts 2 inverters in the reset path. Also there is no logic
between reset and flop in my design. Is there any issue with this version
of DC? (Interestingly it doesn't put any buffers/inverters on the clock
network path though its treated exactly like reset.)
- Rajendra Marulkar
Marconi Communications
( ESNUG 373 Item 7 ) -------------------------------------------- [06/07/01]
Subject: ( ESNUG 372 #3 ) PhysOpt Can't Handle Designs With 100+ SRAMS
> There are a lot of SRAM macros (over 100) in our design, and around 20%
> of die size is used for standard cells. Does anyone has experience with
> PhysOpt to optimize the design like ours?
>
> - Qi Chen
> Gennum Corp.
From: Qi Chen <qchen@gennum.com>
Hi, John,
We don't have a copy of PhysOpt. I have experience with PhysOpt from my
previous company.
Here is the information I got from Synopsys about this issue:
1) The current version of PhysOpt can not handle macro placement.
2) Synopsys will include the macro placement in future version.
(I don't know when.)
Here are my thoughts: In order to get good macro placement, the designers
should understand the architecture level design and signal flow in the
chip. If the critical paths are localized, a manual job is doable. If
the critical paths are global control signals, the macro placement will be
a tough job.
I was told Magma could perform macro placement, but I have not tried it yet.
I fear that a tool which can perform 100+ macros placement isn't available
in the current market.
- Qi Chen
Gennum Corp.
( ESNUG 373 Item 8 ) -------------------------------------------- [06/07/01]
From: Scott Evans <scott@sonicsinc.com>
Subject: One Designer's Sun Solaris 7.0 To Red Hat 6.2 Linux PC Benchmark
Hi, John,
To add to your latest SNUG information on Sun's vs Linux, for me, the issue
came up when I asked the SGI and HP people at the recent SNUG'01 conference
about such data. They said I could see a significant speed-up based on the
speed of the processor. Since then I've done a couple of small comparisons
to get an idea if they really knew what they were talking about.
The systems I used were a Sun Enterprise 420 (4x450MHz processor) running
Solaris 7 and a VA Linux Systems 2200 Series 2U Linux Server (2x800MHz
Pentium III) running Red Hat Linux 6.2. A direct MHz speed comparison has
the PC running 1.8x Mhz of the Sun.
The following table lists the values reported back from the Unix "time"
command on a couple of small synthesis jobs.
job cpu Sun cpu PC ratio
1 3059 sec 1715 sec 1.8x
2 652 347 1.9x
Seems to track the MHz scale fairly nicely. I haven't tried anything that
would push the memory limitations, etc., but at least for reasonably sized
blocks of logic, seems like this is a no-brainer.
- Scott Evans
Sonics Inc. Mountain View, CA
( ESNUG 373 Item 9 ) -------------------------------------------- [06/07/01]
Subject: ( ESNUG 370 #15 ) Mentor's FormalPro Is *Very* Memory Efficient
> Concerning the comments you had about Chrysalis, Formality, and Verplex:
> I was just wondering if anybody commented about Mentor's FormalPro or
> Innologic Systems' ESV-CV? (If there were no comments, I'd be interested
> in what users think about these two tools now.)
>
> - Albin Takami
> Nokia Mobile Phones San Diego, CA
From: Raimund Soenning <raimund.soenning@philips.com>
Hi, John,
We did an eval of 3 formal verification tools (Avanti Design Verifyer,
Verplex Tuxedo, Mentor FormalPro) in January. Mentor at that time had
some problems with automatic mapping of the state points for RTL-to-Gate
comparisons. In March, Mentor showed up again with a new release and now
I consider Mentor definitely as an option to Verplex. Especially if memory
consumption is a concern to you one should have a look at FormalPro.
- Raimund Soenning
Philips Semiconductor Starnberg, Germany
( ESNUG 373 Item 10 ) ------------------------------------------- [06/07/01]
Subject: ( ESNUG 371 #1 ) PhysOpt's Placement Of Clock Gating Cells
> I have some preliminary data to report on PhysOpt and clock gating cells.
> We're not using integrated clock gating cells, which makes this case
> *very* interesting for us.
>
> Around 71% of the clock gates have less than 10 um between the main gate
> and the enable latch. Here's how PhysOpt placed them:
>
> < 10 um - #################################################### 105
> 10 to 20 um - ################ 32
> 20 to 30 um - #### 8
> 30 to 40 um - # 2
> > 40 um - 0
>
> Total clockgates 147
>
> I can provide more info later if you'd be interested... I'm curious to see
> how our router handles these.
>
> - Neel Das
> Corrent Corporation
From: Lars Bo Graversen <larsg@mips.com>
Hello John,
I read Meel's ESNUG Post with great interest as it seems like he is using a
somewhat similar approach to clock gating with PhysOpt as we are. In
particular, I am interested in his statistics of the placement of the latch
with respect to the main clock gate. Has he generated this information
using a script? If so, would he be able to share this script with us? I
would like to attempt to generate the same type of statistic for our design.
- Lars Bo Graversen
MIPS Denmark
---- ---- ---- ---- ---- ---- ----
From: Neel Das <neel.das@corrent.com>
John,
I'll see what I can do. I'm disappointed so far with CTS results, though...
Lars, do you have any data in that realm that you could share?
- Neel Das
Corrent
( ESNUG 373 Item 11 ) ------------------------------------------- [06/07/01]
From: Caesar Abedin <cabedin@amcc.com>
Subject: What About Rivals To Simplex In Electromigration Analysis Tools?
Hi, John,
With our move to technologies below 0.18 and clock speeds in the upwards
of 300+ Mhz, we are finding the need to run electromigration analysis on
our signal nets. Unfortunately, most EM analysis tools available today
are for power nets. Have you heard anything from the masses about this?
So far, I've only uncovered ElectronStorm by Simplex as the only tool
currently in the market that does EM analysis on signal nets. Am I
missing something here? There's got to be more out there than this.
Avanti has something in the works for this, but it won't be available
until Q1/Q2 of 2002. What about Synopsys, Cadence, Mentor Graphics? Any
new startups? HELP!
- Caesar M. Abedin
Applied Micro Circuits Corp. Andover, MA
( ESNUG 373 Item 12 ) ------------------------------------------- [06/07/01]
From: Paul Zimmer <pzimmer@cisco.com>
Subject: Zimmer's vim Syntax File For PrimeTime Is In DeepChip "Downloads"
Hi, John,
I've been working on a color syntaxing file for vim (vim is vi-improved,
and can do color syntax highlighting if someone writes the code for each
language) for PrimeTime. I have finally gotten most of the kinks out of
it, and I'd like to share it with the asic community. I'm working on
getting it into the standard vim release, but that looks like it may take
a while. Would you have room for it on deepchip? It's about 120 Kbytes.
- Paul Zimmer
Cisco Systems
Editor's Note: It's in the www.DeepChip.com "Downloads" section. - John
( ESNUG 373 Item 13 ) ------------------------------------------- [06/07/01]
From: Hans-Christian Schaub <Hans-Christian.Schaub@eed.ericsson.se>
Subject: User Pissed That DC 00.11-SP1 Suddenly Doesn't Have auto_ungroup!
Hi John,
I tried the auto_ungroup feature in DC 2000.11. It worked quite good. Now
we moved to 2000.11-SP1 and DC complains that we don't have the DC-ULTRA
license. Is this "normal" that Synopsys cuts features in a bugfixed
version??? I'm a little unhappy. :-((
- Hans-Christian Schaub
Ericsson Eurolab Hildesheim, Germany
( ESNUG 373 Item 14 ) ------------------------------------------- [06/07/01]
From: Torsten Larsson <t-larsson@ti.com>
Subject: Wanting DC To E-mail Every Hour Instead Of In Between DC Commands
Hi, John,
I have been running synthesis and reoptimization on some very large chip
the last year, and I really wanted some improved tracking and reporting
capabilities that I can use on the fly. (Plus a high performance syntax
checker.)
Today I am running multi-pass LBO reoptimization, run time 2-3 days.
During evenings and weekend, I send emails that I can read from home,
and SMS messages via email, that I can read on my cell phone, to track
the progress.
I prefer SMS messages since they can reach me anywhere, and I don't have
to logon to a computer and check for emails. There are two main problems.
The first is that you can only send an email in-between other commands.
(The current DC command must finish before it can send me an e-mail.)
The second is how do I generate a good report that is possible to read
on a small display? Only 160 characters for SMS.
I want a feature so I can send a status report in the background via email
every "x" hour, plus one more email when the DC run finishes.
The number of characters problem will disappear in a year or so when we
start using GPRS phones, but a special report for a small display will
still be necessary.
Example of how you can send an email from dc_shell, containing the last
100 rows from your log file:
dc_shell>sh tail -100l file.log | mailx -s "Syn Done" [email address]
Is there anyone else that would appreciate these features, too?
- Torsten Larsson
Texas Instruments France Villeneuve Loubet, France
( ESNUG 373 Item 15 ) ------------------------------------------- [06/07/01]
From: Cliff Cummings <cliffc@sunburst-design.com>
Subject: Hey? Wasn't SystemC Going To Replace HDLs with free C Compilers??
John,
Meandering through deepchip.com, I came across Richard Goering's EE Times
(4/5/01) article about "Report reveals unannounced Synopsys tools."
I was amazed by the quote from Kevin Kranen:
"Kevin Kranen, director of strategic programs at Synopsys, noted that
ESNUG readers are primarily RTL hardware designers and verification
engineers. "SystemC is meant for a slightly different audience;
system designers who are modeling, validating and refining entire
systems," he said. Kranen said that SystemC compliments, and is not
intended to replace, existing HDL-based design flows."
Incredible! I thought SystemC was going to replace HDLs with free C
compilers so that we would all have free simulation. If Kevin wants to
combine C modeling and validation with HDL-based design flows, he might
want to look into SuperLog, which permits an engineer to compile C code
with a superset of Verilog.
I think Kevin might have a future as Dean of Spin-Doctor University.
- Cliff Cummings
Sunburst Design Beaverton, OR
( ESNUG 373 Item 16 ) ------------------------------------------- [06/07/01]
Subject: ( ESNUG 372 #4 ) PhysOpt Rival Agrees Congestion Is Pain In Ass
> Though our design's overall row utilization is low, about 55%, PhysOpt
> (since it doesn't have real global routing) keeps clustering cells to
> create very high density areas. This happens with -congestion option,
> even when we leave empty space around the cluster. This congestion makes
> our design unroutable.
>
> - [ Shrek's Donkey ]
From: Keith Mueller <keith@siperspective.com>
Hi John,
We have seen a number of designs that exhibit the same congestion issue
using several of the physical synthesis tools, so this problem is not
unusual, particularly in switching blocks in networking chips. These
blocks tend to be very large (sometimes pushing 500K cells which of course
is too large for physical synthesis), with a large number of ports on all
sides of the block and wide busses running every direction. It is a very
tough placement problem to get a routable implementation on these low
density, highly interconnected blocks.
Silicon Perspective's First Encounter is able to control the placement
density on a module-by-module basis within the block, so we can selectively
relieve the congestion.
- Keith Mueller
Silicon Perspective Corp. Santa Clara, CA
( ESNUG 373 Item 17 ) ------------------------------------------- [06/07/01]
Subject: ( ESNUG 372 #7 ) More React To The Avanti/Cadence Lawsuit News
> Amazing, I could not have come up with a better quote than the one I
> saw from you in EE Times. No, not the one about Cadence being a
> monopoly, anyone with any knowledge of the industry simply disregards
> your rhetoric as coming from a very small man. I am talking about the
> "morality is irrelevent" line. How clueless a man are you? You write
> that and then have the nerve to sponsor a childrens charity banner on
> the bottom of your home page.
>
> - [ unsigned ]
From: Philip Kuglin <phil_kuglin@credence.com>
John,
I kind of agree with some of this. You are saying the end justifies the
means, but doing that is a very slippery slope. Who decides when one can
ignore the law and do what they want? And how far? Are you sure about
this? Be careful what you want - you may get it.
- Phil Kuglin
Credence Systems Corp. Hillsboro, OR
---- ---- ---- ---- ---- ---- ----
From: Beth Martin <bmartin@adaptivesilicon.com>
Hi, John,
I don't know how you tolerate all the freaks that write to you. What you
actually were quoted as saying was:
"What's morally right may be irrelevant," Cooley added. "You need to
produce chips that are the fastest, smallest and best."
I'm getting tired of hearing all these hysterical engineers waving their
little fists at the universe over Avant!'s misbehavior. There are greater
injustices, and this one has aroused such passionate anti-Avanti sentiment
only because Hsu pissed Costello off.
It was a public blood-feud from the beginning, but half the EDA industry (at
least) seems to think it's the most egregiously horrible crime they've ever
heard of. Not that stealing code is okay, but people seem not to realize
that anyone could be convicted for leaving a job with, say, a web-page or
technical document template if someone hated us enough.
I'm glad this is all coming to an end, although I imagine many people will
feel lost without this soap-opera drama to engage them. Anyway, I'll be
toasting with my emotionally stable Avanti and Cadence friends to the final
demise of this insanity.
- Beth Martin
Adaptive Silicon, Inc.
---- ---- ---- ---- ---- ---- ----
From: Peter Hutton <hutton@tality.com>
John,
I don't think Avanti's existence will change the landscape one way or the
other. They don't have a leading product in any category now, e.g.:
- Physical Synthesis is Cadence, Synopsys and the others.
- Physical Verification is Cadence and Mentor.
- Formal Verification is Synopsys and Verplex
Avanti has stolen or bought some great technology (e.g. the ISS products)
and made mediocre badly supported ones out of them.
- Peter Hutton
Cadence/Tality
---- ---- ---- ---- ---- ---- ----
From: [ An Anonymous Mentor Guy ]
John,
I want to predict that Avanti will self-destruct due to attrition. We've
received so many resumes from Avanti since the admission of guilt that it's
quite feasible their brain-drain will leave the company with only lawyers
left to answer the phones.
- [ An Anonymous Mentor Guy ]
---- ---- ---- ---- ---- ---- ----
From: Subha Pindiproli <Subha.Pindiproli@emulex.com>
Hi John,
I heard from my collegue this morning that Cadence is pursuing a Civil
Lawsuit against Avanti for $1 billion. What I heard from your comments
and articles was that, as a result of Avanti's presence, Cadence has
started improving its layout tools.
To me it looks like Cadence is more interested in spending its efforts
in lawsuits than bringing in quality products in reducing design cycles.
If Cadence were to succeed in putting Avanti out of business, the EDA
industry is doomed, and all who depend on it.
I think you should make it as a topic of discussion at DAC during Cadence's
keynotes or Forum discussion. It looks to me Cadence is being very short
sighted in this matter, and they would just alienate more customers.
- Subha Pindiproli
Emulex
============================================================================
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/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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