> After viewing your DeepChip website today, I see that you (again) scooped
> my guys, Goering and Santarini, with that Synopsys conspiracy story.
> You're showing some top-notch investigative reporting there. I hope to
> see you at DAC in 2 weeks with your meds correctly adjusted by then.
>
> - Brian Fuller, Executive News Editor
> EE Times & EETimes.com
From: [ John Cooley's Mom In Vermont ]
Hi Dear,
How are you? What does meds mean in reference to you? We read what your
editor said in praise of your work. We are ok. I had some more gum
surgery this week. It is expensive to keep the old choppers in my head.
So learn from us and floss so you don't spend your sunset years in a
dentist chair like us. Let us hear from you. Does meds stand for
medicine? Mummy worries you know. Love,
- Mom
---- ---- ---- ---- ---- ---- ----
From: Christopher Watson
Attention John,
It has come to my attention that you have made links to a demo proposal
we put together for a Synopsys project. At the request of Synopsys, we
removed the proposal from our website. When we made this proposal, we
were entertained by it. It was a funny idea. We even were hired for the
project. But recently (in the last few days) we were requested to remove
it from our website. So we have completely cut this proposal from our
portfolio. I was bummed about this because I really like having this demo
in our site. I guess it was going to happen sooner or later. Synopsys is
one of our favorite clients. Removing the demo also broke a link on your
website. For this I apologize.
I returned to your site today to find that instead of finding something
else to link to, you simply made your own version of our Internet pills
proposal page at your website. While I am honored that you also find our
graphic humorus, the people at Synopsys do not. At the request of our
legal department, and the Synopsys legal department, I am requesting that
you remove this page from your website immediately.
Sincerely,
- Christopher Watson
TAGE Multimedia Productions Sonoma, CA
( ESNUG 354 Subjects ) -------------------------------------------- [6/1/00]
Item 1 : ( ESNUG 353 #2 ) Handling Scan Test Issues With Ultima ClockWise
Item 2 : ( ESNUG 352 #1 ) ClockWise? Use Free QPopt changeClock Instead!
Item 3 : Overriding Computed Steiner Routing In PhysOpt & Design Compiler
Item 4 : Wall Street Analyst Seeks Beta Users Of Synopsys Detailed Router
Item 5 : Dedicated Scan Out "test_output_only" Fails In DFT Compiler 99.10
Item 6 : ( ESNUG 353 #1 ) PrimeTime Finds DC's Design Rule Violations???
Item 7 : Common Errors On LEF2PLIB Conversion For PhysOpt & Chip Architect
Item 8 : Synopsys DC 99.10 Generates SDFs With "\/" That ModelSim Dislikes
Item 9 : ( ESNUG 353 #8 ) URL's On Fault-Tolerant System Design Strategies
Item 10 : ( ESNUG 353 #4 ) DC Synthesizing To Fewer, Bigger, Richer Cells?
Item 11 : ( ESNUG 353 #7 ) Overcoming Newbie Escalade DesignBook Problems
Item 12 : ( ESNUG 353 #5 ) Signal Integrity, Cadence SE-SI, PhysOpt & Yahoo
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 354 Item 1 ) ---------------------------------------------- [6/1/00]
Subject: ( ESNUG 353 #2 ) Handling Scan Test Issues With Ultima ClockWise
> Did he insert the clock trees before adding scan logic or after? I have
> to assume the useful skew for functional mode is not useful for scan
> testing. Did he then go back in the netlist to add delays to the scan
> paths to fix hold time problems?
>
> - Tim Dunnington
> Motorola SPS Chicago, IL
From: Jon Stahl <jstahl@avici.com>
Hi John,
Since I didn't use this capability - because we have our own methodology for
handling hold time issues - I forgot about it until one of my colleagues
reminded me after he saw ESNUG 353.
ClockWise has a feature where you can define scan chains (or use ones that
are already defined in your DEF), which it will then ignore hold time
problems on during permissible range generation and clock tree synthesis,
and later fix. I thought others would like to know, but I can't speak for
how well it works.
- Jon Stahl, Principal Engineer
Avici Systems N. Billerica, MA
( ESNUG 354 Item 2 ) ---------------------------------------------- [6/1/00]
Subject: ( ESNUG 352 #1 ) ClockWise? Use Free QPopt changeClock Instead!
> I recently taped out a design on which I inserted clock trees using the
> Ultima ClockWise tool and really liked it. In the past I have used
> intentional skew in special situations to help improve timing, but it
> was difficult time consuming hand work...
>
> - Jon Stahl, Principal Engineer
> Avici Systems N. Billerica, MA
From: Bobby Mozumder <mozumder@cadence.com>
Hi, John,
(Fair Warning: I work in Cadence methodolgy consulting, so my experiences
are with Cadence tools.)
You've been really getting into ClockWise lately. I have to ask. Why buy
a new tool when you can use the exact same functionality in your existing
Cadence tools? In case anyone has not mentioned this to you yet, QPopt is
also capable of modifying the clock tree to meet timing. This is a new
capability in QPopt that other people may know about, although QPopt has
been around a while.
For those unfamiliar with QPopt, it is the placement based optimizer within
QPlace, the Cadence standard cell placer and part of the Silicon Ensemble
suite of tools. QPopt performs basic operations such as cell upsizing and
downsizing (including of Flip-Flops), and buffer insertion and removal. It
doesn't perform placement based logic restructuring. For that you would
use PKS.
Anyways, the clock skewing capability of QPopt is simply an additional set
of transforms that QPopt is allowed to perform to meet timing. It adds
clock insertion delay to meet setup timing. The timing constraints are
given to QPopt in GCF Format, a systems level constraints format (contains
clock frequencies, IO timings, and exceptions). Pearl is the timing engine
inside QPlace that handles the GCF constraints. You would use the clock
skewing capability after building a clock tree with CTGen, then performing
propagated clock timing optimizations with QPopt.
You could feed it an RSPF file from HyperExtract, or it will internally
generates its own through its global router (the same global routing code
that is in PKS and WarpRoute).
This flow has obvious advantages over manual editing or using third-party
point-tools such as ClockWise. Mainly that the timing engine, Pearl, is
shared with the rest of the Place and Route tool. Also, it is a systems
level constraints (GCF based) timing optimizer, rather than a clock-tree
builder. This means you don't have to make the flow any more complex than
what it is. Just let the tool do whatever it can to meet your systems
timing (including IO timing requirements). It will also fix hold
violations, if any, by itself.
For those using the Pearl based QPopt, just add "changeClock" along with
the usual "upsize+downsize+bufferInsert+bufferDelete" to the
optAllowedOperation qplace config option. An example qplace.config file:
inputFormat SiliconEnsemble
lefName "tech.lef ../LIBRARY/LEF/cells.lef"
defName "design.def"
inputGCFConstraints "design_worst.gcf"
inputGCFTimingLibraries "design_worst.gcf"
defOutName "design.def"
outputFullDef TRUE
timingMode TRUE
timingDrivenRouting TRUE
placePin "refine"
optScanChain TRUE
optTimingType "setup+hold+maxTran+maxLoad"
optAllowedOperation
"upsize+downsize+bufferInsert+bufferDelete+changeClock+resizeFlops"
optSignalIntegrityType "xtalk+selfHeat+hotElectron"
optReportName "RPT/qpopt.rpt"
timingReportName "RPT/qp.timing.rpt"
The changeClock feature is not alpha or beta code. It's just another
(currently hidden) option within the tool. Silicon Ensemble users should
get qplace 5.1.62 (or the latest) tarkits.
- Bobby Mozumder
Cadence Columbia, MD
( ESNUG 354 Item 3 ) ---------------------------------------------- [6/1/00]
From: [ A Synopsys PhysOpt CAE ]
Subject: Overriding Computed Steiner Routing In PhysOpt & Design Compiler
John, please post this to ESNUG.
Some of my customers are asking me how to override the PhysOpt computed
Steiner routing for back-annotated nets. Steiner back annotation can be
removed with the "remove_annotated_delay" & set_annotated_delay" commands.
In the example circuit:
+-----+
A| G | +-----+
------+ A |Z A| G |
B| T +---netB----+ A |Z
------+ E | B| T +---netC-------
| 1 | -----+ E |
+-----+ | 2 |
+-----+
You can change the delay on netB to 0.25 ns with the following commands:
remove_annotated_delay -from [get_pins GATE1/Z] -to [get_pins GATE2/A]
set_annotated_delay 0.25 -from [get_pins GATE1/Z] -to [get_pins GATE2/A]
WARNING: PhysOpt & Design Compiler will not override the existing delay
value applied on a net if the new value is smaller than the previous value!
No warning is issued when one attempts to override smaller delay value on a
net, the command will be ignored. Therefore, it is ALWAYS best to remove
the annotated delay before attempting to override the delay with the
set_annotated_delay command.
- [ A Synopsys PhysOpt CAE ]
( ESNUG 354 Item 4 ) ---------------------------------------------- [6/1/00]
From: Jared Leon <jaredl@sbsf.com>
Subject: Wall Street Analyst Seeks Beta Users Of Synopsys Detailed Router
Hi, John,
I was wondering if you have heard anything about Synopsys' progress on a
detailed router. To my knowledge they said it should be out by year's end,
but I would think someone must be beta testing it soon if they do plan to
release it in the next 6 months or so.
- Jared Leon, Analyst
SBSF Capital Funds Rockefeller Center, NYC
( ESNUG 354 Item 5 ) ---------------------------------------------- [6/1/00]
From: London Jin <jinl@taec.toshiba.com>
Subject: Dedicated Scan Out "test_output_only" Fails In DFT Compiler 99.10
Hi John,
This is to caution users who are interested in using the dedicated scan-out
"test_output_only" in DFT Compiler 99.10. It does not work. The problem
is that DC 99.10 still uses the dedicated scan-out pins with an attribute
of test_output_only in .lib for non-scan (or functional) purposes, although
we modeled the scan cells exactly according to what Synopsys required.
Synopsys has been working on it since 4/26, and the issue is still open.
- London Jin
Toshiba San Jose, CA
( ESNUG 354 Item 6 ) ---------------------------------------------- [6/1/00]
Subject: ( ESNUG 353 #1 ) PrimeTime Finds DC's Design Rule Violations???
> The ideal net command won't overcome the max_transition problem,
> especially when their signals are driven from internal gates. In order
> to run compile -top to fix other things, these bogus problems have to be
> out of the way. I tried set_load 0 on the high fanout net, but that
> doesn't overcome the load of all the input pins attached to the net, so
> the transition time is still outrageous. In order to get around the
> problem, I had to get ugly and resort to "scratch and sniff" techniques.
>
> - Rob Wiegand
> NxtWave Communications Langhorne, PA
From: Wayne Miller <Wayne.A.Miller@smsc.com>
John,
I've also seen problems where DC finishes with no design rule violations,
but then PrimeTime reports max_fanout violations on gated clock networks.
I reported this to Synopsys, and they said they were aware of it.
- Wayne Miller
Standard Microsystems Corporation Long Island, NY
( ESNUG 354 Item 7 ) ---------------------------------------------- [6/1/00]
From: [ A Synopsys PhysOpt CAE ]
Subject: Common Errors On LEF2PLIB Conversion For PhysOpt & Chip Architect
John, please post this to ESNUG.
If you're using the current version of PhysOpt, you will need to do a
Cadence LEF to Synopsys PLIB conversion to make sure your physical library
for PhysOpt that corresponds to the logical library. Your physical
library defines properties for ASIC cells that allows placement tools to
know the size of the cell, the location of the pins, the locations of
obstructions, and other physical data.
The creation of a physical library involves two steps:
1) lef2plib conversion
lef2plib "physical_lib_name" "lef_filename" "plib filename"
2) compile plib to pdb format in psyn_shell
psyn_shell -f make_pdb.tcl
"make_pdb.tcl" has in it:
read_plib plib_filename
write -output physical_lib.pdb physical_lib_name
exit
The only new variable that is needed to load the physical library in PhysOpt
is:
set_physical_library physical_lib.pdb
Note: PhysOpt will look in your "search_path" to find the physical library.
When you invoke the command "physopt" in psyn_shell, PhysOpt performs one
last check of the logical vs the physical libraries. During the comparison
you may see Warning messages regarding missing physical library for
corresponding logical library. You can invoke a check_only to compare the
logical library with the physical library with the following command:
physopt -check_only
Another check the user can make to see if cells are included in the physical
library is to use the command below:
report_lib -physical "my_physical_lib"
This way you can find any physical probelms before you start a full PhysOpt
run. If a Warning occurs for any cells that you plan on using, below is a
list of guidelines to check to get rid of the warnings:
1) Make sure there is a matching LEF file for your corresponding logical
cell.
2) Check to see that the cell name in the LEF file exactly matches the
cell name in the logical library. The checks are case sensitive so
watch for uppercase vs lowercase errors.
3) PhysOpt checks for matching pin names. To verify the pin names match,
consider the following steps:
* Check that you have the same number of pins in the LEF and the
LIB files. You can grep for keywords to get a quick number of pins.
* Watch for different characters in bus pin names. A common mistake
is "[" in the LEF and "(" in the LIB file.
* Watch for case sensitivity between the pin names.
4) PhysOpt also checks the direction of pins. A mismatch of the direction
for a pin will also cause a mismatch.
Hope this helps.
- [ A Synopsys PhysOpt CAE ]
( ESNUG 354 Item 8 ) ---------------------------------------------- [6/1/00]
Subject: Synopsys DC 99.10 Generates SDFs With "\/" That ModelSim Dislikes
> We have a problem in the SDF file generated with Synopsys DC 99.10. We
> have a design, which we ungroup, in the lower design we have a component
> named qWRN3_F_reg in the umpi block. In the VHDL netlist generated by DC
> is umpi_qWRN3_F_reg. When an SDF file is generated using:
>
> write_sdf -c vhdl -v 2.1
>
> it appears as umpi\/qWRN3_F_reg. Our ModelSim simulator doesn't like it.
> Does anyone knew a way to overcome this?
>
> - Nitzan Poylitz Israel
From: Emmanuelle Laprise <emmanue@photonics.ece.mcgill.ca>
The trick that I have found is that after you ungroup, you use the rename
command like this:
change_names -rules vst_cell -hierarchy
Where the rules can be defined something like this:
define_name_rules vst_cell -type cell -allowed "A-Za-z0-9_"
You can also use for other reaons:
define_name_rules vst_net -type net -allowed "A-Za-z0-9_<>"
define_name_rules vst_port -type port -allowed "A-Za-z0-9_<>"
change_names -rules vst_net -hierarchy
Hope that this helps.
- Emmanuelle Laprise
McGill University
( ESNUG 354 Item 9 ) ---------------------------------------------- [6/1/00]
Subject: ( ESNUG 353 #8 ) URL's On Fault-Tolerant System Design Strategies
> Does anybody know of a resource (web, book or article) describing
> architecture design for systems, storage or logic, whose components are
> prone to very high rate of failure, along the line of 0.1%-1%?
>
> - Greg Deych
From: Subhasish Mitra <smitra@CRC.Stanford.EDU>
Hi John,
You can take a look at the web-site of Center for Reliable Computing here at
Stanford University directed by Prof. Ed McCluskey. http://crc.stanford.edu
In the bibliography page, you can find a very comprehensive list of
publications related to fault-tolerance and digital test. Some of the major
innovations in the field of fault-tolerant computing happened at Stanford
CRC. Right now, the center is running 2 big projects on fault-tolerance:
(1) Fault-tolerance in reconfigurable systems and (2) Fault-tolerance in
space environment (they have their experiments running on a real satellite
in the space.)
About Greg' queries about fault-tolerance techniques in systems, here is a
simple, high-level classification:
(1) Memories: Error detecting and correcting codes ( Hamming codes, etc.)
(2) Logic:
Error detection:
Techniques include: Duplication, Diverse Duplications (different
implementations of the same logic function), parity prediction. For
circuits like adders, etc., parity prediction may be economical;
however, recent IBM papers on G5/G6 chose duplication for their
execution units compared to parity prediction. A source of problems
in these systems is the problem of common-mode failures (single cause,
affecting multiple modules, data integrity not guaranteed). It has
been shown recently that for random logic circuits, diverse
duplication has marginally more area-overhead than parity prediction.
However, diverse duplication provides significantly more protection
against common-mode failures.
Error correction:
Triple Modular redundancy, etc.
(3) Storage (Disks): RAIDS: Redundant array of inexpensive disks.
Another good source of real industrial data is the IBM Journal of Research
and Development.
- Subhasish Mitra
Stanford University
( ESNUG 354 Item 10 ) --------------------------------------------- [6/1/00]
Subject: ( ESNUG 353 #4 ) DC Synthesizing To Fewer, Bigger, Richer Cells?
> I was wondering how I could use that 23 percent white space for a few
> bigger, richer cells (e.g. AND-OR-INV) and reduce the wiring overhead. My
> idea is while the cell area increases, the routing overhead decreases,
> and the overall design area should shrink (wishful thinking?)... We tried
> editing the .lib file to increase the wire area in wireload model. The
> idea being that each wire now should have an "area penalty" associated.
>
> wire_load ("my_wire_load") {
> resistance : 0.000083 ;
> capacitance : 0.000116858 ;
> area : was: 1.319252 is: 5.319252; <== but didn't help a lot
> (0.3% less nets)
> slope : 101.342461 ;
> fanout_length (1, 149.84) ;
> ... more entries here ...
> }
>
> To me it seems that this number is primarily used for the report_area
> output but for nothing else. Correct?
>
> We were also thinking about making nets artificially longer, so that each
> wire has a timing-penalty associated (I have no synth results yet) but I'm
> somehow not convinced that that's a good strategy. Any suggestions?
>
> - Christian Bohm
> Analog Devices B.V. Somewhere, Europe
From: [ A European Synopsys FAE ]
Hi John,
Yes, wire area attribute is useful to some extend in reducing net length and
using more complex gates, yet...
DC always had a limitation when it comes to using complex gates. Outside of
DesignWare and sequential cells we hardly ever map to cells with multiple
outputs, and the number of used inputs has a maximum of (have to check) 4.
Using DC Ultra however, you can use more complex cells, and wider fanin
cells, but be aware of the fact that occasionally wide fanin cells might
lead to congestion problems.
Concerning DC Ultra, I believe we have an upgrade plan from DC Expert
available.
- [ A European Synopsys FAE ]
---- ---- ---- ---- ---- ---- ----
From: Stephen McInerney <spmcinerney@hotmail.com>
Hi John,
Has Christian tried the prefer_cell or set_prefer directive? He could also
forbid the smaller cells (at appropriate points in synthesis.) I used this
many years back with reasonable results to guide DC.
Another hack would be to set the areas of complex cells in the library to
lower their synthesis cost.
There are many manipulations that you can to do the wireload, setting an
over-optimistic wireload, customizing it, etc., but they tend to cause huge
violations when you check with the target wireload.
One final question: is he correctly using hierarchy in the design? Has he
tried different synthesis scripts and constraints for each (separate FSMs
and control logic from regular stuff.) Are his test insertion, I/O delays
or clock tree inserting spurious cells?
- Stephen McInerney
---- ---- ---- ---- ---- ---- ----
From: Kevin Grotjohn <krag@lsil.com>
Hi John,
I figure I should contribute results of my R&D on this topic. Hopefully it
is free of spelling/grammer errors -- any mistakes are the fault of cold
medicine and bad typing!
The WLM area factor does work if you set it properly, but this is not easy
to do because it is a unitless factor that depends on your ASIC vendor
library area units, EDA vendor WLM length units, and your ASIC/EDA vendor
needs to be in sync! I assume you do not have that problem. ;-)
WLM area factor should be calculated such that dc_shell cell_area/total_area
is a good prediction of layout utilization. Thus if it is a highly utilized
design then it is OK to use smaller/faster cells, while for low utilization
the larger/smaller cells should be tried.
Dc_shell multiplies WLM area factor by total fanout_length for the design
and WLM, which usually is monotonically increasing per fanout. Thus the
higher the total fanout in your design, the higher the wire_area of your
design. Since wire_area is included as part of the area cost function
(assuming you did set_max_area 0) it will tend to map to cells that
eliminate nets thus reducing total fanout.
Even though these complex cells eliminate wires in layout, they are
usually slower, so your timing constraints may interfere with this
optimization - in which case you can ignore this letter...
First find out how Synopsys FloorPlan Manager calculates it. This is
something many design/floorplanners miscalculate, and like the original
poster they have not seen the benefit.
dc_shell> man create_wire_model
Net area coefficients are calculated whenever the
-total_area option is used. The cell area of the top
design or cluster specified is subtracted from the
total area, area, to determine the total net area
(wire_area). Then wire_area value is used to calculate
the area coefficient (wire_area / total_wire_length).
If the -hierarchy option has been specified, the area
coefficient calculated for the top design or cluster is
used for all wire load models of subdesigns or
clusters.
Here is a breakdown of the formula for LSI.
Cell area is calculated in cellunits for LSI libraries. This simply
measures the number of grids the cell occupies in the placement row
direction. If it is a double cell that takes two rows then count it twice.
Total area must also then be calculated in cellunits. Assuming that
placement rows have no spacing between them, this is simply the number of
placements rows times the number of grids wide for the cell placement area.
Even if the designs placement rows have added route spacing, no spacing is
assumed because area utilization rather than row utilization needs to be
calculated. If you have a floorplan with memories/cores be sure to subtract
out those areas using an equivalent measure.
"total_wire_length" must be in the same units that the wire load model uses.
I like LSI WLM's to use Kgrids (1000 cellunits), but getting access to
total_wire_length and its units depends on your tool suite. If you are
stuck then summarize the backannotation set_load file and divide by the WLM
capacitance factor to estimate the total_wire_length.
So for LSI the formula is
(total_area_in_cellunits - cell_area_in_cellunits)
WLM area = ------------------------------------------------
(total_wire_length_in_cellunits/1000)
How can you tell it worked?
The painful way is to do an iterative squeeze on place and route until route
failure, for netlists synthesized with different WLM area factors. This is
especially painful if you are not sure you have the WLM area factor set
right. Realize also that this is a recursive problem, because the layout
used to calculate WLM area factor will depend on the initial WLM area
factor.
Another way is to score the library/design for those cells that eliminate
nets to gage the potential for layout improvement. It is really not
necessary to score MUX, flop, or arithmetic cells because those are not
synthesized with random logic algorithms in dc_shell and there is not much
chance to minimize this cost. Hopefully your ASIC vendor has include
schematics of cell structure in the databook so you can calculate this cost.
Here's how total nets is influenced:
a) number_of_inputs: If high input cells do not exist, then more low
input cells would get used, which would increase total nets
b) logical_depth: If complex "and/or" cells are used - then this will
eliminate chains of "and/or" logic in the netlist, which minimizes
total nets.
Cell prefix logical_depth
A O 1
AO OA 2
AOA OAO 3
AOAO OAOA 4
AOAOA OAOAO 5
AOAOAO OAOAOA 6
c) number_of_inversions - All ASIC libraries are composed of negative
logic primitives, so count the number of input/output inverters in the
cell. If instead dc_shell used inverters in the netlist, then total
nets would be increased.
Cell number_of_inversions
ND2 0 basic NAND gate
AND2 1 ND2 w/ N1 on output
ND2AN 1 ND2 w/ N1 on input A
AND2AN 2 ND2 w/ N1 on output & input A
AND2ANBN 3 ND2 w/ N1 on output & input A, B
NR2 0 basic NOR gate
Note that even though the AND2ANBN performs the same function as NR2, it
counts more as a net minimizer. If the NR2 is poor for drive staging,
dc_shell will use NAND gates and inverters if the AND2ANBN is not available
to get better drive staging.
To evaluate the mapping of the design use a multidimensional histogram to
see the WLM area shift from cells with a lower score to a higher score, that
results in a reduced net count. You really can not simply summarize the
score for a design because the tradeoff is between more cells with a lower
score, and fewer cells with a higher score. The result can also be seen
with less net/instance count, but that does not make for pretty charts for
clueless managers. Make sure you do not report cell area - as it may
actually go up with complex cells which is OK if you have better layout
utilization.
So there you go John, this method is a lot easier than tweaking the WLM area
with layout squeeze iterations. Tweak the WLM area so it predicts the
layout utilization, and measure the reduced fanout (net) cost of the complex
cells. However what you really need is a physical synthesis tool that does
not use WLM area for prediction but optimizes local congestion vs. timing
vs. area when mapping cells - but that is another topic.
- Kevin Grotjohn
LSI Logic Corp. Pleasanton, CA
( ESNUG 354 Item 11 ) --------------------------------------------- [6/1/00]
Subject: ( ESNUG 353 #7 ) Overcoming Newbie Escalade DesignBook Problems
> I've just started using Escalade DesignBook on Solaris 2.6. While
> testing several cases, I've got serveral questions that couldn't
> overcome as far as reading PDF documents.
>
> - [ From The Land Of Hello Kitty ]
From: John Vincent <vincent@kodak.com>
Hi, John,
We're using Escalade DesignBook 3.8c on Solaris 2.6. This has several
important bug fixes and I would recommend using it rather than the previous
versions. It was available for download from the Escalade web site.
However, in the wake of the recent acquisition of Escalade by Mentor, the
download page is no longer working. You will probably have to call
Escalade support, (408) 654-1600, to get the upgrade.
As for the problems mentioned:
> 1. The Help doesn't work. The format of help file seems to be Windows
> help format(.hlp), so can't I use Help on Solaris? Why?
> 3. I set the header information from the menu (Options)- (code generation)
> - (copyright) - (Use Project Copyright). But the properties such as
> $name, $date aren't expanded.
- #1 and #3 are probably installation / setup problems. We have not had
problems with these.
> 2. When I check a block with Ctrl-F9 in the block editor, a small window
> appears and reports only Error/Warning counts. Is there any way to
> get further information?
- #2 - try using Windows >> Output Window to make the Output Window
appear. It may also help to toggle off and back on the "Bring up
Output Window on errors or warnings" button on the Miscellaneous
tab in the View Options window from Options >> View.
You may also occassionally have the same problem when doing checks
on HDL code blocks using a 3rd party checker (compiler), toggling
off and then on again the "Show External Syntax Checker log output
on Design Check" button on the General tab of the Code Generation
window from Options >> View should solve this.
> 4. When I rotate a block with wire and connector 270 degree, the port
> description and connector description faces the opposite side. I can
> correct it by rotating only connectors, but it's troublesome. How
> can I move the port/connector/wire description?
- #4 - You made an interesting observation. The text for connectors,
for ports, and inside symbols behave differently as they are
rotated. Connector text rotates in the opposite direction from
that for ports. Text inside the symbol follows the port text on the
first rotation, but the connector text on the third rotation. I had
not noticed that previously.
> 5. How to set the Printer and printing size? Although I can set the
> working page size in the menu (Option)-(Edit Preference)-(Page),
> printing page size seems fixed to A4 Portrait.
- #5 - Printer setups need to be defined by the win.ini file in the
user's home directory to control the print options used. Here are
the changes I made to mine:
[windows]
device=lp,PSCRIPT,DEFAULT
[ports]
DEFAULT=lp -c -o letter "%s"
DBOOK_PRINTER1=lp -d hp1 -c -o letter "%s"
DBOOK_PRINTER2=lp -d hp1 -c -o letter -o landscape "%s"
DBOOK_PRINTER3=lp -d hp1 -c -o 11x17 "%s"
DBOOK_PRINTER4=lp -d hp1 -c -o 11x17 -o landscape "%s"
...
[Devices]
A size Portrait=PSCRIPT,DBOOK_PRINTER1
A size Landscape=PSCRIPT,DBOOK_PRINTER2
B size (Tabloid) Portrait=PSCRIPT,DBOOK_PRINTER3
B size (Tabloid) Landscape=PSCRIPT,DBOOK_PRINTER4
The ports section defines the commands issued when particular printer
"devices" are selected. The Devices section sets the descriptions that
appear in DesignBook when selecting the printer to use.
Printing changed somewhat in version 3.8x. You need to perform the
printer setup before doing any printing. The selection applies to all
printing operations until changed.
You need to make sure the printing setup matches the page being printed;
both size and orientation. DesignBook formats the output according to
the selections specified. If this does not match the printer "device",
you will not get what you want.
Words of warning:
- The win.ini may be used by other applications which also used MainWin
for porting to UNIX, e.g.Altera Max+plus II, so you may have to watch
for that.
- Avoid using rotated text, it does not work well in UNIX - the
position often gets messed up - but is fine using Windows
(possibly a MainWin porting problem?)
Hope this helps you, "Hello Kitty".
- John Vincent
Eastman Kodak Rochester, NY
( ESNUG 354 Item 12 ) --------------------------------------------- [6/1/00]
Subject: ( ESNUG 353 #5 ) Signal Integrity, Cadence SE-SI, PhysOpt & Yahoo
[ Editor's Note: Again I'm surprized. Usually the Yahoo EDA stock chat
boards are rife with day traders trying to manipulate stock prices. Yet
I accidently found another technical exchange there this week! - John ]
From: [ Tall Thin Dude ]
I have some friends who looked at the supposed Cadence Signal Integrity
offering. Apparently it uses a VERY crude model.
Instead of looking at real agressor slews it averages slews across the whole
design for all agressors losing substantial accuracy. The equation used
once the raw inputs are obtained is also not very good.
Perhaps a bigger limitation is in terms of it's inability to correct
violations. While it may be able to crudely detect some violations the
fix-up will be mostly manual with alot of iterations. The confidence of
detection when you are done will be poor.
It is fundamentally limited for future needs by the primitive SE router.
The only true variable width/spacing support in Cadence tools is through
their IC Craftsman, but this will not help here.
This solution might work for some 200 MHZ designs in 0.25 um and is perhaps
better than nothing at all. You've got to ask yourself one question, do you
feel lucky?
In terms of the Avanti Signal Integrity, this I know the least about. I
have heard it also is fairly primitive and based on their Star-RC flow.
I am looking to the start-ups for solutions here. There are some good
analysis companies coming on line. I plan to check out CADMOS and Moscape.
In terms of fixing the only interesting companies I see here would be those
who offer a full backend solution such as Magma or Monterey. I plan to do
some looking around at the DAC.
- [ Tall Thin Dude ]
---- ---- ---- ---- ---- ---- ----
From: [ firfilter ]
Here's my lucky guess from feedback I got:
- Cadence PKS+SE just doesn't cut it
- Avanti neither
- Synopsys PhysOpt improves the Cadence/Avanti flow quite a lot but is
not a full solution (yet)
- Magma has some technology but mainly: a lot of marketing BS
- Monterey: they may have something there, though their product looks
like a pre-pre-beta release
Good luck!
- [ firfilter ]
---- ---- ---- ---- ---- ---- ----
From: [ si_wizard ]
> I have some friends who looked at the supposed Cadence Signal Integrity
> offering. Apparently it uses a VERY crude model.
Perhaps you should check out the quality of your friends, or examine the
software yourself.
> Instead of looking at real agressor slews it averages slews across the
> whole design for all agressors losing substantial accuracy. The equation
> used once the raw inputs are obtained is also not very good.
It does this during PLACEMENT, when of course the neighbors are unknown, and
using an average is the best you can do. And using an accurate equation here
is pointless, since the data is only an approximate.
The main idea of this step is to fix the obvious problems early. Note that
PhysOpt, and to my knowledge Avanti, don't do anything at all at the
placement stage to try to reduce downstream Signal Integrity problems.
Once the design is routed, of course, Cadence Signal Integrity uses real
cross coupling caps, accurate slews, timing windows, and an accurate
electrical model.
> Perhaps a bigger limitation is in terms of it's inability to correct
> violations. While it may be able to crudely detect some violations the
> fix-up will be mostly manual with alot of iterations.
In the most recent case of which I have knowledge, the software found 140
potential errors (out of 326K nets) and was able to fix all but 5
automatically.
> It is fundamentally limited for future needs by the primitive SE router.
> The only true variable width/spacing support in Cadence tools is through
> IC Craftsman, but this will not help here.
Note that in general fiddling with width and spacing is the wrong way to
solve Signal Integrity problems. The reason is simple - the big designs
that have these problems are already routing limited. Increasing the width
and/or spacing makes them bigger, or unroutable, or both. However, this
implies the cell utilization is not 100%, so if you can insert buffers or
size cells without affecting the routing you can fix Signal Integrity
problems without a size or speed penalty, in general. This is the approach
used in the example above.
> I am looking to the start-ups for solutions here. There are some good
> analysis companies coming on line. I plan to check out CADMOS & Moscape.
The CADMOS product that was just introduced:
http://www.dacafe.com/DACafe/NEWS/CorpNews2/20000522_fl_cadmos_.html
It does EXACTLY what the Cadence product introduced 1999 does in terms of
timing, and it does not offer nearly the support in terms of automatic
fixing.
> I plan to do some looking around at the DAC.
An excellent idea, especially if you can discard your preconceived notions
and look at the evidence of which tools are working, in production, today.
- [ si_wizard ]
---- ---- ---- ---- ---- ---- ----
From: [ Tall Thin Dude ]
Well, si_wizard (or is that Cadence Signal Integrity Mktg. Droid), perhaps
Cadence has refined its crude model slightly by including the individual
slews and driver resistances in the backend.
There are many other aspects to a good model other than just a marketing
"feature checklist" for the basics. It is good to see at least Cadence may
now have the basics. I trust my sources and still have my doubts.
Since there are conceptual limitations with the SE router in supporting more
advanced routing and many known congestion problems with the SE/PBOPT/QPOPT
flow, I can understand si_wizard's limited view on the use of wide wire
spacing and shielding for fixing Signal Integrity violations. From my real
world design experiences I do not agree.
First of all, unlike PhysOpt, PBOPT/QPOPT are severly limited in the
percentage of placement based sizings they can do. Wireloads for initial
sizing and little downsizing of gates means big slews, more wasted area, and
a more poorly Signal Integrity conditioned design to start with.
Until (if ever) PKS becomes usable, the overall noise level of a Cadence
design will be higher to start with than a tool that sizes every gate based
on placement. Perhaps this is the real reason for the large number of
violations being reported in ESNUG. I don't know that I buy that improper
slew story. Lib slews are characterized using SPICE. Unless there is a
problem with bad threshold settings I don't know that this really holds
water.
Concerning the use of wide spacing, I have seen that typically larger nets
will suffer from Signal Integrity problems due to the summation of
individual aggressors. Even though the big chips may have hot spots that
are congested, there will generally be many areas of a problem net where
wide spacing can be used successfully to bring down the noise to acceptable
levels.
Many of these Signal Integrity problem nets tend to also be timing critical
nets. While buffering can be useful in some cases, it increases the risk of
holding timing closure due to the added intrinsic delay of the buffer.
Spacing or shielding on the other hand can be done without negative timing
impact.
In our manual approaches there were many places where buffering would not
have been able to fix problems without making timing worse. For these cases
spacing and shielding were able to do the job with no timing impact. In
fact many cases timing was actually improved from the wide spacing.
Since si_wizard reports only 140 out of about 326K nets that needed
correction, I have a hard time seeing how wide spacing noncongested sections
of this small percentage of wide spaced nets would significantly impact
area. In fact in a gridded routing approach where pitch is typically line
to contact there is alot of spacing that can be done for free just by going
offgrid if the router is capable. The more integrated solutions will
benefit here since they can check the slack on adjacent nets where wires
will be moved closer.
While I have done alot of manual fixing with shielding and spacing in layout
editors, I still believe there is big potential for an automatic tool in
this area. For Cadence to enter this area they will need a more modern P&R
infrastructure.
Since the Cadence Signal Integrity option is only available on their
unstable Genesis database, I question the claims of "production use" of the
tool.
How about giving some names of the customers you claim are using the Cadence
Signal Integrity solution in production flows?
Also be sure to list the combination of tools this Signal Integrity flow
integrates with.
I am sure there will be some folks who will pay the high price for the
option. To me it does not really matter. I like these customers with big
$$$ to spend.
All I can say is read the fine print before you buy, and don't trust anybody
with a Marketing title.
- [ Tall Thin Dude ]
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 11,086 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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