> John -- I'm surprised you didn't mention "The Horse Whisperer". It was
> the same as "The English Patient". Wife steps out on loyal husband and
> falls for cowboy (Robert Redford) who is tending to sick horse. Husband
> never did anything wrong. (anon pls.)
>
> - [ Zigzag, the Bail Bondsman ]
From: Karen@vitalcompr.com (Karen Tyrrell)
John,
I recommend an article in the October 19, 1998 Forbes magazine about
Marx & Marriage. After reading it I decided to cut my husband some slack
and to stop swooning over the "Titanic", "Bridges", "English" type movies.
Although, just because he "shows me he loves me" by taking the trash and
recycleables out faithfully, and keeping everything mechanical around the
house in good repair, doesn't mean he can rest on those laurels...
Women still need to be romanced. They thrive on it. They need to be
whisked away from the everyday: work, laundry, carpooling, dusting,
preparing meals the for kids who inhale food, and so on. Like a flower
needing water and sun, we need TLC... Need an idea? Get a big blanket,
a bottle of wine, some cheese and crackers, and take a trip to the beach,
or go apple picking first then find a field where you can be alone...
listen to the woman you love, tell her she's the most beautiful, most
important woman in the world... Then she'll pose naked waiting for you
to draw her (a la "Titanic"), stand by a bridge looking seductive waiting
for you to photograph her (a la "Bridges"), or lie down in a cave waiting
for your return (a la "English").
But, of course, you'll either have drowned ("Titanic"), moved on and
stayed lonely ("Bridges"), or been arrested ("English"). Ain't life
sweet? I've been married 15+ years.
- K a r e n T y r r e l l
VitalCom Public Relations
( ESNUG 302 Item 1 ) --------------------------------------------- [10/98]
Subject: (ESNUG 300 #3) Comments On The Current State Of The Test World
> Here's my take on the current state of the test world: ...
>
> In my opinion, stand-alone fault simulators will not stay for too long in
> the current chip development process. There are several companies that
> use fault simulation as their only manufacturing test tool. For today's
> million gate chips, getting a decent (90%+) stuck-at-fault coverage with
> functional vectors alone is a rather tedious and clumsy process. ...
>
> - Shankar Hemmady
> Guru Technologies Cupertino, CA
From: dchapman@goldmountain.com (Dave Chapman)
Dear John,
Shankar has many good things to say, and I would like to add a little:
1. There have always been two different test requirements: Functional
testing used in development, and go/no-go testing used in production.
It does not seem likely that both needs can be met by the same tools.
2. The one test which confirms whether your design has a chance of working
is this: Set all register bits to 0, then read back; set all register
bits to 1, then read back. Despite much progress over the years, stuck
bits are still the most common type of manufacturing error.
If you cannot perform this test, then I suspect that you cannot test
the device at all.
3. JTAG is the gold standard here. Any proposed testing method should be
(and will be) compared with a comprehensive JTAG solution.
Worst thing about JTAG: It eats silicon like pop corn.
Second worst thing about JTAG: It is not as easy to do right as people
think.
4. BIST is a software concept.
The era of building stuff and hoping that it works is long gone, and the era
of building stuff and hoping that the test guys will figure a way to verify
operation is rapidly fading. TODAY, A TEST STRATEGY MUST BE PART OF THE
INITIAL DESIGN. Everybody already knew that, right?
- Dave Chapman
Goldmountain
---- ---- ---- ---- ---- ---- ----
From: Duncan M. (Hank) Walker <walker@cs.tamu.edu>
John,
Shankar's message was nice, but had one glaring ommission: IBM TestBench.
This is the grandfather of all the other tools, and had the capabilities he
mentioned at earlier dates. It is primarily an internal tool, but IBM does
have quite a few external TestBench customers, they have a booth at ITC,
etc. IBM has also used logic BIST in production. The S/390 processor
chips have about every form of test known.
- Duncan M. (Hank) Walker
Texas A&M University
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
From: rp00280@email.sps.mot.com (Morgan Monks)
> Shankar, Very good comments on the EDA Tools in ESNUG.
>
> I work in a Standard Cell Foundry at Motorola Semi. My team has developed
> a Memory BIST Tool set which inserts Memory BIST into the netlist at the
> Verilog Netlist level. Your comments that BIST should be like scan is what
> my team did. We find this approach is accepted by the customers.
>
> - Morgan Monks
> Motorola Semiconductor Products
From: Shankar Hemmady <hemmady@gurutech.com>
Morgan, My personal opinion is that both the scan tools and the BIST tools
should be avialable at the same level(s). Some have succeeded in doing
this at the RTL level with some limited correlation between extra test logic
and extra coverage. Many have been successful at the netlist level.
Question: don't you find the netlist overwhelmingly large at the netlist
level these days? Do you still prefer to operate at the netlist level for
all forms of testability?
> In a way I would like to see a commerical vendor adopt this approach to
> insert at the netlist level because this would allow other Motorola groups
> to purchase the software. How many embedded memories have you worked with
> in MEMORY BIST ? We are currently doing 6 million plus transistor chips
> with 200+ embedded memories.
My usage of memory BIST is limited to only a couple of multimedia chips
which had a few embedded memories. I know of some people who have used
it in a lot more complex situations. Yours seem to top the list.
Did you share the BIST logic among memories of similar sizes? How did the
team and the management perceive the so-called BIST overhead requirements?
- Shankar Hemmady
Guru Technologies Cupertino, CA
---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ----
Shankar Hemmady <hemmady@professionals.com> writes:
> Question: don't you find the netlist overwhelmingly large at the netlist
> level these days? Do you still prefer to operate at the netlist level for
> all forms of testability?
From: "Morgan Monks (rp00280)" <rp00280@email.sps.mot.com>
Shankar,
Working with the netlist is a large database -- but since I am in a foundry
the customer won't share the RTL files since it's his IP. Also we wanted to
create a system where the BIST logic stays out of the designer's hair as
long as possible.
I use Synopsys Design Compiler to do the "weaving" of the BIST logic
into the Gate level netlist. I also have a couple of tricks which make this
go quickly.
I always stay at the netlist level. It keeps our customer's IP on his site
and I don't change any of the hierarchy in doing the weaving. This approach
also lets me change the BIST and be independent of the customer's design.
This is good since many of my customers will re-use the RTL and if BIST had
been inserted I would have to keep this updated in the field.
Concerning your question of "Did you share the BIST logic among memories of
similar sizes?" -- We have a single controller for all the BIST memories.
Each BIST ram has a "wrapper" or "collar" which contains the BISTregister
and BIST RAM. The customer instiantiates a BIST ram which has all the
BIST inputs tied off so the customer only makes system connections to the
RAM. During the weave the weaving tool removes the ram and inserts a new ram
which has the BISTregister contected to the RAM and new BIST ports. Since
the old RAM wrapper and new are the same port for the customer nothing
changes as far as the customer's logic is concerned.
> How did the team and the management perceive the so-called BIST overhead
> requirements?
My overhead is 5% or less. So far this has been recieved very well. Of
course, as I go to larger number of RAMS the overhead increases since the
BISTregister grows.
I will give a paper on this topic at DesignCon 99 in Feburary 3, in
Santa Clara. (Look at www.designcon.com and search for "schedule".)
- Morgan Monks
Motorola Semiconductor Products
( ESNUG 302 Item 2 ) --------------------------------------------- [10/98]
Subject: (ESNUG 292 #4 301 #3) My 12-Day Runaround W/ The Synopsys Hotline
> ... My point to all of this is that the hotline did not help me in my
> critical time EVER. It's the same each time. I spend an hour explaining
> the situation and it never resolved. I always find a solution by long
> hours of trial and errors. Please follow the dates on this issue. From
> October 1st till today October 13 and it is not resolved! ...
>
> The fact that he sent me e-mail yesterday asking more questions, told me
> he *just* started to work on it after 2 weeks. ...
>
> - Ihab Mansour
> XLNT San Diego, CA
From: Ihab Mansour <ihab@xlnt.com>
Hi John,
ESNUG did it again. After reading about the Hotline issues a while back
and especially the response from Vito J. Mazzarino (Synopsys) that he
welcomes feedback, I sent him one about my last experience with the
hotline. I have to give Synopsys management credit here that my issue got
resolved in few hours after I sent the e-mail to them and you on ESNUG. The
moral of the story here is that we need to keep communicating with each
other.
After talking to the manager of the support center, I am planning to send
him feedback every time I do business with the hotline. Hopefully all
good news!!!
- Ihab Mansour
XLNT San Diego, CA
( ESNUG 302 Item 3 ) --------------------------------------------- [10/98]
From: "Charles Klaasen" <klaasen@natlab.research.philips.com>
Subject: How To Keep Logic0 Cells From Being Put On Unconnected Scan Ports?
Hello John,
Since the scan chains in my design are inserted 'outside' Synopsys, I
have unconnected (scan out) ports in my design. After a compile run, DC
connects these unconnected port to logic0. These logic0 cells cause
problems in the rest of the design flow. I can fix this with a simple
DC-script that removes these cells, but I was wondering if I can prevent
the inserting of the logic0's by with some variable or attribute???
- Charles E. Klaasen
Philips Semiconductors Eindhoven, The Netherlands
( ESNUG 302 Item 4 ) --------------------------------------------- [10/98]
Subject: ( ESNUG 300 #5 301 #7 ) Experiences, Scripts, & Benchmarks w/ DC'98
From: Jason Surprise <jmsurpri@ichips.intel.com>
> I just read your recent ESNUG post regarding your findings with DC98.
> Good post. However, I have some concerns with the section of the report
> which talks about set_input_delays on clocks.
>
> In the example that you showed, you are applying a negative delay on the
> clock using set_input_delay -0.82. This, in essence, is changing the
> waveform of the clock, correct. So, your waveform has been changed as
> follows:
>
>
> +--------+ +--------+
> | | | |
> | | | | Before
> | | | |
> --------+ +---------+ +-------
> 0 5 10 15
>
>
> +--------+ +--------+
> | | | |
> | | | | After
> | | | |
> ------+ +---------+ +-------
> -0.82 4.18 9.18
>
>
> So you've just shifted the clock back by 0.82. Looking at your timing
> report, I don't see this shift happening, all I see if the .82 taken
> from the originating clock, but not taken away from the sampled clock.
> Seems like a bug to me.
>
>
> Point Incr Path
> -----------------------------------------------------------
> clock clk (rise edge) 0.00 0.00
> clock network delay (propagated) -0.82 -0.82
> q_reg/CK (DFF) 0.00 -0.82 r
> q_reg/D (DFF) 1.29 0.47 r
> U9/Y (BUFX1) 0.08 0.55 f
> q (out) 0.00 0.55 f
> data arrival time 0.55
>
> clock clk (rise edge) 10.00 10.00
> clock network delay (propagated) 0.00 10.00 <-- This should
> output external delay -8.00 2.00 read -0.82 !
> data required time 2.00
> -----------------------------------------------------------
> data required time 2.00
> data arrival time -0.55
> -----------------------------------------------------------
> slack (MET) 1.45
>
>
> What do you think?
>
> - Jason Surprise
> Intel Hillsboro, OR
From: sgolson@trilobyte.com (Steve Golson)
Jason,
Not exactly. What I did was this:
create_clock -period 10 find(port,CLK)
set_clock_skew -propagated find(clock,CLK)
set_input_delay -3.82 -clock CLK find(port,CLK)
So I started with an ideal clock that rises at 0 and falls at 5. Then
I shifted the clock back by 3.82. However this is a *propagated* clock,
which means all the real back-annotated delays on the clock network will
be used. In my example the delay from the CLK input to the source flop clock
pin has 3.00 delay for a total delay of -0.82 (which is what the timing
report shows). The delay from the CLK input to the destination flop will be
different because of skew in the clock network.
I should have picked a better example that had a destination flop rather
than an output.
- Steve Golson
Trilobyte Systems
( ESNUG 302 Item 5 ) --------------------------------------------- [10/98]
From: janick@qualis.qualis.com (Janick Bergeron)
Subject: We BEG YOU To PLEASE Help On Our Cadence Verilog-XL License Problem
John,
We're desperate. REALLY desperate. We BEG YOU to PLEASE help us on our
Cadence Verilog-XL FLEXlm licensing problem! PLEASE!
Earlier this month I posted it on comp.cad.cadence as a description of a
licensing problem when running Verilog XL on Solaris 5.6. I was told that
updating to 97AQSR5 is required for Sol5.6. I did but to no avail.
Verilog-XL refuses to connect to the license daemon but works fine under
Sol 2.5.1... The following are transcripts of everything I tried. The text
between "[]" are my own comments.
Version of the OS we are using [XL and the license server are both running
on the same machine "speedy"]:
janick@speedy % cd /tools/adm/cadence
janick@speedy % uname -a
SunOS speedy 5.6 Generic_105181-06 sun4u sparc SUNW,Ultra-4
I make sure my DEAMON line is correct [it's ok]:
janick@speedy % grep DAEMON key
DAEMON cdslmd /tools/home/cadence/97A/tools.sun4v/bin/cdslmd
I verify that the path to the vendor deamon is correct and check its version
at the same time [5.12]:
janick@speedy % lmver /tools/home/cadence/97A/tools.sun4v/bin/cdslmd
lmver - Copyright (C) 1989-1998 Globetrotter Software, Inc.
FLEXlm 5.12 (libmgr_as.a), Copyright (C) 1988-1997 Globetrotter...
FLEXlm 5.12 (libmgr_s.a), Copyright (C) 1988, 1997 Globetrotter...
FLEXlm 5.12 (liblmgr.a), Copyright (C) 1988-1997 Globetrotter...
I check the version of the lmgrd that come with 97AQSR5 [5.12 too]:
janick@speedy % setenv CDS_HOME /tools/home/cadence/97A
janick@speedy % lmver $CDS_HOME/tools.sun4v/bin/lmgrd
lmver - Copyright (C) 1989-1998 Globetrotter Software, Inc.
FLEXlm Copyright 1988-1996, Globetrotter Software, Inc.
FLEXlm 5.12 (libmgr_s.a), Copyright (C) 1988, 1997 Globetrotter...
FLEXlm 5.12 (liblmgr.a), Copyright (C) 1988-1997 Globetrotter...
I try to manually start the license server [cdslmd can't talk to lmgrd]:
janick@speedy % $CDS_HOME/tools.sun4v/bin/lmgrd -t 20 -c key
10/20 10:01:31 (lmgrd) -----------------------------------
10/20 10:01:31 (lmgrd)
[...]
10/20 10:01:31 (lmgrd) FLEXlm (v5.12) started on speedy (Sun)
(10/1998)
10/20 10:01:31 (lmgrd) FLEXlm Copyright 1988-1996, Globetrotter...
10/20 10:01:31 (lmgrd) World Wide Web: http://www.globetrotter.com
10/20 10:01:31 (lmgrd) License file: "key"
10/20 10:01:31 (lmgrd) Starting vendor daemons ...
10/20 10:01:31 (lmgrd) Started cdslmd (internet tcp_port 60656
pid 2620)
10/20 10:01:31 (cdslmd) ----------------------------------
10/20 10:01:31 (cdslmd)
[...]
10/20 10:01:31 (cdslmd) Server started on speedy for: 100
10/20 10:01:31 (cdslmd) 21900 26000 CWAVES
10/20 10:01:31 (cdslmd) SimVision UET VERILOG-XL
10/20 10:01:31 (cdslmd) VXL-TURBO VXL-VCW VXL-VET
10/20 10:01:31 (cdslmd) VXL-VLS VXL-VRA
10/20 10:01:31 (cdslmd) Vendor daemon can't talk to lmgrd (Cannot
read data from license server (-16,287:22) Invalid argument)
10/20 10:01:31 (lmgrd) Vendor daemon died with status 240
10/20 10:01:31 (lmgrd) Since this is an unknown status, lmgrd will
10/20 10:01:31 (lmgrd) attempt to re-start the vendor daemon.
10/20 10:01:31 (lmgrd) REStarted cdslmd (internet tcp_port 60658
pid 2621)
[...]
Message repeated several times as lmgrd attempts to restart cdslmd. It
eventually gives up. ....
10/20 10:01:32 (cdslmd) Vendor daemon can't talk to lmgrd (Cannot
read data from license server (-16,287:22) Invalid argument)
10/20 10:01:32 (lmgrd) Please correct problem and restart daemons
I now kill the deamon:
janick@speedy % lmdown -c key
lmdown - Copyright (C) 1989-1998 Globetrotter Software, Inc.
Port@Host Vendors
1) 15280@speedy Unknown (pre-v6 lmgrd)
Are you sure (y/n)? y
Shut down FLEXlm server on node speedy
1 FLEXlm License Server shut down
10/20 10:01:40 (lmgrd) SHUTDOWN request from janick at node speedy
10/20 10:01:40 (lmgrd) lmgrd will now shut down all the vendor daemons
I consult the FAQ from FlexLM [it does not help]:
Q8.5 Vendor daemon can't talk to lmgrd
This means a pre-v3.0 lmgrd is being used with a v3.0+ vendor daemon.
[That's not the case here] Simply use the latest version of lmgrd (MUST
be a version equal to or greater than the vendor daemon version). [It's
already the same but let's try a newer version (6.1)]
(Rare): This can also happen if TCP networking doesn't function on the
node where you're trying to run lmgrd. [Everything else works fine]
Q8.6 Vendor daemon died with status n...Since this is an unknown
status, lmgrd will attempt to re-start the vendor daemon.
Often this is accompanied by printing a port number which increases
over and over. lmgrd tries to start the vendor daemon using the DAEMON
line in the license file, which looks like:
DAEMON demo /usr/bin/demo
The /usr/bin/demo is a path to a binary, and there's something wrong
with either the path or the binary itself. One way to debug this is to
run vendor daemon directly, using this path, and problem then becomes
more apparent. [That path is fine]
I try using a more recent version of lmgrd [6.1, it works!]:
janick@speedy % lmver /tools/lib/lmgrd
lmver - Copyright (C) 1989-1998 Globetrotter Software, Inc.
FLEXlm Copyright 1988-1998, Globetrotter Software, Inc.
FLEXlm 6.1 (libmgr_s.a), Copyright (C) 1988, 1997 Globetrotter...
FLEXlm 6.1 (liblmgr.a), Copyright (C) 1988-1997 Globetrotter...
janick@speedy % /tools/lib/lmgrd -t 20 -c key
10:02:03 (lmgrd) ------------------------------------------
[...]
10:02:03 (lmgrd) FLEXlm (v6.1) started on speedy (Sun) (10/1998)
10:02:03 (lmgrd) FLEXlm Copyright 1988-1998, Globetrotter Software, Inc.
10:02:03 (lmgrd) US Patents 5,390,297 and 5,671,412.
10:02:03 (lmgrd) World Wide Web: http://www.globetrotter.com
10:02:03 (lmgrd) License file(s): key
10:02:03 (lmgrd) lmgrd tcp-port 15280
10:02:03 (lmgrd) Starting vendor daemons ...
10:02:03 (lmgrd) Started cdslmd (internet tcp_port 60680 pid 2637)
10/20 10:02:03 (cdslmd) lmgrd version 4, cdslmd version
WHOA! Here's something odd: cdslmd thinks it's talking to a lmgrd
version 4 !?!?!?!?!
10/20 10:02:03 (cdslmd) -----------------------------------
[...]
10/20 10:02:03 (cdslmd) Server started on speedy for: 100
10/20 10:02:03 (cdslmd) 21900 26000 CWAVES
10/20 10:02:03 (cdslmd) SimVision UET VERILOG-XL
10/20 10:02:03 (cdslmd) VXL-TURBO VXL-VCW VXL-VET
10/20 10:02:03 (cdslmd) VXL-VLS VXL-VRA
I then try to run Verilog [it STILL fails]:
janick@speedy % verilog list.v
VERILOG-XL 2.5.20 Oct 20, 1998 10:02:27
[...]
-------- Qualis Design Corporation Verilog-XL --------
(use $list_pli_pkgs to display installed PLI packages)
Compiling source file "list.v"
Error! ERROR (LM -15): license server ("speedy")
communication error - try longer timeout (run
'lic_error -15' for more information). Feature
is VERILOG-XL [Verilog-LICENSE]
Exit 1
The original binary version shipped with 97AQSR5 (without PLIs) failed, too.
I try from a Sol 2.5.1 machine [it works]:
janick@jaguar [~/verilog]% uname -a
SunOS jaguar 5.5.1 Generic_103640-21 sun4m sparc SUNW,SPARCstation-10
janick@jaguar [~/verilog]% verilog list.v
VERILOG-XL 2.5.20 Oct 20, 1998 10:35:44
[...]
-------- Qualis Design Corporation Verilog-XL --------
(use $list_pli_pkgs to display installed PLI packages)
Compiling source file "list.v"
Highest level modules:
LIST
This version of Verilog-XL includes:
Design Acceleration SST Extensions version 5.3
Veritools Undertow Interface version 6.0.9
Veritools Interactive Tool Interface version 2.2.8
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.4 secs to compile + 0.2 secs to link + 0.0 secs in simulation
End of VERILOG-XL 2.5.20 Oct 20, 1998 10:35:48
I manually check that licenses can be checked out using lmdiag shipped with
the Cadence software [they all work :-(]:
janick@speedy % $CDS_HOME/tools.sun4v/bin/lmdiag -c key
lmdiag - Copyright (C) 1989-1997 Globetrotter Software, Inc.
FLEXlm diagnostics on Tue 10/1998 10:02
-----------------------------------------------------
License file: key
-----------------------------------------------------
10/20 10:02:43 (cdslmd) OUT: "100" janick@speedy [lmdiag]
"100" v4.400, vendor: cdslmd
License server: speedy
floating license starts: ..., expires: ...
10/20 10:02:43 (cdslmd) IN: "100" janick@speedy [lmdiag] (used: 0:00)
This license can be checked out
[...]
Enter <CR> to continue:
10/20 10:02:51 (cdslmd) OUT: "VXL-VRA" janick@speedy [lmdiag]
"VXL-VRA" v2.300, vendor: cdslmd
License server: speedy
floating license starts: ..., expires: ...
10/20 10:02:51 (cdslmd) IN: "VXL-VRA" janick@speedy [lmdiag] (used: 0:00)
This license can be checked out
AAAAAaaaaaarrrrrrggggghhhhhhhhh! *help*
- Janick Bergeron
Qualis Design Lake Oswego, OR
( ESNUG 302 Item 6 ) --------------------------------------------- [10/98]
Subject: ( ESNUG 301 #10 ) Anyone, Anywhere Have An "ied" That Runs On SUNs?
> Several years ago (through the wonders of ESNUG), I was introduced to a
> very handy little program called "ied". ied sits between you and any
> stdin/stdout program, and provides ksh-like command line history and
> editing. It works on most everything, including ftp, & (ta-da!) dc_shell.
>
> Well, I changed jobs from an all-HP shop (HP) to an all-SUN shop (Cerent),
> and discovered, to my horror, that ied doesn't seem to exist on SUN.
> So much for, "everything runs on SUN".
>
> I've tried the Solaris news group, but without success. I thought that,
> since I heard about ied on esnug originally, and since many ESNUG'ers
> are probably multi-platform, perhaps someone in the esnug community
> can point me at an ied equivalent for SUN (or LINUX - since then I might
> be able to get the source code and compile it on SUN!).
>
> - Paul Zimmer
> Cerent Corporation
From: Don Reid <donr@hpcvcdo.cv.hp.com>
John,
This is not an official HP answer, I am just as IC guy, but I remember when
and where ied came from. HP licensed the ksh source directly from AT&T in
order to include several parts of it into a CAD tool shell. Based on this
someone produced ied as a stand alone program. You are not likely to find
it outside HP.
I agree that ied is a very usefull tool, I have many programs aliased to run
it with text based tools.
- Don Reid
Hewlett Packard Corvallis, OR
---- ---- ---- ---- ---- ---- ----
From: Ngo Bach Long <bach@pc3.eecg.utoronto.ca>
John,
There's a similar program called "ile", written by Robert Pendleton.
Here's an excerpt from the man page:
ile - An input line editor for UNIX (Input Line Editor)
ile [-file/name] [prog arg1 arg2 ... argn]
The ile program is an input line editor that provides an
easier to use history mechanism than the shell.
The ile program can be run as a simple shell around any
program. It gives any program an input line editing and a
history mechanism. It can also be run around your favorite
shell. When run around the shell ile records the input to
programs as well as input to the shell in its history
buffer.
A Linux port (with source) is available at
http://sunsite.unc.edu/pub/Linux/utils/terminal/ile-linux.tgz
- Ngo Bach Long
University of Toronto
---- ---- ---- ---- ---- ---- ----
From: Andrew Maccormack <andrewm@bristol.st.com>
John,
There is a shell-mode inside the most versions of Xemacs and GNU Emacs that
you can run any program inside, and can use sophisticated command line
editing with. On the smaller side, there is a program like the "ied" you
describe called fep that stands for "front end processor". I believe that
it has both Emacs-like and vi-like modes.
You can find fep by searching at www.shareware.com, or any SunSite FTP site,
in the Linux tree under utils/shell/fep-9612.tar.gz.
- Andrew R MacCormack
SGS-Thomson Microelectronics
---- ---- ---- ---- ---- ---- ----
From: Ken Goldman <kgold@watson.ibm.com>
John,
Even before I finished reading this post, I was thinking emacs.
You can pop a shell in an emacs window (any shell, csh, ksh, dos,
...). Since it's an emacs buffer, you automatically get scrolling,
editing, syntax coloring, and so on. And command history is built in.
I use it a lot when running DOS command line programs, because the DOS
shell does not have a scroll bar, and is limited to 80 characters.
Give it a try. It's free and available on most every platform.
- Ken Goldman
IBM Watson
---- ---- ---- ---- ---- ---- ----
From: Jonathan Liu <jonathan@ikos.com>
John,
In response to Paul Zimmer's inquiry in ESNUG 301 regarding "ied" for Sun
Workstation. I have used a tool called "ile" on Solaris which has similar
functionality only it is more like csh or tcsh rather than like ksh.
(I think "ile" probably stands for Interactive Line Editor.)
I believe it's available as freeware on the web someplace. If you can't
find it, I may be able to ask around some more to see where it came from.
- Jonathan Liu
Ikos Systems
( ESNUG 302 Item 7 ) --------------------------------------------- [10/98]
Subject: (ESNUG 301 #5) Synopsys Seems To Give Inconsistant Timing Reports?
> We are building a 500k gate chip with LSI. When we do top level timing
> reports we see may clk-to-q times of more than 3ns for nets with only a
> fanout of 2. We are using the "enclosed" mode for wireloading, but these
> nets are contained within small blocks. When we time the enclosing block
> the exact same nets have delays less than 0.5ns. (?) ...
>
> clock pad/clk (rise edge) 0.00 0.00
> clock network delay (ideal) 0.00 0.00
> core/atm/at_learn0/ln_fsm/sa_rd_req_reg/CP (FD2QC) 0.00 0.00 r
> core/atm/at_learn0/ln_fsm/sa_rd_req_reg/Q (FD2QC) 3.69 3.69 f ?
> core/atm/at_learn0/ln_fsm/sa_rd_req (net) 2 0.00 3.69 f
>
> - Greg Brookshire
> Peracom
From: Oren Rubinstein <oren@gigapixel.com>
John,
The classical cause for high CLK->Q delays is a slow transition on the
clock. This can happen when you forget to set_drive 0
In this case, it seems you're driving all the flops directly from the clock
input pad.
There should be a fake clock driver which lateer gets replaced by the clock
tree, or something like that, and the fake driver should have infinite
drive. If you don't have one of those, you can create it yourself:
module clk_drv(clk_in, clk_out);
input clk_in;
output clk_out;
parameter TREE_DELAY = 3.0; // Or whatever you think it will be
assign #TREE_DELAY clk_out = clk_in;
endmodule
Then, in the top level, you insert clk_drv in the clock, between the pad
and the flops, and you can do the following:
1. When you load the top level, make sure Synopsys can't see the fake
driver, so it treats it as a black box.
2. Do a create_clock on the clk_drv/clk_out pin, and
set_drive 0 clk_drv/clk_out
Hope this helps.
- Oren Rubinstein
GigaPixel Santa Clara, CA
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From: Scott Evans <scott@NPLab.Com>
John,
You might want to add -trans to your timing reporting and check to see if
the transition times are the cause for the difference. Another thing to
do, if your library allows it, is
report_delay_calculation -from
core/atm/at_learn0/ln_fsm/sa_rd_req_reg/CP
-to core/atm/at_learn0/ln_fsm/sa_rd_req_reg/Q
It will give you all the details of where it comes up with the delay
numbers.
One other item to look at is the loading on the net.
report_net -verbose -connections core/atm/at_learn0/ln_fsm/sa_rd_req
should provide that.
- Scott Evans
NeoParadigm Labs San Jose, CA
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From: Bret Bersack <bret_bersack@mint-tech.com>
John,
We had a similar problem that was caused by the clock transistion time.
Even though the clock network was "ideal", the clock driver transition
time was being used! You can check this by adding the "-transition_time"
switch to the report_timing command.
The fix is: set_clock_transition 0.0 find(clock, "pad/clk");
- Bret Bersack
Mint Technology Billerica, MA
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From: Ajoy Aswadhati <ajoy@lucidsolutions.com>
John,
It is likely that Greg forgot to specify set_drive of 0 (infinite drive) on
the clock port.
dc_shell> set_drive 0 clock
Assuming clock is a port on the module for which he is doing the timing
analysis.
If the drive strength of the clock port is not specified correctly the clock
signal will have large transition times because of the high fanout
associated with clock networks. This in turn is reflected in big delay seen
in the clock->q time for the flops connected to this clock port.
The command 'report_delay_calculation' can be used to figure out how the
delay values of timing arcs inside a cell are computed. If the 'clock'
signal is driven by a pad or buffer then the buffer or pad should have a
high drive strength specified.
- Ajoy Aswadhati
Lucid Solutions
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From: [ A Synopsys CAE ]
Hi John,
Keep me anonymous, thanks.
The usual culprit for this is heavy loading on the clock net, not the
Q output of the register. The result is a large transition time on the CLK
pin, causing a large transition on the Q pin. The report_delay_calculation
-from CLK -to Q command should be of some help here. This is common in
pre-layout designs where you have a large fanout on the clock because you
haven't inserted clock buffers yet. If this is Greg's case, you can do a
set_clock_transition on the clock that will set the transition all along
the clock network. Set it to some reasonable expected value.
- [ A Synopsys CAE ]
---- ---- ---- ---- ---- ---- ----
From: Tom Cruz <tomcruz@us.ibm.com>
Hi Greg - did you try looking at the slew rate of the clock input to your
storage element (flip-flop to you - latch to me).
We had a similar problem on a previous chip - a timing report from the top
level of the chip showed a 5 ns clock to Q delay but when changing to a
lower level design we got the correct clock to Q delay.
In our case, the slew rate of the clock into the storage element was long
due to the lack of a clock tree. In other words, the clock root book was
driving too many loads.
- Tom Cruz
IBM Networking Hardware Division
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From: Greg Brookshire <gbrookshire@peracom.com>
John,
We discovered our problem. Our synth person was running timing on the top
level of our chip which included pads and no clk tree. The set drive 0 of
course did not propagate through a pad cell like he thought it might so our
internal clk net had a horrible transition time which created the clk-q
times we saw. These ESNUG responses helped a lot.
- Greg Brookshire
Peracom Cary, NC
( ESNUG 302 Item 8 ) --------------------------------------------- [10/98]
Subject: (ESNUG 301 #6) Exemplar Challenges Non-Compliant-To-VHDL'93 VSS
> One of our customers popped up with a problem that was so outlandish I
> scarcely believed it. We delivered them a virtual component (aka "core")
> written in VHDL RTL version 1993. After a few days they came back
> and said their VSS system could not process it because *it only comprehends
> VHDL 1987*! They were given these systems on very favorable terms by
> Synopsys as an inducement to by other Synopsys software. The customer did
> not want to use a beta version of 1993 VSS that Synopsys has for the
> obvious reasons of nervousness, and they could not switch to Model Tech
> because they were too far down the road with the rest of their system in
> VSS. Is this for real? Did Synopsys really do that to them?!?!
>
> - Frederick Hinchliffe
> Technical Data Freeway Concord, MA
From: scott.winick@exemplar.com ( Scott R. Winick )
Hello John -
I'll bet dollars to doughnuts that Exemplar Logic's Spectrum can handle
Fred's original virtual component design (in VHDL 93) and produces results
comparable (say +/- 10%) of Synopsys. In fact, I'd even like to provide
the software and/or and AE to try and do just that. Interested? Let me
know if so and what ASIC library we'd need to target.
- Scott R. Winick
EXEMPLAR LOGIC Lancaster, MA
( ESNUG 302 Item 9 ) --------------------------------------------- [10/98]
From: [ Curious Minds ]
Subject: Seeking Lessons Learned -- Is VERA A Good Tool For Verification ?
Hi John,
I am looking for lessons learned from someone who has used VERA in the past.
Our full-chip Verification environment has Diag that issues commands to the
HW Abstract Layer which spawns Verilog simulation. The Verilog side then
forks, and execvp to execute a child process to run C simulation of C
Reference models.
During the course of C simulation, stimulus and responses around each module
are envelope-captured. The stimulus are sent to an IPC (Interprocess
Communication) FIFO to be applied to the Verilog counterpart. The responses
are sent to another IPC FIFO to be compared to that of the Verilog
counterpart. The Verilog and C sides are run in parallel and handshake thru
semaphore and shared memory.
I have two questions of which answers would help us in evaluating the tool.
First, what is your detailed lesson you learn from using VERA in your
environment. Any caveat and pitfall of the tool contrary to mktg claim ? How
does VERA stack up against Specman ?
Second, does anyone have a similar environment as ours and use VERA as a
cosimulator between C and Verilog sides successfully ? If yes, is there any
catch ? How are its RPC (Remote Procedural Call) and IPC ? Please keep
me anonymous because we're looking into a possible purchase of VERA.
- [ Curious Minds ]
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