Editor's Note: It's amazing how powerful sex is. As many of you know,
I live on a sheep farm about 45 minutes west of Boston. Of the many
animals on the farm, we have two rabbits, one female that's grey, and
an orange male rabbit. We keep them in two separate cages about 100
feet from each other. They're both very tame rabbits. About six weeks
ago, the female escaped from her cage overnight. To our surprize the
next morning, she came running right up to us and hoped happy circles
around us. We easily caught her. This happened again a few days later.
We wondered why she just didn't disappear into the woods having nothing
to stop her? Huh? It turned out that when people weren't around, she
would just hang around the outside of the male rabbit's cage all day! And
when we let out the male rabbit, he would amorously chase & annoy the
cats and then hang around the outside of the female's cage all day! So,
now when any of us go out in the back yard, we're met by a happy, kind
of silly looking rabit who just gleefully hops in small circles around
our feet. And sometimes the cats look harassed. It's kind of weird,
funky, funny & most definitely Spring thing. Peace, man! :^)
- John Cooley
the ESNUG guy
( ESNUG 287 Item 1 ) ---------------------------------------------- [4/98]
Subject: ( ESNUG 286 #1 ) Verilog, VHDL, NT, Unix & Ron Collett's Bad Advice
Hi John-
> Thought I'd pass along some thoughts after reading your article "From
> Beirut to Bosnia" posted on techweb.cmp.com as I was searching for
> references to Collett International (Ron Collett).
>
> Before coming to Systems Science, I worked for Zycad over 6 years. Ron
> was contracted and, as a stipulation, would speak to the company about his
> vision of the simulation-environment-of-the-future. Ron assuredly promoted
> the demise of Verilog in favor of the upcoming contender, VHDL. On that
> advice, Zycad's executives based the future of the company on a hardware
> engine (ViP) designed to digest raw VHDL in preparation to capture the VHDL
> market which was prophecized to take over by 1996. Because of this huge
> R&D investment, Zycad was fatally crippled and by the time they backtracked
> to update the successful gate-level simulator (Paradigm XP, Lightspeed),
> they had already lost momentum and could no longer invest in the resources
> necessary to regain lost ground.
>
> After my first experience hearing Ron's presentation, I was always
> very skeptical of his market analysis. In 1996, it hit directly in my
> realm when he avoided the VHDL-versus-Verilog topic and began to harp on
> the demise of the workstation platform in favor of NT.
>
> - Clay Degenhardt
> Systems Science
From: "Brian LaPorte" <Brian.LaPorte@xilinx.com>
John,
Regarding Clay Degenhardt's note on the demise of Zycad, which bet its
strategy on Ron Collett's advice: Any company that formulates its strategy
based on a market analyst's vision versus its customers' vision deserves
the fate it gets.
- Brian LaPorte
Xilinx
---- ---- ---- ---- ---- ---- ----
From: "Gabe Moretti" <gmoretti@ingr.com>
John,
I take issue with some statements and conclusions offered by Clay Degenhardt
on ESNUG Post 286 with respect to the reasons for the demise of Zycad
through its ViP product. ViP was not the victim of a Verilog vs VHDL market
struggle, but of the following facts:
1) ViP was a very early exploration on "how to" and most importantly
"how not to" accelerate VHDL execution.
2) ViP's architecture was the antithesis of the KISS principle.
3) ViP machines were extremely difficult to use.
4) ViP machines never came close to provide a return on investment even
to die hard VHDL users.
Some of us like conflict: Verilog vs VHDL, UNIX vs NT. I prefer appropriate
cuddly coexistence. Economics determines the survivors (some would call
them winners).
- Gabe Moretti
Chair VHDL International
VP Engineering, VeriBest, Inc.
---- ---- ---- ---- ---- ---- ----
From: plaberge@micronpc.com ( Paul LaBerge )
Hi John,
I'm in agreement with Clay's foresight in the following statement :
"The result is the current situation we're seeing of the hybrid environment:
A workgroup of users working on NT platforms with one or 2 Sun workstations
acting as servers for "serious work". " This is exactly the environment we
have setup at Micron. Of course being a PC company it's not without some
bias, but the PC platform and NT 4.0 has worked extremely well for us.
We've done 6 or so 200+ gate asics using ModelSIM and PC based tools. We
use workstations for Synopsys along with some other tasks (bfl compiler runs
on UNIX only). The mixed environment poses some process problems, but
we've successfully integrated the design environment to take advantage of
both platforms. It also allows us to use either platform quite easily.
It also allows our engineers to chose. Some are more comfortable using one
platform vs the other. I've also found out that it is just a preference in
many cases. To argue one plaform over the other tends to turn into a heated
debate at times. It's like almost like talking about religion or
politics :-) Each side offers arguments and opinions, but neither side
really changes their mind.
- Paul LaBerge
Micron
( ESNUG 287 Item 2 ) ---------------------------------------------- [4/98]
Subject: ( ESNUG 286 #11 ) Seeking Many Decimal Digits Delays On Inputs
> I was wondering if anyone knows an easy way to automatically set the drive
> at each pin such that I am assured that there is, say, 0.5ns at all inputs.
> The set_drive command will work, but I need to know the capacitance at
> each input port in order to set each pin's drive correctly, e.g. set_drive
> <0.5ns/capacitance> <input_port>. The problem is knowing each input's
> capacitance. I've tried to get the capacitance attribute by using the
> 'get_attribute' command, unsuccessfully. I finally wrote a Perl script
> to create a set of set_drive commands, based on a report using the
> 'report_net' command. The problem with that is, the resolution is only
> to 2 decimal places (load field):
>
> Net Fanout Fanin Load Resistance Pins
> ------------------------------------------------------------
> INPUT_1 1 1 0.01 0.00 2
> INPUT_2 1 1 0.01 0.00 2
>
> "Load" here may be 0.0149 or 0.0101 - so you don't generate a very precise
> drive value this way. I don't want to change my lib input capacitances
> from pF to fF right now. That would certainly help in the report. Any
> other ideas?
>
> - Chuck Bellman
> Motorola NCSG SemiCustom
From: "Russell Ray" <rray@msai.mea.com>
John,
Since he already mentioned that he used the get_attribute command, I'm not
sure if he has tried this, he probably has.
I have had to use this for other things, too, and have found it to be a
pain. But, the only way to get all the digits in the library file is to
either have the library file (which most of us can't get) or use the
get_attribute command.
I have used the report_lib, get_attribute, and perl to create the scripts I
wanted. The report_lib piped to a file so that I would have a list of all
the library cells (sounds like you already know these). Then I use perl to
create a dc script that would run get_attribute on each of the cells and
their input pins. All dc_shell output goes to a file. Then I use another
perl script to process the output of dc_shell to create my script (in his
case, the set_drive script).
It is all very messy and time consuming, but it does work.
- Russell Ray
Mitsubishi Semiconductor Durham, NC
---- ---- ---- ---- ---- ---- ----
From: Scott Evans <scott@NPLab.Com>
John,
You may want to try report_net -verbose -connections. An example:
Connections for net 'ck$ck_gen$n1531':
pin capacitance: 0.063
wire capacitance: 0.170708
total capacitance: 0.233708
wire resistance: 0.101727
number of drivers: 1
number of loads: 5
number of pins: 6
Driver Pins Type Pin Cap
------------ ---------------- --------
ck$ck_gen$U427/O Output Pin (INV1L) 0
Load Pins Type Pin Cap
------------ ---------------- --------
ck$ck_gen$count4_reg_4/SEL Input Pin (DFZN) 0.0126
ck$ck_gen$count4_reg_3/SEL Input Pin (DFZN) 0.0126
ck$ck_gen$count4_reg_2/SEL Input Pin (DFZN) 0.0126
ck$ck_gen$count4_reg_1/SEL Input Pin (DFZN) 0.0126
ck$ck_gen$count4_reg_0/SEL Input Pin (DFZN) 0.0126
It provides a lot more detail.
- Scott Evans
NeoParadigm Labs San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: David Cassetti <david.cassetti@tempe.vlsi.com>
John,
You might want to read Solvit article synth-022860.html. The gist of it
is, you can do something like:
set load 100000 your_input_port
set drive .000005 your_input_port
This will give you a delay of 0.5 ns
- David Cassetti
VLSI Technology Tempe, AZ
---- ---- ---- ---- ---- ---- ----
From: Paul Fletcher <paulf@chdasic.sps.mot.com>
John,
Give this a try, I have done some of this type of work to add constraints
to an existing library to get better synthesis results, so I new how to
get these values.
T_L = cdr1synPwcshV300T125
remove_varilable capacitance_attribute > /dev/null
wild = "*" /* used so wild carding does not look like a "C" comment */
_DRIVE = "1" /* all 1 x drive cells */
cap_attr = 0.0 /* make sure this is a float */
foreach(cell_name, find(cell,T_L + "/" + wild + _DRIVE) {
pinlst = filter(find(pin,cell_name + "/" + wild), "@port_direction ==in") > /dev/null
echo cell_name pinlst
foreach(pinn,pinlst) {
list pinn
cap_attr = get_attribute(find(pin,cell_name + "/" + pinn) capacitance)
list cap_attr
}
}
You can remove the echo and list commands and add commands to use the data
this returns. Here is an example of what the script returns:
cdr1synPwcshV300T125/sdffps_1 {sb, d, ck, sdi, se}
pinn = "sb"
Performing get_attribute on port 'sb'.
capacitance_attribute = {0.015935}
pinn = "d"
Performing get_attribute on port 'd'.
capacitance_attribute = {0.010037}
pinn = "ck"
Performing get_attribute on port 'ck'.
capacitance_attribute = {0.006111}
pinn = "sdi"
Performing get_attribute on port 'sdi'.
capacitance_attribute = {0.007052}
pinn = "se"
Performing get_attribute on port 'se'.
capacitance_attribute = {0.010471}
Hope this helps.
- Paul Fletcher
Motorola Chandler, AZ
---- ---- ---- ---- ---- ---- ----
From: "Stickel, Tedd K" <Tedd.Stickel@unisys.com>
John -- to characterize library timing I've used a large set_load on
all inputs, say 5000pF, and then a small set_drive, say .0001 on those
same inputs. The large set_load washes out any intrinsic pin C.
- Tedd Stickel
Unisys
( ESNUG 287 Item 3 ) ---------------------------------------------- [4/98]
Subject: DEC, Intel, StrongARM, Cadence Spectrum Services & The Alpha Chip
> The most recent rumor about Cadence Spectrum antics really made me laugh!
> Before DEC was bought out by Compaq, DEC & Intel were at loggerheads about
> the technology used in the DEC Alpha chip. How the conflict was eventually
> resolved was by Intel buying the Alpha chip, the StrongARM chip, the fab,
> and all the related engineers from DEC for a hefty $700 million. What made
> me laugh was the recent rumor that Cadence Spectrum Services had managed to
> stealthfully hire away the majority of the DEC StrongARM design engineers
> before they were delivered to Intel!
> - John Cooley
> Industry Gadfly
From: [ Jack Harding, CEO of Cadence ]
John, I wish we were that smart. The StrongARM team called us.
- Jack Harding
CEO of Cadence
---- ---- ---- ---- ---- ---- ----
From: Julie Staraitis <juls@uofi.hlo.dec.com>
John,
DEC did not actually sell the Alpha chip to Intel. They sold the fab, they
sold all OTHER semiconductor designers, and they cross-licensed the patents.
Intel will sell Alphas back to Digital, and Digital only. There was also
something about 'if DEC doesn't stay with the Alpha platform for at least
7 years, all Alpha employees will have a guaranteed job at Intel.' That
clause may have disappeared with the Compaq deal.
Minor detail to some, but even though I got sold I get to hear the
non-sold go into a tirade every time someone gets that part confused.
- Julie Staraitis
DEC
---- ---- ---- ---- ---- ---- ----
From: Aaron Sakovich <sakovich@hsv.sungardtrust.com>
Hi John,
Just wanted to point out a mistake in your article: you claim that "Intel
bought the Alpha chip" when such is not the case. Intel is being forced to
manufacture Alpha chips for Digital at cut-rate pricing, plus has to buy
Digital's underutilized semiconductor manufacturing plant forcing the delay
of Intel's plant in Texas, plus must pay Digital untold hundreds of
millions of dollars in licensing fees for the technology that they stole
from the Alpha design in the first place.
Digital still owns the Alpha, Samsung is a much larger manufacturer of
Alpha chips than Intel is, and rumors abound regarding at least one more if
not two fabricators coming online.
It is NOT Intel's Alpha chip. It is the only open standard in the industry
unlike the proprietary chips Intel manufactures.
Oh yeah, it's also a heck of a lot faster and was 64 bit 6 years before the
much delayed Merced is supposed to trickle out to developers.
Please consider not repeating Intel's propoganda regarding the Alpha in the
future. The truth is much different.
- Aaron Sakovich
AlphaNT Maillist Moderator
---- ---- ---- ---- ---- ---- ----
From: "Ted Frederick" <tedf@Cadence.COM>
Hi John,
I thought I'd never live to see the day... (I just keeled over from a heart
attack... I am now typing from beyond the grave...) John Cooley has a
positive thing to say about Spectrum... WOW! I told you several years ago
that this would be a good thing for guys like you, but you wouldn't believe
me. As for your:
> the typical buyer of EDA tools is now quite acclimated to the idea of
> bringing in outside help *and* paying an outrageous $200 to $300 an hour
> for their work! (Yes!)
'Outrageous'? John, if you take a look at the fully-burdened cost of an
engineer, $1500 to $2500/day is less than the company would spend to hire
that person full-time (facilities, benefits, profit sharing, salary, parking
space ;] )
John, as you are surely aware, the real money is not in charging by the
hour, but rather by project and by milestones (forget the hourly stuff
unless you are just doing libraries or design translation grunt work)...
Regarding your:
> Why should I care if it pissed off Andy Grove, the newly ex-CEO of Intel,
> if this raises what consulting engineers are paid? Why should I care if
> some Nortel managers might be trying to boot Cadence out, if Cadence's
> efforts mean that Nortel engineers get paid more to stay? In my reversal,
> I've learned that those who live in glass houses shouldn't look gift
> horses in the mouth. My error. Spectrum helped increase engineering
> wages. Cool.
The StrongARM guys came to Cadence and wanted to be part of the team.
Cadence immediately notified Intel of this and gave them several weeks to
give them first dibs on the engineers. Intel did nothing, so they came to
work for Cadence... then Intel complained. Go figure...
- Ted Frederick
Cadence
( ESNUG 287 Item 4 ) ---------------------------------------------- [4/98]
From: Mark Fox <mark.fox@amd.com>
Subject: Huh? DC 98.02 Ultra License Needed To Replace Old Commands?
John,
We're attempting to run 98.02 and have found an interesting requirement of
another license (DC Ultra) in order to use one of the new commands that
replaces an obsolete compilier option (prioritize_min_paths).
set_cost_priority gives an error message.
Has anyone else run into this problem?
- Mark Fox
Advanced Micro Devices
( ESNUG 287 Item 5 ) ---------------------------------------------- [4/98]
[ Editor's Note: What follows is an on-line conversation I had with
the original developer of Chronologic's VMC (Verilog Model Compiler,
an IP encryption tool that keeps the IP executable). Synopsys is
giving out a $75,000 Humvee Jeep to anyone who cracks it. (Go see
http://www.synopsys.com/secureip about the contest.) He's kind of
shy, so I'm editing his name to read as [ Chicken Man ]. :) - John ]
From: [ Chicken Man ]
Subject: The Crack VMC And Win A $75,000 Humvee Contest
John,
I noticed that you are one of the vmc contest officials. You know as well
as I do that this is a sucker's bet. There is no way to extract the design
from a VMC model and if anything I would be the only one that could even get
close to extracting any sort of information that even resembled the design.
So I guess synopsys will not be giving away that humvee.
Darn.. and I wanted to get to my house in the santa cruz mountains!!
Have a good one,
- [ Chicken Man ]
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
Yea, when I heard about that contest I kind of pushed my way into being a
judge or customer advocate or something like that, [Chicken Man ]. I just
wanted to get the inside scoop if any managed to crack the code and be
able to tell the world how it was cracked. I didn't want a bunch of
backroom Synopsys marketing hacks doing a cover-up. Why don't you give it
a shot, [ Chicken Man ]? If you break it, I'll push like hell to make sure
you get the reward! Go for it!
- John
---- ---- ---- ---- ---- ---- ----
From: [ Chicken Man ]
John,
So would you get also bulldog all the synopsys lawyers for me too?
- [ Chicken Man ]
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
Chicken! Buck-buck-buck-buck-buck! Go for it!
- John
( ESNUG 287 Item 6 ) ---------------------------------------------- [4/98]
Subject: ( ESNUG 286 #3 ) Newer Rev of DC LOGSCAN v1.20 Now Available
> (You can also expect another minor update to appear at the web page in the
> near future to correct an installation issue. For now, just be sure to
> (A) rename the executable to 'logscan'; (B) make sure it's
> executable/readable; and (C) modify appropriately if your Perl 5 executable
> is named anything other than 'logscan'.)
>
> - David C Black
> Qualis Design
From: David C Black <dcblack@qualis.com>
John!
Oops...that last line should have read "anything other than 'perl'". I was
not trying to be so presumptuous as to have perl renamed to my tool. ...
I imagine most folks will automatically recognize this typo.
- David C Black
Qualis Design
( ESNUG 287 Item 7 ) ---------------------------------------------- [4/98]
From: plaberge@micronpc.com ( Paul LaBerge )
Subject: DC 98.02 Has Screwed Up Timing With The LSI Logic lcbg10p Library
Hi John,
We came upon a bug in 1998.02 using the LSI Logic lcbg10p library.
DC doesn't see the correct timing while optimizing, therefore it doesn't
give good results for timing. Later when report_timing is done the correct
timing shows up. It has something to do with min cap in the library.
If you have the problem you'll see the delta delay at zero, but your timing
report will show a negative slack.
WORKAROUND:
remove_attribute lib_name + "/*/*" min_capacitance > /dev/null
- Paul LaBerge
Micron
( ESNUG 287 Item 8 ) ---------------------------------------------- [4/98]
Subject: ( ESNUG 286 #10 ) Using My Cadence Simwave To View Synopsys VSS?
> Does anybody know of a better waveform viewer than the lousy one that comes
> with Synopsys VSS, yet is compatible with the Synopsys simulator? I have
> the simwave tool from Cadence for our verilog simulations. Is there any
> way to use it (compatibility wise) with vhdlsim?
>
> - Salman
> NASA Goddard Space Flight Center Greenbelt, Maryland
From: [ A Synopsys DW R&D Engineer ]
John,
VSS is capable of outputting VCD (Verilog Change Dump) files instead of/
in addition to its normal format. The two commands required (on the
simulator command line) are "vcdfile <filename>" and "vcdaddobjects 0
<path>". The command
vcdaddobjects 0 *'signal
will trace all signals at the current level of hierarchy.
- [ A Synopsys DW R&D Engineer ]
( ESNUG 287 Item 9 ) ---------------------------------------------- [4/98]
From: peterpb@lsil.com (Peter Bojanczyk)
Subject: You Can't Find O-in On the Web Anywhere! Does This Company Exist?
Hi John,
Can you give me contacts (phone, web site) of the company which developed
"0-in" ? Can't find it on the web.
- Peter Bojanczyk
LSI Logic
---- ---- ---- ---- ---- ---- ----
From: Rachael Berman <rach@mint-tech.com>
John,
I thought the two trip reports were very useful, and downright hysterical
at times. It just goes to show, you should never write off someone's talent
just because he doesn't like emacs... I especially liked the description of
0-in. I've been meaning to look into their product for a while. I couldn't
find it, having foolishly searched for the word "zero". They should add a
(<META> zero ) (in proper HTML) so the search engines will pick that up.
- Rachael Berman
Mint Technology
( ESNUG 287 Item 10 ) --------------------------------------------- [4/98]
From: "Yuan (Steve) Hwang" <hwang@eng.adaptec.com>
Subject: DC 98.02 May Hang Up During Insert_Scan & The Workaround
Hi John,
Design Compiler 98.02 may hang during insert_scan process, and the problem is
reported to Synopsys (registered as LOGID 65436.) The problem occurs when
insert_scan in the process of fixing design rule violation, and it does not
work even if -ignore_compile_design_rules is specified.
Synopsys engineering has come out with a hidden variable which can avoid the
problem, and I have verified the workaround.
test_dont_fix_constraint_violations = true
Since insert_scan command is widely used by all Synopsys users, please post
this information for whom may encounter this issue during insert_scan.
- Yuan (Steve) Hwang
Adaptec
( ESNUG 287 Item 11 ) --------------------------------------------- [4/98]
Subject: ( ESNUG 286 #7 ) Free FSM Tool "cisco_fsm" For Verilog Designs
> In next few days, we will release cisco_fsm on a limited basis (i.e. you
> cannot develop Cisco competing products by applying cisco_fsm tools and
> only a Solaris version is available.)
>
> - Tsu-Hua Wang, Ph.D.
> Cisco Systems
From: "Sam Bishai" <bishai@nortel.ca>
Hi, John,
As an ASIC designer I usually focus on getting a chip out to meet a system
requirement but I am not always sure who the company competes against for
that particular product.
I understand that in two or three sites both our companies are collaborating
as per customer request. But there may be an area or two where we obviously
compete. How do you determine this?
- Sam Bishai
Nortel
( ESNUG 287 Item 12 ) --------------------------------------------- [4/98]
Subject: (ESNUG 285 #6 286 #4) Formal Verification, Formality & Chrysalis
> OK, John. What's your take on Formality's current capability? Is it the
> usual 'trust us, we'll take care of the problems', or does the approach
> Synopsys has taken -- same compiler for DC and Formality, use of .db file
> to represent logic elements, switching DC versions to find differences, the
> same mapper, parser, synthesizer, etc., etc.
>
> Are the comments above meaning to say: We'll work w/ the tool, hacking away
> until it does the job; because of the investment in Syn (dare to interpret
> that as a double entendre). If so, we're in the same boat, and should plan
> on added time and cost in solving the verifications we do.
>
> Or, should designers looking to Formality to chase arduous regression
> simulations at the gate level consider it a reasonable alternative? Is
> any user going to understand the risk in using Formality also going to be
> working on real silicon? Or the issues he (and Chrysalis) raises
> significant enough to bother about? Some clear and conclusive answers
> would be helpful!
>
> - Frank J. Rich
> MRT
From: Craig Cochran <craig@Synopsys.COM>
John,
I was quite astonished to find this message from Frank Rich, planting
ouright falsehoods about Formality in ESNUG . Frank didn't identify
himself, so allow me to identify him for you - he is the PR Representative
for Chrysalis. It's not enough that Chrysalis is spreading outright lies
about Formality in advertisements and statements to customers - Their PR
guy feels it's appropriate to use your user-oriented medium to covertly
spread false marketing messages about his competition. I know this is not
how you intend people to use ESNUG.
In any case, allow me clear things up for your readers. Formality is NOT
based on Design Compiler. It does not use the .db format to represent
designs, it does recompile the design separately from Design Compiler using
a different version parser, and it DOES correctly verify 0,1,X and Z states
and check the sequential behavior of flip-flops. Formality is in use today
at major customers and already has silicon success - and has displaced
Chrysalis in many accounts that have purchased it. Why? Higher
performance & capacity, excellent debugging capabilities and it is a much
easier tool to use. If Chrysalis can only compete by spreading false
statements, I think that makes a statement in and of itself.
Sorry to put my marketing hat on in your user-oriented forum. We now
return you to your regularly scheduled programming.
- Craig Cochran
Product Manager - Formal Verification
Synopsys Inc.
[ Editor's Note: It's my personal policy to not let *any* EDA sales or
marketing people post anything on ESNUG other than purely *technical*
replies to what users bring up. (i.e. ESNUG is meant for technical
discussion and *user* opinions -- anyone can put techie stuff on ESNUG
(even marketing hacks), but no sales pitches are allowed!) I appologize
for not "catching" Frank while editing. Sorry. (I must give Frank the
Biggest Balls Of The Week Award, though, because he must have known
he'd be caught. My kudos. :^) - John ]
( ESNUG 287 Item 13 ) --------------------------------------------- [4/98]
From: Will Leavitt <leavitt@giga-net.com>
Subject: How Can I Map From A Hierarchical Path To A Design Name?
John,
I have a uniquified, hierarchical design. I would like to start with
a path to a cell
"h2u1/h3u4/lh_out_reg"
and figure out which design it is in so I can change my current_design
to it. Conceptually, I want to
cd "h2u1/h3u4".
Is there a simple way to go back and forth between paths and design
names? I have tried the current_instance command, but I really need
to cd between designs, not instances. I want to take the path of a
gate or a net, cd to the design containing it, then run a script that
adds and deletes nets and cells. I can only do these commands in the
design itself.
- Will Leavitt
GigaNET, Inc. Concord, MASS
( ESNUG 287 Item 14 ) --------------------------------------------- [4/98]
From: Victor_Duvanenko@truevision.com
Subject: How To Save "false_path" or "multi-cycle path" Sub-design Info?
John,
Does anyone know of a method to save the false_path or multi_cycle_path
information for a block? Then when you go to the next level up within the
hierarchy to use that information automatically (it would be nice if
it was saved in the .db file). Then on the next level up within the
hierarchy the design would actually meet meet timing constraints since
the "false_path" or "multi_cycle_path" information would be available.
- Victor J. Duvanenko
Truevision, Inc.
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