Editor's Note: For fans of "Star Trek: The Next Generation", bizzare
aliens with borderline personality disorders is nothing new. For example,
there is the "Borg", a race of half-human, half-machine entities all
mind-linked together traveling through space in giant cube-shaped ships.
They have this antisocial habit of attacking and mercilessly "absorbing"
other cultures in their entirety (people, machines, everything!) Borgs
like to say: "Prepare to be assimilated", and when their target very
predicably reacts negatively to this greeting, the Borgs retort with:
"All resistance is futile" as they commence the "assimilating" process.
They had a series of shows where Jean-Luc Picard, the Captain of our
beloved Enterprise, was caputured and "assimilated" by having some very
fashionable machine parts added to his person along with a name change to
"Locutus". (Even had him saying "All resistance is futile!", too.)
A few days ago I was buzzing about the SolvIt database trying to find an
esoteric Verilog related bug. I mis-typed the search engine request and
suddenly found literally *hundreds* of Verilog *VCS* bugs! Whoa! I was
stunned by the implications. Synopsys had finalized buying ViewLogic not
two months ago and they had *VCS* bugs deep within the SolvIt database!!??
Do you know how long it takes to bring an in-house EDA product on-line?
All the training of trainers, of CAEs, of Field Engineers? And before that
you need to get R&D buying in, too! It can take 6 to 18 months before
significant numbers of bugs start poping up in the SolvIt database! Yet
two months and the Synopsys-Borg seems to have "assimilated" (i.e. snorted
down) ViewLogic like a McDonald's Kids Happy Meal!
And the scariest thing is that no one has seen Will Herman, the old CEO of
ViewLogic, around lately... Don't be surprized to see if he now answers
to the name "Locutus" and greets people with: "All resistance is futile!"
Whoa! :^)
- John Cooley
the ESNUG guy
( ESNUG 282 Item 1 ) ------------------------------------------------ [2/98]
Subject: (ESNUG 281 #11) Problems Cleaning Up Dangling Gates In An IP Core
> In my design, I have a bunch of gates whose outputs are not being used.
> (A purchased core that has functionality, and thus outputs, that I don't
> need is a common way that I get dangling gates.) Are there switches in
> DC to tell it only to remove extra gates & not further optimize? I tried
> "-incremental". I tried "-incremental -only_design_rule". But DC always
> insists on further "optimizing" other logic. I added
>
> "compile_no_new_cells_at_top_level = true"
>
> (for flat designs), which was successful on some modules, but
> optimized-out needed buffering on other modules. Any ideas, anyone??
>
> - Rick Weiss
> NABLE Technologies Cupertino, CA
From: Gilbert Nguyen <imgn_1@yahoo.com>
Try:
set_unconnected { your unused out_ports }
compile -only_design_rule
This should remove the unused gates at that level of hierarchy.
If it is a submodule or component underneath then:
characterize -connections your_ipcore
current_design ipcore_ref
compile -only_design_rule
To verify that the attributes are on your ports do:
get_attribute {your unused out ports } output_not_used
Regards,
- Gilbert Nguyen
( ESNUG 282 Item 2 ) ------------------------------------------------ [2/98]
Subject: (ESNUG 281 #9) Why Design_Analyzer Works Faster In The Background?
> I have run optimization of my design (written in VHDL, works fine) using
> Design Analyzer in the background. Why? Because it ties our machine
> for at least 2 days if I execute it in the foreground. DA's graphics
> aren't that involved; why does it chow so much time?
>
> - P.J. Chose
> Memorial University (Canada)
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Why are you bothering with Design Analyzer at all? Just use dc_shell
instead. I only startup DA when the boss comes around and wants to
look at a schematic for some arcane reason. :)
>When I do a report_area, I get the following messages.
>
> Information: This design contains unmapped logic. (RPT-7)
> Information: This design contains black box (unknown)
> components. (RPT-8)
>
> - P.J. Chose
> Memorial University (Canada)
This means that at least one of your modules had a problems when it was
compiling and it still has unmapped logic in it, check the log file for
errors. Another possibility is that your VHDL code contains logic that
does not exist in the target library. A D Flip/Flip with asynchronous
clear and preset for instance.
The black box warning indicates that an component that you instantiated
did not have a corresponding cell in the target library or within the
supplied VHDL code. An interface mismatch may also be a culprit here,
forgetting a port, an additional port, different bus width, etc...
To find out which entities/components are the offending ones use
check_design or link *
In addition, to speed up your compile times I would suggest that you
use a bottom-up compile approach and apply dont_touch'es as you go, unless
you want to pop for new UltraSPARC 300MHz box with 2 GIGs of RAM. :)
For a bottom-up compile you start from the lowest level module,
use "current_design [design_name]" and compile it with medium effort,
use "compile -map medium". Then instruct Synopsys not to touch it again,
use "set_dont_touch current_design", before preceeding to the next one.
This will result in much smaller memory needs and design space exploration
especially if you are using the same module multiple times. The tradeoff
is that you may lose performance or area since you aren't compiling across
module boundaries. These problem areas can be easily identified with
report_timing and fixed with incremental compiles, use
"compile -incr -map high"
- Ed McGettigan
Xilinx Inc.
( ESNUG 282 Item 3 ) ------------------------------------------------ [2/98]
Subject: Reviews of Cooley's Review of "HDL Chip Design" By Doug Smith
> And even though this type of work can be rewarding, it's also quite
> physically and emotionally draining. It usually takes me a week or more
> to get reaquanted with my girlfriend, unwind, and generally return to (at
> least) appearing coherent. And here's where my feeling threatened comes
> in. During these low stress times, I'll sometimes take on short term
> contracts to tutor one or two engineers in Verilog or VHDL. Gravy work.
> Easy money. Low stress. Relaxing.
>
> Relaxing, that is, until I recieved Doug Smith's book "HDL Chip Design"
> (ISBN 0-9651934-3-8) in the mail. That damn book teaches Verilog and VHDL
> in a very understandable and common sense way. And it teaches the reader
> how to think like a synthesis tool, too. Damn! It really sucks! Who's
> going to want high dollar personal Verilog or VHDL tutoring when they could
> just as easily e-mail "asmith@doone.com" and buy his book? Damn! This
> REALLY sucks! There goes my easy, low stress tutoring jobs between the
> high stress contracts. Oh, well. I guess all good things must come to
> end sometimes.
> - John Cooley
> EE Times Industry Gadfly
From: [ Don't Worry, Be Happy! ]
I read your article in EE Times, "Feeling Threatened". I work for an ASIC
design consulting firm and we recently worked with a large corporation.
They bought several copies of Doug Smith's HDL Chip Design book last year
for their junior engineers. To this day they are still clueless about VHDL
(at least most of them).
So I wouldn't worry too much if I were you.
Please don't mention my name or company, I wouldn't want this to get back
to that other organization. They're good people and I don't want to hurt
their feelings.
- [ Don't Worry, Be Happy! ]
---- ---- ---- ---- ---- ---- ----
From: john.eldon@fairchildsemi.com (John A. Eldon)
Hi John,
Thanks for the tip on Doug Smith's book. I created and teach a Verilog
class at UCSD Extension. Over the years, I've used four different textbooks
and have at least a few gripes with each one. I'm keen to compare my
current text, James Lee's "Verilog Quickstart" (Kluwer 1997), against the
Verilog portions of Smith.
- John A. Eldon, D.Engr.
Principal Systems Engineer
Fairchild Semiconductor San Diego CA
---- ---- ---- ---- ---- ---- ----
From: Jake Karrfalt <jake@ascinc.com>
John,
Alex Z signed an early copy of Doug Smith's book "HDL Chip Design" (ISBN
0-9651934-3-8) two years ago at IVC. Our engineers have used it often as
a reference. What you have to offer is knowing which page to go to in
the book, so I would not lose heart. Experience is the greatest teacher.
Keep the faith.
- Jake Karrfalt
Alternative System Concepts, Inc.
---- ---- ---- ---- ---- ---- ----
From: khui@auravision.com (Kenny Hui)
Dear John
You should feel threatened!
Today, all the hardware, or EE engineer know how is to design digital logic
with Verilog or VHDL. The tools is just too easy to use. In a few more
years, every person in Silicon Valley will know how to use it, even the
secretary. Even more threatening, almost every engineering school is
teaching some Verilog or VHDL. Most new graduates I interview can tell you
the whole design flow and syntex.
Even more, today's new products have a very short life cycle, and gates are
cheap. Who cares if your design is better than the other? By the time it
was done, the engineer who design it has changed jobs!
So just relaxing, make as much as you can, retire early, and forget about
the future contracts. You are one of the few lucky one who has been ahead
of his time.
- Kenny Hui
Auravision
---- ---- ---- ---- ---- ---- ----
From: "James M. Lee" <jml@c118618-a.frmt1.sfba.home.com>
Well, John,
I would not feel threatened by a book, since as good as a book can be,
there is no substitute for real experience.
However, I am offended that you are plugging someone else's book and not
mine! :(
- James Lee, ex-Cadence, now consulting
Author of "Verilog Quickstart" (ISBN 0-7923-9927-7)
---- ---- ---- ---- ---- ---- ----
> Their chip was mostly in Verilog, but there was a mysterious piece of
> IP from Intel written in VHDL that had to be incorporated into it.
>
> - John Cooley
> EE Times Industry Gadfly
From: [ Wally Rhines, CEO of Mentor Graphics ]
John,
Your letter is a great testimonial for single-kernel Verilog/VHDL simulators
like Modelsim! If these examples of mixed blocks of VHDL and Verilog
continue to turn up, don't you think designers will begin solving the
problem this way? Or, alternatively, use a product like Renoir to convert
the unfamiliar language IP block to graphical form and then recompile in
their language of choice? (Both approaches available today.)
Thanks for the real world experiences.
- Wally Rhines, CEO
Mentor Graphics
[ Editor's Note: Wally, I can't let you get completely away with murder.
Your Renoir is pretty much a copycat product mimicking Summit Design's
toolset straight down to the very look and feel. OK, so plagerism is
the sincerest form of flattery. But Summit's tools have been around far
longer, so they have the advantage of being more debugged than Renior.
(Sorry, I just had to level the playing field a bit here.) :^) - John ]
---- ---- ---- ---- ---- ---- ----
From: Tom Scharf <t_scharf@sirius.com>
Greetings John,
I just read your column in EET in which you mentioned Doug Smith's HDL
book. I agree with you that it should be on the desk of anyone attempting
HDL synthesis of either asics or fpga's. I have noticed that there is not a
large selection of books available on verilog. Besides the Smith, which
concentrates on the synthesizable sub-set, I found only 3 verilog texts (I
own all of them). Of these, only one is really useful. The classic text
from Mooreby is OK but hard to learn from and the book from Trivedi & Singh
is incomprehensible. The book that I have been recomending to everyone who
asks is "Verilog HDL, a Guide to Design and Synthesis" by Samir Palnitkar,
ISBN #0-13-451675-3. It doesn't have the easy to use pizzaz of Smith, but
it covers all aspects of the language in a clear, well developed fashion.
In learning verilog, I have taken classes from both Yatin Trivedi and Samir
Palnitkar. Both are fine teachers, but Palnitkar's book is without a doubt
the best available text for learning the language.
- Tom Scharf
ADAC Laboratories Milpitas, CA
---- ---- ---- ---- ---- ---- ----
From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
Hi, John
I read your "Feeling threatened" EE Times article and agree that Doug
Smith's HDL Chip Design book is a very good book with lots of good
side-by-side Verilog-VHDL examples.
The VHDL examples appear to be excellent but I do have two observations
about some of the Verilog examples.
(1) Doug does not use non-blocking assignments in his sequential Verilog
examples. Although blocking assignments will synthesize to the desired
logic, blocking assignments might introduce Verilog simulation race
conditions when doing Verilog RTL simulations. In a nutshell, I recommend
using blocking assignments for combinational logic assignments and
non-blocking assignments for sequential logic assignments (or mixed
sequential and combinational logic assignments).
(2) Some of Doug's Verilog examples are somewhat verbose. A barrel shifter
example, on page 277, uses a separately coded rotate-left function that is
unnecessary. The exact same example could be coded as shown below. (Note:
as one who believes all of Hillary Clinton's conspiracy theories, I believe
Doug is part of a VHDL conspiracy to make Verilog look more verbose ;-)
module ds_SHIFT_BARRELb (Rotate, A, Y);
input [2:0] Rotate;
input [5:0] A;
output [5:0] Y;
reg [5:0] Y;
always @(Rotate or A)
case (Rotate)
0: Y = A;
1: Y = {A[4:0],A[5]};
2: Y = {A[3:0],A[5:4]};
3: Y = {A[2:0],A[5:3]};
4: Y = {A[1:0],A[5:2]};
5: Y = {A[0],A[5:1]};
default: Y = 6'bX;
endcase
endmodule
The VHDL examples in Doug's book use the IEEE.Numeric_STD package. Are
engineers successfully using this package with Synopsys synthesis?
Overall I give Doug's book a "thumbs-up," which is more than I can say for
the book Logic Synthesis using Synopsys, 2nd Ed. The latter has very
inefficient Verilog coding and testing styles and a number of Verilog and
functional typos. Even the Verilog example on the cover of the book has a
Verilog syntax error and will not compile. I'm also not impressed with the
VHDL coding styles in the "Logic Synthesis" book.
- Cliff Cummings
Sunburst Design
---- ---- ---- ---- ---- ---- ----
From: Jan Zegers <janz@easics.be>
Hello, John,
On receiving your "publicity" for the VHDL/Verilog book "HDL Chip Design",
we as an ASIC Design Company, immediately bought it. I did not read it
completely, but rather scanned to detect the VHDL/Verilog style that it
recommends. I was very surprised to see so many obvious errors, that I
wonder why you recommend it.
As an example, take the FSM1_BAD on page 203. All the boxes that clarify
why it is bad, are simply wrong on the VHDL side.
Did you overlook these errors or do you agree with the boxes?
- Jan Zegers, General Manager
Easics Leuven, BELGIUM
[ Editor's Note: Jan, I think you may have misunderstood the reason why
I like Doug's book. It's not because it's error free, or that it teaches
anything beyond a blindingly average view of synthesis. (Shit, it doesn't
even teach Synopsys; it teaches VeriBest synthesis! Who the hell is using
VeriBest synthesis for real design work???? No one!) I like the book
because it's good for *newbies* -- engineers who are just trying to grasp
the *basics* of Verilog, VHDL, and synthesis. For that purpose, I've
found it to make those topics "reachable" to an average *beginner*. For
*advanced* designers like yourself or Cliff, this book probably is just a
typo catching exersize rather than a source of new ideas. I thought I
conveyed this when I wrote about it replacing "gravy contracts" teaching
*newbie* engineers about Verilog, VHDL, & synthesis. Sorry. - John ]
( ESNUG 282 Item 4 ) ------------------------------------------------ [2/98]
Subject: (ESNUG 281 #10) HELP! Synopsys Online Viewer "Page-Up" Gets Drunk!
> Has anyone else experienced this strange condition with the online
> documentation viewer? Sometimes the Page-Up key flips the pages one way,
> but other times the pages go backwards! This is kinda petty but it's
> starting to really bug me. I can handle the tooth-paste thing and the
> changed-my-mind syndrome in other people but this is too much! If you
> know the solution or cause of this please respond!
>
> - Rod Ramsay
> Ford Microelectronics Colorado Springs, Colorado
From: Peter Kamphuis <peter.kamphuis@hl.siemens.de>
John,
We've seen this effect in the past, too. I've always thought this was
caused by the (at that time) older version of WorldView in combination with
SunOS 4.1.* and OpenWindows. Probably some kind of key binding (xmodmap)
problem. We are now mainly using the latest version of WorldView (which
comes with the Synopsys software) on Solaris 2.5 and both OpenWindows and
CDE. To get rid of this problem in the past I can remember we added some
lines to the Iview setup file:
Iview*defaultVirtualBindings: osfCancel : <Key>Escape \n\
osfLeft : <Key>Left \n\
osfUp : <Key>Up \n\
osfRight : <Key>Right \n\
osfDown : <Key>Down \n\
osfPageUp : <Key>F29 \n\
osfPageDown : <Key>F35 \n\
osfBackSpace : <Key>BackSpace \n\
osfDelete : <Key>Delete \n\
osfInsert : <Key>Insert \n\
osfCopy : <Key>F16 \n\
osfCut : <Key>F20 \n\
osfPaste : <Key>F18
Hope this helps in finding a solution to the problem.
- Peter Kamphuis
Siemens Semiconductor, Munich
( ESNUG 282 Item 5 ) ------------------------------------------------ [2/98]
Subject: (ESNUG 281 #5) FPGA Gate Counts And Equivalent ASIC Gate Counts
> I am involved with a design that will go first into an FPGA and later it
> will be part of an ASIC. As FPGA, we selected an Altera Flex10K10 (or if
> required we could go to a Flex10K20). ... Our estimates initially were
> about 8K gates (of which 400 flip-flops) and 1.8 kbit of ram (single port).
>
> Synthesis for an ASIC tells me that the current design has:
>
> - 663 FFs -> 3656 equivalent gates (nand2's)
> - combinatorial logic -> 2869 equivalent gates (nand2's)
> - some RAM, but this is mapped into the 3 EAB blocks.
>
> ... The current status of my design is that it needs about 1080 LE's
> (report of MaxPlus2) but we can't get it routed. It complains on
> fasttracks that are all used somewhere in the design. Is this 6 to 12
> gates per LE with or without the flip-flop gates? Are there others with
> similar problems with either routing or in estimating the size of the
> target device ??
>
> - Koenraad Schelfhouts
> Alcatel Bell Antwerpen, Belgium
From: [ Keep-Those-Rampaging-Altera-Lawyers-Away! ]
John -- please withhold my name, although they are going to able to guess
who wrote this. Altera has been on a rampage lately with lawyers. Thanks.
We have found that given the LSI standard for measuring gates, the Altera
10k family follows approximately the following formula:
Take the last digits of the part number:
"10k20" take the 20,
"10k100" take the 100, etc.
Multiply by 0.4 and add whatever memory constructs. Therefore:
a "10k40" calculates to 16Kgates + mem,
a "10k100" calculates to 40Kgates + mem, etc.
This represents the *maximum* number of gates you will be able to fit into
an equivalent ASIC. Note that this number is a maximum and should be
backed off by 25-50% to ensure reasonable routes. Large busses are
troublesome in Altera 10k, but other than embedded memory constructs, which
*SUCK UTTERLY* for any dual-ported functions such as FIFO's or dual-port
RAM's, it is a decent technology. Be careful of the OE's also -- Altera
has not yet figured out that designers actually need these things on I/O's.
In general, the 4000XL family is better for ASIC prototyping because of its
more flexible memory capability. Xilinx 4000XL, however, is prohibitively
expensive (~= 2X the cost of an equivalent Altera 10k part). The XC4000XL
is also 10-15% faster in the faster speed grades. The sales force is also
an issue. If you are in an Altera territory that has only a direct
sales force with support through distribution, expect to get very hostile
(or no) treatment when you ask for databooks, pricing, availability etc.
Altera has clearly decided that anybody beneath Cisco doesn't warrant any
attention and should be ignored. This is not true (yet) with Xilinx.
For Koenraad, unless he is adding memory, an 8000 gate design is too big to
prototype in either a 10k10 or 10k20, he needs at least a 10k30A. This is
only possible if he is willing to add a regulator.
Incidentally, the Xilinx gate multiplier is 0.5, but memory takes CLB
resources so the formula is much more complicated.
Synthesis is also an issue. Design Compiler for FPGA's from Synopsys
generally is beaten out for last place by ViewLogic for quality of
synthesis and both those tools should be mothballed. FPGA synthesis should
be done by Synplify (from Synplicity), FPGA Express (Synopsys), or Galileo
(Exemplar). There are differences between these tools and we have found
that Synplicity generally gets the best results, but all three tools are
quite useful. Competition has been a wonderful thing for FPGA synthesis.
Hopefully soon the same will be able to be said about ASIC synthesis.
- [ Keep-Those-Rampaging-Altera-Lawyers-Away! ]
---- ---- ---- ---- ---- ---- ----
From: Eric Ryherd <eric@vautomation.com>
Our very crude rule of thumb here at VAutomation is
ASIC gates X 4 = Xilinx 4000
ASIC gates X 6 = Altera 10K
Thus, an XC4036 with 36,000 "gates" really only holds 9,000 gates
which is about the same as a 10K50.
Our designs tend to be a bit heavy in decode and control logic which
tends to suck up routing which is often the constraining item (especially
in Altera). Your mileage may vary...
- Eric Ryherd
VAutomation Nashua, New Hampshire
( ESNUG 282 Item 6 ) ------------------------------------------------ [2/98]
Subject: (ESNUG 278 #7 280 #4 281 #2) Synch Resets Combined W/ Random Logic
> process (clock, reset)
> begin
> If reset = '1' then
> A <= '0';
> elsif clock = '1' and clock'event then
> A <= Input1;
> B <= Input2;
> endif;
> end Process;
>
> If you elaborate the above without adding process-specific attributes
> or changing the default value, you will find design compiler DOES NOT
> NECESSARILY recognize either a synchronous or async reset. The reason
> is the code attempts to infer a synchronous reset, but the variable
> precludes it. ....
>
> - Jeff Koehler
> Cabletrons Systems Littleton, Massachusetts
From: Ed Bender <bender@atitech.ca>
Sorry to nitpick but this code looks like it is attempting to infer an
asynchronous reset, not a synchronous reset. If you want a synchronous
reset then 'reset' should NOT be in the sensitivity list:
process (clock)
begin
If reset = '1' then
A <= '0';
elsif clock = '1' and clock'event then
A <= Input1;
B <= Input2;
endif;
end Process;
Regards,
- Ed Bender
ATI Technologies Inc
( ESNUG 282 Item 7 ) ------------------------------------------------ [2/98]
Subject: (ESNUG 280 #7 281 #1) Need Help Doing Synopsys-HSPICE Correlation
> First of all, thanks for all the great information presented in the ESNUG
> postings. We are doing some Synopsys to HSPICE correlation. I am
> interested if anyone has an idea of how to automatically generate the
> input vector that correlates to the report_timing static analysis. In my
> particular case I am dealing with an asynchronous logic block, so there
> are no flip flops to disturb the path. Any ideas anyone?
>
> - Dave Schaefer
> Logical Silicon Solutions
From: Tom Ho <tom@iota.com>
John,
We found something interesting in the Synopsys timing report recently
that I had to use a better Timing Analyzer to cross check the timing
reports from Synopsys. We put 9999 in some of the impossible paths
in the Synopsys library file. Those 9999s showed up on the timing report.
In order to correlate between HSPICE and the other Timing Analyzer,
we used a Transistor level Timing Analyzer we have (may be it is like
PathMill from Synopsys). It can report the critical path easily and extract
a HSPICE netlist of the critical path with all the nodes initialized
automatically. You can just take the SPICE deck to run HSPICE. We have
accuracy of less than 3%. This was how we calibrate the accuracy of our
Synopsys library files, and the our Timing Analyzer.
I guess people can use Anagram, TimeMill, PathMill, ...etc to perform
the correlation. It is just that the timing reports from Synopsys are
quite rough. Good luck.
- Tom Ho
IOTA Technology Inc
( ESNUG 282 Item 8 ) ------------------------------------------------ [2/98]
From: Eran Vodevoz <eran.vodevoz@analog.com>
Subject: Library Compiler Won't Take Discharge Cells
Hello John,
I have a problem/challenge - how to "feed" Library Compiler with discharge
cells? As it was proposed in the course -- the general direction is to
define it as an ITS module. I've been searching in the openbook ("Synopsys
On-Line Docs") for an example of discharge cells but I found none.
I would really appriciate if someone could send me an example of ITS format
with the required timing arcs (I mean the names/kinds of arcs -- not the
numbers) for a discharge cell. Here is an example of a typical circuit:
+---o NOUT
|
|
EN---||
|
|---------+
A---|| |
| B---||
| |
| |
| C---||
| |
| |
\/ \/
Let's say that the EN input is clock or "something & clock"
- Eran Vodevoz
Analog Devices Hertzlia, Israel
( ESNUG 282 Item 9 ) ------------------------------------------------ [2/98]
From: erez@taux01.nsc.com (Erez Naory)
Subject: DesignTime -- Problems Generating SDF With Timing Driven Layout
Hi John,
I am trying to generate the SDF for timing driven layout. For this
we use the "write_constraints -cover_design" command. The design
contains gated clocks, so we use the -propagate option in dt_shell.
Here is a simple example:
____
------------ / \____ -----------
| FF1 | / \__ | FF2 |
| Q |------->| logic |------->| D |
| | \______________/ | |
clk --|> | clk --|> |
------------ ------------
Both FF1 & FF2 are driven by the same clock, with delay of ~2ns. (skew
in this case is close to zero). The setup to FF2 is 1ns. Cycle 10ns.
The report_timing reports a path that starts from:
FF1/Q at time 2ns (clock delay) + 0.8ns (delay clk to Q in FF1)
and ends at
FF2/D at time 10ns (cycle) - 1ns (setup) + 2ns (clock delay to Ff2)
Which is what you'd expect. However, in the SDF generated, the path will
start at time 0.83 (delay of the FF1 to Q) and will not include the delay
of clk to FF1, but will take into account the effect of the delay to
the clock to FF2, therefore generating a path which is longer in 2ns
(exactly the delay on clock to FF1).
Has anyone ran into this problem? Is there a way to bypass that? Any
flags or other report methods?
- Erez Naory
National Semiconductor Hertzlia, Israel
( ESNUG 282 Item 10 ) ----------------------------------------------- [2/98]
From: Chad Fasca <cfasca@cahners.com>
Subject: Questioning Formality's Independence From Design Compiler
Dear Mr. Cooley:
I need your insights on Formality, Synopsys's new equivalence checker.
Questions have been raised by Synopsys competitor Chrysalis about the
independence or lack thereof of Formality from Synopsys's Design Compiler
synthesis tool. How much of an issue is Formality's reliance on DC? Is
Formality going to allow the same faults to slip through that DC allows?
- Chad Fasca
Associate Editor
Electronic News
|
|
