Editor's Note: At the end of last month's "SNUG'97 Trip Report" I asked:
"as a reader of ESNUG, do you like trip reports like this that mix news,
business, technology, & opinion?" Overall I received 137 letters from
readers: 121 voiced general approval of this style of reporting, 2 didn't
like it, and 18 had direct responses to topics within the report itself.
Enclosed is a sample of the general reactions plus the all of the specific
topics individuals had issue with. Enjoy!
- John Cooley
the ESNUG guy
( ESNUG 262 Item 1 ) -------------------------------------------- [5/97]
Subject: General Response To Reports That Mix News, Gossip, Technology, etc.
> P.S. I'm curious: as a reader of ESNUG, do you like trip reports
> like this that mix news, business, technology, & opinion?
From: Yves DURAND <yves@sat.grenoble.hp.com>
Yes! And every "leak" you reported matched a strange question from my
local "salesdroid"!!
- Yves Durand
HEWLETT-PACKARD, Grenoble, France
From: "Jeff Waite" <waitej@adtaz.sps.mot.com>
Absolutely - keep them coming. It helps very much to pick up this
information that we won't be reading in EETimes! Keep up the good work.
- Jeff Waite
Motorola
From: stai@Brocadecomm.COM (Jeff Stai)
Are you kidding? I look *forward* to your stuff! :^) The Protocol Compiler
and telecom workbenches sound particularly interesting, but only if they
do Fibre Channel someday...
- Jeff Stai
Brocade Communications, Irvine, CA
From: eimear@s3dub.ie (Eimear Murphy)
Hi John,
In a word, yes, I like (and NEED) your trip reports. We get zero contact
from Synopsys Apps engineers. Paul Osborne promised me at the VHDL-UK
conference last year, that they would hold a RTL Design seminar in Ireland,
now that there are a shit load of Synopsys licenses in the country, but it
has yet to be.
Can you recommend any books / papers on Verilog for Synthesis ?
- Eimear Murphy
Silicon & Software Systems, Dublin, Ireland
From: Ed Spittles <spittles@bristol.st.com>
Sorry John, much as I find ESNUG interesting and useful, I don't like
the mixed report style - I took five minutes halving the size and making
meaningful headlines, so if/when I browse in future I'll be able to see
the wood for the trees. Call me a humourless bastard.
- Ed Spittles
SGS-Thomson
( ESNUG 262 Item 2 ) -------------------------------------------- [5/97]
From: b_roach@emulex.com (Brad Roach)
Subject: IMPORTANT: SNUG Attendees Check Your Credit Card Statements!
Dear John,
This message is for anyone who attended February/March 1997 meetings at the
Red Lion in San Jose (like SNUG'97 !!!!), and used their credit card for
meals, lodging, etc. Apparently a major credit card counterfeiting ring has
been arrested in Oakland, by the FBI and Secret Service. One of the sources
for credit card numbers was an employee of the Red Lion in San Jose. That
employee has been arrested and is no longer a Red Lion employee.
A friend of mind had his credit card number found in the possession of the
counterfeiters by the Secret Service, who contacted his bank, who contacted
him. Therefore, it might be wise to double check your card statements,
on the chance that the Secret Service did not find all of the stolen
credit card numbers, or on the chance you do not have a 'full service
bank' ;-). I might suggest anyone who suspects their card may have been
used by these perps contact your bank or card provider ASAP.
- Brad Roach
EMULEX Network Systems
PS, Ironic Note: Apparently, one of the groups at the hotel that got stung
by this ring was a conference for police officers. The subject of the
conference was combatting fraud...
( ESNUG 262 Item 3 ) -------------------------------------------- [5/97]
Subject: DEC's Alphas Are Floundering In EDA Due To No Verilog Port
> "DEC is still pushing Alpha, yet the industry-standard simulator,
> Cadence's Verilog-XL, hasn't been ported to Alpha. How can DEC
> pretend to be serious about EDA?" - An anonymous user's response
From rongood@world.std.com (Ronald Goodstein)
It is too sad that DEC will not port Cadence Verilog XL over to their Alpha.
I keep hoping that DEC will turn the corner as Bob Palmer is predicting and
has been predicting now for several years. Then I can go back and contract
for them. About a year ago they eliminated their requirements that if one
left the company they could not go back. (The reason is that DEC couldn't
find enough engineers to hire...)
- Ronald Goodstein
First Shot Logic Simulation
( ESNUG 262 Item 4 ) -------------------------------------------- [5/97]
Subject: Tell Me Names! Exactly *WHO* Is Using Behavioral Compiler?
> "How come there were no papers on Behavioral Compiler? At the
> Applied Behavioral Compiler Tutorial (which was _excellent_
> btw) they mentioned about 50 companies worldwide using BC. Yet
> only one chip taped out so far! How can this be? Do companies
> really spend $150K on a tool and then not use it? Does it really
> reduce the time to market?" -- An anonymous user's response
From: [ Treated As Anon ]
I can believe it. It doesn't fit our needs just yet. We tried it and
did not like it. Synopsys folks were outraged, practically calling us
idiots for not embracing it now. But then when that Apple paper came
out last year, we thought "it must be good". Eval'd it again. My latest
check of our Synopsys licenses shows we still don't have it. Please
treat me as anon on this, OK?
- [ Treated As Anon ]
From: Ann Nunziata <NUNZIATA1@apple.com>
Hi John,
When is Synopsys going to admit that Behavioral Compiler is a failure? It's
a nice idea, but the implementation doesn't sound like it has improved any.
- Ann Nunziata
Apple Computer, Cupertino, CA
From: macafee@taec.com (David MacAfee)
Hi John,
I really appreciate your efforts to report on the SNUG conference. I use
verilog and I am happy to hear that there may be a future in using it. I
think that the comments on BC tape outs was particularly telling. I guess
I'm not the only one who doesn't "get it" yet.
- David MacAfee
Toshiba
( ESNUG 262 Item 5 ) -------------------------------------------- [5/97]
Subject: One Last Verilog Vs. VHDL Snipe Plus Cadence Tests A User's Idea
> "I hope my competition uses VHDL."
>
> - Consultant Cliff Cummings' Internet signature of many years ago.
> Cliff's new motto is: "I *still* hope my competition uses VHDL."
From: Janick Bergeron <janick@qualis.com>
The irony of it is that he did his SNUG presentation using an InFocus
projection system which was designed using VHDL! :-)
- Janick Bergeron
Qualis Design Corporation, Beaverton, OR
From: Michael Rockenhauser <rocky@Cadence.COM>
Hi John,
Concerning the mention of Re-entrant "task" statements as a possible
enhancement to the Verilog standard syntax. I'm curious to know what
you'd use this for in a synthesis context. Any ideas?
- Michael "Rocky" Rockenhauser
Cadence
( ESNUG 262 Item 6 ) -------------------------------------------- [5/97]
Subject: Cooley's Mistaken Conjecture That Synopsys Used Synplicity On ARKOS
> ACCIDENTAL ENDORSEMENT OF SYNPLICITY: On the Friday at the end of SNUG,
> the ARKOS group within Synopsys took 20 customers on a "school trip" to
> go see the actual manufacturing of the ARKOS boxes. (One of the guys in
> our group saw the ARKOS box for the first time and described it as "it
> looked like an old 50's vintage Philips refridgerator painted blue with
> a Pratt & Whitney turbofan jet-engine cooling system installed on top".)
> Once we got to see the actual PCBs used to make the ARKOS box, I laughed
> out loud. Why? Because I saw 5 QuickLogic FPGAs on that PCB. Synopsys
> doesn't have QuickLogic synthesis libraries (because QuickLogic is such a
> small FPGA vendor.) There's really only one company that has QuickLogic
> synthesis libraries: Synplicity, an FPGA synthesis rival of Synopsys,
> which means Synopsys had to use Synplicity to build ARKOS! :^)
From: sgolson@trilobyte.com (Steve Golson)
Probably not. QuickLogic does have a Synopsys library (I wrote the
first release of it for them several years ago) and it was recently
greatly improved with some assistance from Kurt Baty. In fact, three
QuickLogic employees (Venkatesh Nathamuni, Atul Ahuja, Chris Chow) were
given the "SVP Team Play Award" this quarter for their development of
DesignWare components for the QuickLogic synthesis library. (SVP is
Synopsys' Semiconductor Vendor Program.)
- Steve Golson
Trilobyte Systems
From: klein@ATB.Teradyne.COM (Larry Klein)
The bit about Synopsys not having Quicklogic synthesis libraries is not
true, and has not been true for more than 4 years. I bought and still
use, now in version 2.0, the Quicklogic Synopsys libraries, and they
work quite well. We have done more than 20 FPGA designs using it over
the years.
In fact, the shortcomings of Synplicity (it has problems with latches
and FF's using both the set and reset pins) has made it mandatory to
use Synopsys over Synplicity for most of our designs....
- Larry Klein
Teradyne
From: Nelson_Willhite@BayNetworks.COM (Nelson Willhite)
John...
I worked with QuickLogic on a large FPGA project last year, and we used
Synopsys Design Compiler to synthesize the VHDL-based design to
QuickLogic's library. The library was developed internally by QuickLogic
and was very immature, ie it didn't account properly for cell input
capacitance, etc. when mapping - it was logic mapping only. I spoke
briefly with the QuickLogic Engineer who developed the libarary (I was
teaching him a lot). Bottom line... there is a Synopsys library for
QuickLogic parts available - I've used it.
- Nelson Willhite
Bay Networks
( ESNUG 262 Item 7 ) -------------------------------------------- [5/97]
Subject: One User's Take On Quickturn Going Against ARKOS/Synopsys
> QUICKTURN & SPEEDSIM VS. ARKOS & CYCLONE. Given that QuickTurn's
> emulation technology is based on reprogramming FPGAs, while the far faster
> non-FPGA, special custom microprocessor based ARKOS is just now hitting
> the hardware emulation market, quite a few users thought that ARKOS would
> be a technological death knell for QuickTurn. QuickTurn has adeptly
> countered this threat by signing an OEM deal with IBM to resell IBM's
> ARKOS-like emulators called "Cobalt". The schuttlebutt on this is that
> although it may technologically temporarily meet the ARKOS threat, from
> a business perspective it's put QuickTurn in a bind because it's hard
> to make serious money when your future is based on reselling IBM boxes.
From: Nelson_Willhite@BayNetworks.COM (Nelson Willhite)
John...
I attended the Chrysalis, Quickturn, Systems Science Verification97 Seminar
last week. The Quickturn speaker was VERY DEFENSIVE in his presentation.
He was constantly defending Quickturn's product-line. Also, they are
trying to partition CoBALT and System Realizer to different market segments:
System Realizer: Asynchronous & Synchronous logic, gated clocks, delay
dependent clocks, < 300K gates
CoBALT: Synchronous Only, Single or Multiple clocks, Limited number of
design styles supported, > 300K gates
It will be interesting to see if they succeed pushing both technologies.
- Nelson Willhite
Bay Networks
( ESNUG 262 Item 8 ) -------------------------------------------- [5/97]
Subject: "I Hate, Loathe, Despise, and Dislike the 8051 !!!"
> AART'S TECHNOLOGY LEAK #2: In his speech, Aart displayed slides with an
> 8051 DesignWare part on them. Later at the Vendor Fair, I got a copy of
> the 8051 MacroCell Databook. This is an unannouced Synopsys product.
> In related news, it appears that the Synopsys offerings of DesignWare
> parts has grown significantly within the past year.
From: dchapman@goldmountain.com (Dave Chapman)
John,
I hate, loathe, despise, and dislike the 8051. I am currently at ANOTHER
company which designed the horrid piece of shit into a major, successful
product, only to discover that the 64k memory limitation is going to
require the complete redesign of their stuff.
It is 1997 (last time I looked). Anybody who is still using a second-rate
1970's microprocessor in new designs needs to find another career. I
understand that there is something called "Marketing", for people
who couldn't make it in Engineering . . .
- Dave Chapman
Goldmountain
( ESNUG 262 Item 9 ) -------------------------------------------- [5/97]
Subject: A Synopsys Salesdroid Defends His "Honor" & His Customer Replies
> DEATH TO SALESMEN & MARKETING PEOPLE: The overwhelming majority of
> Synopsys customers at SNUG said they very much liked the fact that no
> Synopsys sales or marketing people are allowed to attend SNUG.
>
> "Nice parties, and I DO like to meet the R&D folks. And it's a damn
> good idea to protect SNUG attendees from the Synopsys sales people."
>
> - Engineer Oren Rubinstein of Hewlett-Packard (Canada).
From: Howard Pakosh <howie@Synopsys.COM>
John - You probably had to expect a response from me on this one...
I take pride in the 15 years of experience I have in high-tech sales, the
last two here at Synopsys. As a fellow engineer, I have the greatest
respect for the work they perform. Engineers are professionals, like
doctors, accountants and lawyers (although, much more ethical) - and should
be treted as such.
The HP group in Waterloo are top-notch. Very, bleeding edge designers. I
believe that in the past 18 months here at Synopsys Canada, I have
personally visited Oren's group once. They do not need me to introduce new
Synopsys technology or review cost-of-ownership analysis with them because
Synopsys is best-in-class, as HP is. They have reviewed all the latest we
have to offer, with only Applications Engineer interaction.
I honestly believe that Oren's viewpoint may be skewed by the impressions
left by their Cadence sales rep. ;-)
- Howard Pakosh
Synopsys Sales, Canada
[ Editor's Note: Below is Oren's reply to Howard's response. - John ]
From: Oren Rubinstein <oren@waterloo.hp.com>
Thank you, Howard, and I'd like to point out that, on those occasions when
we did need the support, it was there.
Let's just say I like Synopsys better than other companies (no names :-)
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
( ESNUG 262 Item 10 ) ------------------------------------------- [5/97]
Subject: Gordon Bell Defending Ambit & His Book On High Tech Ventures
> For expert guidance on this topic, on the flight home to Boston, I picked
> up and read a book written in 1991 titled "High Tech Ventures: The Guide
> For Entrepreneurial Success". It's a good book; very insightful ...
>
> "A strategy whose objective is to claim a niche from other niche
> players or from newly established, aggressive start-ups is almost
> certain to be fatal." (pg. 236) ...
>
> But to the book's author I must laughingly give a "Don't-Do-As-I-Do,
> Do-As-I-Say...Uh...Make-That-Don't-Do-As-I-Say,-Do-As-I-Do" Award.
> Why? Because that book was written by C. Gordon Bell, the Chairman of
> Board of Directors of Ambit!!!
From: Gordon Bell, Chairman of the Board of Ambit
Dear John,
I am glad you liked my book and the insight. I'm glad to have your view on
Ambit, too. Let me comment on whether I've acted according to how I would
advise others. Rest assured, arrogance and for established rules are not
present.
Recall I was on John Sanguenetti's board at Chronologic. It established
a successful company competing with Cadence for simulation. Chronlogic
was instrumental in keeping Verilog from going down the tubes. At the
first Verilog User's group, I persuaded the group to get their IEEE
standard license. This was non-trivial because IEEE didn't want a
competitor to their and DOD's language. I thought Verilog was an
intrinsically better language and that without it, we'd go into an abyss
design-wise with just VHDL. I wrote to a friend, Anita Jones,
undersecretary of DOD's DDR&E and ask her to rescind the order to allow
Verilog. She wouldn't, and I was happy to tell her that Verilog now has
the majority of design seats.
Chronologic was successful because it FOLLOWED the dominant language
standard but yet built a product that significantly increased user's
productivity. Cadence needed a competitor in order to make them better.
Recall I headed engineering at Digital for a number of years and tried
to manage products to be competitive both internally and externally.
As for Ambit, you're right, I'm Chairman of their board. I was an
initial investor and have been advisor to the company, and helped
recruit employees:
* Unlike the company I cited in the book that created the rule,
you'll find no coffee cups or tee-shirts lying around and it's unclear
that anyone knows very much about the company e.g. size, product
characteristics, users, beta sites (if any), founding date, founders,
funders because the team has been working on the product... not hyping
it. So note, their was NO telegraphing of intentions. Recently, my
friends at Ambit simply ask a few of the folks in the design community
they respect to have dinner and to talk about design.
* Although the company cited in the book created a superior product,
the problem of converting user programs to use vectors and the
porting of software was virtually insurmountable. What is important is
being able to utilize standards so that users need not be retrained and
can utilize their base of libraries etc.. In the case in the book, a
different programming style was required even though the company
followed the "Fortran" standard.
* Finally, it is essential to have new functionality for any
product if it is going to follow a standard and create its market.
Recall I said "A niche is often the only way a fledgling company can
develop a product that will return high margins and hence, be
profitable enough to fuel growth". I believe Ambit can fill a very
large niche.
* Recall all the advice we have followed: we have not announced a
product (so what's the big deal about having dinner with a few
designers?), knowing the customer (and communicating with them), focus
groups, living with standards, creating significant value added
functionality, etc. Time will tell whether what we've created is useful
and designers want it.
* There are lots more things that the company stands for that I feel
are really significant, but I won't bore you with all those details
until the team decides to announce it.
So far it's nice to see that users are interested in products that use,
extend, and open standards. This is the flaw that the established CAD
companies seem to have missed when they've tried to build various products.
- Gordon Bell
Chairman of the Board of Ambit
( ESNUG 262 Item 11 ) ------------------------------------------- [5/97]
Subject: Formal Verification, Static Sign-off, Chrysalis, MOTIVE & PrimeTime
> AART'S TECHNOLOGY LEAK #1: During the Q&A part of Aart speech, Aart said
> to a user's question: "We are not selling a Formal Verification tool
> yet... Yet? Did I just annouce a Synopsys product?!... Clearly we're
> interested in this but, as many of you know, designs with things like
> tri-states and multipliers are very hard to test by Formal Verification.
> By the time we're ready to annouce a Formal Verification tool, we'll
> have solutions to these problems and much more." Watch out, Chyrsalis!
From: Dyson.Wilkes@swi055.ericsson.se (Dyson Wilkes)
On the "Formal Verification leak": Synopsys has been looking at formal
verification for years. The story used to be; "FV, we got it already, take
a look at compare_design".
Anyone who says, "so and so cannot be done in FV" does not know enough
about the subject". Nay, does not know about the fundamental nature of
technological development. Take "Dolly", the cloned sheep, for example:
last year that could not be done.
Maybe it's a question of tense and place. It cannot be done *today* with a
commercial tool. More specifically on the topic of tristates: 1) there have
been academic papers on solutions to this topic in publication since 4 years
ago at least. 2) ARKOS, which is cycle-based, deals with tristates so why
cannot a FV tool?
I am more of the opinion that the market is not pulling hard enough at the
FV string. Also, FV is seen as being only for the mathematicians/logicians.
To realy take advantage of FV is a big leap of faith. The tools are not
cheap so the natural step of doing both traditional verification and FV in
parallel is not attractive. On top of the s/w cost, you seem to need a
bunch of specialists working to do the FV == more additional costs in the
*short term*. I am a FV fan so all of this is a bit frustrating.
- Dyson Wilkes
Ericsson
From: Paul Smith <pauls@lsil.com>
John,
As a group leader of a newly formed 'Verification' group I am particularly
interested in all aspects of verification (naturally). Your remark on
Chrysalis is interesting. I think they are still minnows in the formal
verification category. Their strong point is equivalence (i.e.
VHDL<->Verilog). Here in the UK, a small startup looks very promising on
the formal methods side - Abstract Hardware Limited <http://www.ahl.co.uk>
We are about to do some evaluation (time permitting), but I am very
interested in their products.
- Paul Smith
LSI Logic Europe PLC
> WATCH OUT "MOTIVE" ... AND CADENCE, TOO! One of the worst kept secrets
> in Silicon Valley is that Synopsys is developing a Static Timing Analyzer
> called "PrimeTime" that will directly compete with ViewLogic's MOTIVE
> product. The implicit threat that comes to Cadence (a company built on
> Verilog and VHDL simulation) stems from this and the recent leak about
> Synopsys working on a Formal Verification product. It clearly indicates
> a future where IC Sign-Off being done *without* any simulation. (That
> is, with Static Timing checking timing, and Formal Verification checking
> functionality, who will need simulation then?)
From: silbey@colnago.asd.sgi.com (Alex Silbey)
John,
While I'm a big formal verification pundit, even I wouldn't go so far as
to say it's going to replace simulation. I always talk about multiple
"axes" of verification - FV is just one. Simulation and emulation are on
another axis. A third axis (or perhaps a blending of the two) is a new
class of FV-aided simulation tools or simulation-aided FV tools.
If you look at the Venn diagram of all bugs present in a system, simulation
is a big circle that covers much of the area, but it overlaps some outside
because of false errors. FV covers a whole bunch of the simulation area
and some outside area and some new area.
I think "third axis" tools have to be developed to cover the other parts of
the bug diagram. A good idea for a startup company: talk to companies that
have done extensive FV and simulation, then categorize the near-tapeout
or post-tapeout bugs that weren't discovered. Write a tool to find only
30-40% of these bugs, and the world will beat a path to your door.
- Alex Silbey
SGI
|
|
