I was surprized reading in this week's EE Times how Cadence & Mentor Graphics
wants to take over their customer's internal CAD functions along with some
of the design activity. Effectively they're telling their customers (mostly
CAD managers): "Please, buy our $100,000 EDA tools. Pay us $15,000 every
year for the right to phone us when you run into trouble. If you're really
stuck, hire our own 'special" on-site consultants for $250/hour to solve
your problem. If it gets really, REALLY bad, we'll talk your boss's boss
into having you, your entire CAD department and some of your fellow design
engineers all fired so *we* can do your job for you... Please, buy our
$100,000 EDA tools..." (Whoa!)
- John Cooley
the ESNUG guy
( ESNUG 210 Item 1 ) ---------------------------------------------- [2/95]
Subject: (ESNUG 209 #5) VHDL Errors Using "liban" rev. 5.1d On My FPGA
>Using the Synopsys liban program to extract the xprim_4000_5_components.vhd
>and xprim_4000_5_FTGS.vhd.E files from xprim_4000-5.db library, I got errors
>involving:
> REAL port name: A<0> VHDL port name: Ax0x
>
>I used the following command:
>
> liban -arch FTGS syn/xprim_4000-5.db -output src/xprim_4000_5 -xgen
>
>My question is: How can I tell to liban to use "(" and ")" instead of x
>in the VHDL port name? (I want A(0) instead of Ax0x.)
From: krish@neomagic.com (Krishnan Dharamrajan)
Hello John,
I had this problem. This happens when one has library cells w/ ports defined
as a BUS. While generating the library files these BUSSED ports have to be
bit-blasted and each of these ports are assigned unique timing variables.
IF you have a bus defined as A : std_logic_vectors(7 downto 0);, this will be
blasted as Ax0x, Ax1x, ... Ax7X and not as A(0), A(1), .... A(7), since
port names like A(0), A(1), .... A(7) are not allowed in VHDL.
- Krishnan Dharamrajan
NeoMagic
--- --- --- ---
From: sharp@xilinx.com (Steve Sharp)
From the looks of this question, I suspect the user may be trying to get a
RAM16x1 or RAM32x1 model. He should check out the new rev of the
Xilinx-Synopsys Interface (Xilinx part number DS-401 version 3.2 -- shipped
Jan. 95) It has many updates to the synthesis libraries AND full FTGS models
for VSS for XC3000, XC4000, and XC7000 devices plus back annotation
translation from post-route XNF to VHDL/SDF.
- Steve Sharp
Xilinx
( ESNUG 210 Item 2 ) ---------------------------------------------- [2/95]
From: [ The Horse With No Name ]
Subject: (ESNUG 207 #3) "Setting Stacksize For Large Designs & Coredumpsize"
> UNIX PROMPT> limit
>
> stacksize 8192 kbytes
> coredumpsize unlimited
>
> 8192 kbytes was not sufficient. The solution was to run the UNIX command
> "limit stacksize unlimited" (or to be safe) "limit stacksize 100000".
John, it's a good idea to mention here that people should limit their
coredumpsize to 0. Most people forget to remove coredumps and they pig
up space in a system needlessly. Hence, I recommmend "limit coredumpsize 0".
Because of company politics I'd rather sign as...
- [ The Horse With No Name ]
( ESNUG 210 Item 3 ) ---------------------------------------------- [2/95]
From: sgolson@trilobyte.com (Steve Golson)
Subject: Synopsys Design Compiler Watchlog Utility
Hi John,
Here is a favorite utility of mine. It monitors the log file being generated
by any process and annotates it with the elapsed CPU time. For Synopsys runs
it generates a CPU timestamped output like:
Beginning Resource Allocation (constraint driven)
-----------------------------
Allocating blocks in 'r1'
25:03 Allocating blocks in 'fifo'
Beginning Mapping Optimizations (Medium effort)
-------------------------------
26:02 Structuring 'fifo'
32:33 Mapping 'fifo'
In this example you can see that "Structuring 'fifo'" took (32:33 - 26:02)
6:31 CPU minutes. (It's great for long compiles; you can see what soaks up
all the time!)
Start watchlog after you start your dc_shell run, and pass it the name
of your logfile and the PID:
csh> dc_shell -f myscript.ss >& myscript.log &
[1] 1234
csh> watchlog myscript.log 1235 >& myscript.watchlog &
Note that the PID returned by csh when you start up dc_shell is the PID of
dc_shell (makes sense!) but the process that we want to watch is
dc_shell_exec, which is typically the next PID in sequence. Your OS may vary.
(To be sure you could invoke dc_shell_exec directly.)
Watchlog builds a sed script; after the monitored process exits it runs "sed"
on the log file and spits the resulting watchlog file to stdout.
Comments, bug reports, etc. are much appreciated.
- Steve Golson
Trilobyte Systems
#! /bin/sh
#
# watchlog 1.5 -- annotates a logfile w/cpu time of the process creating it
#
# Usage: watchlog logfile pid [hostname] [sleep_time]
# where
# pid = id of the process to monitor
# logfile = the logfile being created by the process
# hostname = host running the process to monitor (optional)
# sleep_time = seconds to sleep between timestamps (defaults to 60)
#
# watchlog monitors the logfile length and the elapsed cpu time of the
# process. It generates a sed script that is used to create the annotated
# log after the monitored process exits.
myname="`basename $0`"
# get args
if [ $# -lt 2 ]
then
echo "Usage: $myname logfile pid [hostname] [sleep_time]" 1>&2
exit 1
fi
logfile=$1
pid=$2
if [ $# -ge 3 -a "$3" ]
then
hostname=$3
fi
if [ $# -ge 4 ]
then
# sleep_time must be a positive integer
expr "$4" : '[0-9]*[0-9]$' > /dev/null || {
echo "$myname: bad sleep_time value: $4" 1>&2
exit 1
}
fi
# time in seconds between ps runs, defaults to 60
sleep_time=${4-60}
# file where the sed commands go
sed_script="${myname}.$$.sed"
# the ps command, using rsh if hostname exists
ps="${hostname+rsh -n} ${hostname-} /usr/bin/ps $pid"
# make a tab character to use with sed
tab=`echo 't' | tr 't' '\011'`
# make sure we can read logfile
test -r $logfile || {
echo "$myname: cannot read $logfile" 1>&2
exit 1
}
# make sure ps works
$ps > /dev/null &&
ps_info=`$ps | egrep -v "PID"` &&
test "$ps_info" || {
echo "$myname: $ps failed" 1>&2
exit 1
}
# initialize the sed script
echo "# sed script for: $myname $@" > $sed_script &&
echo "# created on `date`" >> $sed_script || {
echo "$myname: cannot write to $sed_script" 1>&2
exit 1
}
### done with initialization
# prepend a tab to every line of logfile
echo "s/^/${tab}/" >> $sed_script || {
echo "$myname: cannot write to $sed_script" 1>&2
exit 1
}
# setup prev_line_num for first time through the while loop
wc_result=`wc -l $logfile`
prev_line_num=`expr "$wc_result" : ' *\([0-9]*\)'`
while
# while the process still exists
ps_info=`$ps | egrep -v "PID"`
test "$ps_info"
do
# get the number of lines in logfile
wc_result=`wc -l $logfile`
line_num=`expr "$wc_result" : ' *\([0-9]*\)'`
# get the cpu time used by the process so far
time=`expr "$ps_info" : '.*[^0-9]\([0-9]*:[0-9][0-9]\).*'`
# format it nicely to fit in 8 spaces "1234:56 "
time=`expr " ${time}" : \
'.*\([ 0-9][ 0-9][ 0-9][ 0-9]:[0-9][0-9]\)'`
# if logfile has grown
if expr "$line_num" != "$prev_line_num" > /dev/null
then
# mark previous line with current time
echo "${prev_line_num}s/^/${time}/" >> $sed_script || {
echo "$myname: cannot write to $sed_script" 1>&2
exit 1
}
# time has been used
time=""
fi
prev_line_num=$line_num
sleep $sleep_time
done
# process has finished
# if time hasn't been used then put it on the last line found
if [ "$time" ]
then
echo "${line_num}s/^/${time}/" >> $sed_script || {
echo "$myname: cannot write to $sed_script" 1>&2
exit 1
}
fi
# run sed to make annotated logfile
# unfortunately sed has a bogus 200 command limit, so...
# split up sed_script
split -190 $sed_script ${sed_script}.
# build up a pipe of multiple sed commands
notfirst=""
for file in `/bin/ls ${sed_script}.??`
do
if [ "$notfirst" ]
then
# add to the pipe
command="$command | sed -f $file"
else
# first sed in the pipe, so add logfile
command="sed -f $file $logfile"
notfirst="true"
fi
done
# execute the pipe
eval $command
# cleanup
/bin/rm -f $sed_script ${sed_script}.??
exit 0
( ESNUG 210 Item 4 ) ---------------------------------------------- [2/95]
From: zeisu@snipe.dwe.co.kr (Jae-Soo Yoon)
Subject: Positive Edge Oriented "balance_registers" Creates Poor Designs
John,
I was trying to break down a design block into several pipelined stages using
the balance_registers command. The block is similar to an array multiplier
to which I attached three rows of registers to make it four-stage pipelined.
My whole design basically uses a negative edge clock for the storage elements,
and thus I described the pipeline registers to work at the neg edge w/ WAIT
statements as usual. Once I read in the design and optimized it with low
mapping effort, it, of course, created the original block with three rows of
neg edge F/Fs connected to the output port.
Then I recreated clock with my desired cycle and issued balance_registers
command. What I got after the execution was essentially a pipelined design
with all the F/Fs having *positive* edge clocks! Then I gave it an exact
F/F type attribute and repeated the above procedure. (I noticed that then it
printed "preferred register" as FDN1A, which was the neg edge F/F that I
told it to use.) It then attached an *inverter* to the global clock net and
was still treating the whole design as if using a positive clock!
I looked up every reference I could find to make balance_registers use
negative edge clock, but there are none. Is it a bug or a feature that I'm
missing here? I can't believe a synthesis tool creating an opposite result
from the original user's intention given by the HDL description. Please help.
- Jae-Soo Yoon
Daewoo Electronics Co., Ltd.
( ESNUG 210 Networking Section ) ---------------------------------- [2/95]
Milpitas, CA -- Quantum seeks ASIC Engineer w/ 2+ years Verilog & Synopsys
exp. ATA and PCMICA exp. a plus. Please, NO recruiters. "jzaidi@qntm.com"
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