>Editor's Question: How did the SNUG Europe '94 meeting go? Let's see
>some reports! What were the best & worst presentations/talks? Was
>language an issue? How many actual users attended? Did Synopsys
>sales & marketing reps take over the microphones and drone for hours on
>end? Any good after hours parties? Hot gossip? Inquiring minds want
>to know!
From: Dennis_Brophy@pdxml1.mentorg.com (Dennis Brophy)
From those in Mentor, I heard Synopsys did not win any points having a two
day users group meeting during EuroDAC. If it was not enough to offer
their commercial message on the exhibit floor and briefing meetings, they
also removed conference attendees from the show itself. So much for
building a good reputation.
- Dennis Brophy
Mentor Graphics
( ESNUG 197 Item 1 ) ---------------------------------------------- [10/6/94]
Subject: (ESNUG 195 #2) "DesignWare Is A Carefully Crafted Marketing Ploy"
> 5. Is there a genuine need to have multiple DesignWare licenses? Do the
> tools lock up a license for an extended period of time? Can they even be
> effectively shared? It seems that one license for a given DesignWare
> library should be sufficient for all but the largest sites.
From: mark@abekas.com (Mark Andrews)
The bad news here is, yes, the tools lock up a license for an extended
period of time. In fact, the license can stay checked out for the whole
compile time, even a later incremental compile will recheck out the
license unless you "ungroup -flatten" the DesignWare design first. The
practical reality is that you may need a DesignWare license for each seat
of Design Compiler that you are using. We only have two seats of
Design Compiler and we frequently need two seats of DesignWare.
- Mark Andrews
Abekas Video Systems Inc.
---- ---- ---- ----
> I've evaluated the "fast carry-lookahead" implementation of the adder
> using two different ASIC libraries. In comparison to the standard
> carry-lookahead implementation, I found for some cases a degradation in
> speed, and in some cases a 2% to 4% speedup at the expense of 10% to 20%
> in area. The Wallace tree multiplier is quite useful (and the vector
> adder is a minor variant of this), but I was able to write my own
> parameterized Wallace tree generator which, when coupled with a standard
> Synopsys carry-lookahead adder, outperforms the DesignWare version.
From: John_Swan-ACIC00@email.mot.com (John Swan)
Now that's interesting. On the day I received this ESNUG posting I also
completed an evaluation of the Synopsys' "fast carry-lookahead" adder with
much different results. (Remember, the "carry look-ahead" implementation is
included in the standard "foundation" DesignWare ALU library; the "fast carry
look-ahead" adder is in the extra cost SynLib-ALU license.)
Unlike the above results, my tests show that the "fast carry look-ahead" adder
does show a significant increase in speed with some increase in area. In my
evaluation I increased the timing constraints on successive compiles, starting
each optimize with a freshly elaborated design to get a common starting point.
I optimized each trial one time with a medium mapping effort. My test
implements a fairly wide adder. Here are my results:
Speed Area
factor Factor Implementation
------- ------- ----------------
1.00 1.00 Fastest "carry look-ahead" adder time.
0.97 1.15 The original user's results w/ "fast carry look-ahead"
0.56 1.43 My fastest results for the "fast carry look-ahead".
0.66 1.30 \
0.74 1.19 > Other fast carry implementations show speed/area
0.83 1.14 / trade off.
- John Swan
Motorola Corporate Research
To fellow Motorolans: I want to form an ESNUG MO-SIG! E-mail me!
---- ---- ---- ----
[ Editor's Note: Charles is addressing the overall DesignWare issue
in his response bellow, not any above specific quote. - John Cooley ]
From: cwg@Synopsys.COM (Charles Gopen)
John,
I need to clarify what DesignWare is and how customers pay for it. Today
DesignWare is sold in a single Foundation Library consisting of four basic
families of reusable synthesizable designs: Advanced Math, ALU, Basic
Sequential components and Fault Tolerance components. This library
presently contains something over 50 designs. The customer pays for this on
an annual subscription basis, like a magazine subscription, not as a
maintenance product. This annual subscription provides the customer with
all new component designs and allows him to use them in an unlimited number
of his designs. Several million dollars has already gone into the
development of the library and we will continue to add new components and
more functionality (new views) with each new release of the library, but at
a constant cost to the customer, making each new annual subscription to the
user more valuable. Other companies in the industry have a similar annual
licensing schemes.
DesignWare is an open system, that is a customer can desgign his own
components and other third parties can develop their own Designware parts.
Any existing customer design can be reused without making it a DesignWare
component. If the customer wants to make his design into a DesignWare part,
so it can be automatically linked into High Level Optimization, he can do
so through the DesignWare Developer. The Designware Developer is a tool we
sell that allows a design to be "encapsulated" and thus become a DesignWare
part.
- Charles Gopen
Synopsys DesignWare Marketing
( ESNUG 197 Item 2 ) ---------------------------------------------- [10/6/94]
Subject: (ESNUG 194 #3 195 #1 196 #3) "Hold On Single FF Breaks Gate Array Size!"
>Concerning clock skew for register self loops in v3.1a use a hidden variable:
>"tvc_uncertainty_handle_self_loops = 1" ... To obtain the more accurate
>behavior of no clock skew (uncertainty) for such paths, set the variable to
>true, but note that runtime and memory usage may increase significantly.
From: stropparo@pasta.enet.dec.com (Peter A. Stropparo)
John, "runtime and memory usage may increase significantly" -- this is an
understatement! Memory usage went up by 2x and runtime by 3x!
- Peter A. Stropparo
Digital Equipment Corporation
( ESNUG 197 Item 3 ) ---------------------------------------------- [10/6/94]
Subject: (ESNUG 195 #0 196 #2 ) "Synopsys Announcing DesignPower"
>I wouldn't start counting your sheep just yet. Many Verilog-XL users have
>written "toggle count" PLI programs to estimate the switching frequency of
>their gates. They multiply the frequency times some AC power factor to get
>the total power consumption. This was done even before Synopsys was around.
From: mark_indovina@pts.mot.com (Mark Indovina)
Hi John,
I must concurr with the above user; a toggle test PLI function source code
is shipped with the Cadence Verilog distribution. For example, take a peek
at the May 1-4, 1994 Proceeding of the IEEE 1994 Custom Integrated Circuits
Conference. Of particular interest is paper 11.5 "Power Analysis for
Semi-Custom Design", written by some dudes at Motorola's Advanced Design
Technology Center in Tempe, AZ. This paper describes some internally
developed tools called "Entice" and "Aspen". Entice is a circuit
characterization tool; Aspen is a power analysis system (which is primarily
C/Verilog PLI) which reads the Entice database for power vectors when a cell
port transition is detected in the simulator. No GUI but what the hey ...
look for it at Babagges!
- Mark A. Indovina
Motorola
---- ---- ---- ----
From: stevem@siecomp.com (Steve McChrystal)
John,
It is not clear from your comments on DesignPower what they actually are
doing, but the idea of calculating dynamic power during VHDL (or Verilog)
simulation is due.
With an event driven simulator, why can't a quantum of power be tallied
with each transition of a CMOS gate? The situation is similar to
back-annotated timing simulation, where an intrinsic delay is added to
a loading delay calculated from estimated or layout interconnect data.
The gate model could treat power the same way, with a characterized
internal power and a loading derived interconnect power.
Of course it would suffer the same problem as detailed timing analysis
- you'd have to run real simulations, but this is far better than the
various guess methods used currently. Any ideas out there ?
- Steve McChrystal
Siemens ICD, Cupertino, CA
---- ---- ---- ----
>If you have to use simulation vectors to estimate power, then DesignPower is
>nothing like a static timing analyzer. Worse yet, if you expect to run
>simulations in the middle of a synthesis job to see how well you are meeting
>your power budget, you better be prepared to wait a while.
From: kgomes@Synopsys.COM (Kelly Gomes) [ plus Synopsys R & D and CAE ]
DesignPower is a new gate-level power analysis tool that enables RTL and
gate level design tradeoffs and library tradeoffs for power. The really
new technology here is the probabilistic approach and the robust power
model that enables the designers to do RTL-level, gate-level and library
experimentation. It *is* analogous to static timing analysis in its usage
model.
This tool will help designers in estimating the power consumption early
in the design cycle & guide them to ultimately meet their power constraint
specification. This has been accomplished by two fundamental approaches:
The first approach is based on probabilistic estimation technique. This
approach gives the designer a fast power estimation early in the design
cycle without having to simulate the design.
This probability based estimation technique uses switching activity
information provided by the designer only for the "primary inputs".
DesignPower uses this switching activity to compute the toggle rates
& static probability for all the internal nodes (also referred to as
switching activity). Using switching activity of internal nodes in
the design in conjunction with the voltage & capacitance values from
the technology library, DesignPower calculates the final power
estimation of the design.
In the second approach, DesignPower uses switching activity based on
the information generated by VHDL or Verilog gate level simulator. The
simulator provides switching activity for all the internal nodes and
this is used to calculate the power estimate of the design.
An important fact to note here is that DesignPower calculates Static
as well as Dynamic power dissipation in the design. Both the components
of the dynamic power dissipation; Switching power dissipation and
Internal power dissipation; are taken into consideration while
computing the total power dissipation. Thus we can assure the user
base that DesignPower does far more complex calculations using
different complex algorithms than simply multiply the frequency with
AC power factor to get the total power consumption.
- Kelly Gomes, Synopsys Marketing
[ Synopsys R & D ]
[ Synopsys Corporate Applications Engineering ]
( ESNUG 197 Item 4 ) ---------------------------------------------- [10/6/94]
From: mkphilli@netcom.com (Mike Phillips)
Subject: How to Get Synopsys To Write VHDL Structural In Reverse Order?
Does anyone know how to get Synopsys to write out a VHDL structural netlist
in the reverse order? Synopsys currently writes the structural netlist
from the top of the hierarchy to the bottom of the hierarchy when writing
to an output file. The reason this is needed is because one of our VHDL
simulators (Model Technologies) prefers to compile starting from the bottom
of the hierarchy.
- Mike Phillips
E-Systems
( ESNUG 197 Networking Section ) ---------------------------------- [10/6/94]
Scotts Valley, CA: Silicon Engineering Inc. ( SEI ) seeking ASIC/full custom
IC designers with HDL & synthesis experience. E-mail "George" lambo@sei.com
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