> From: cjitlal@asic.sc.ti.com (Colin Jitlal)
> Subject: ESNUG Archives
>
> John,
>
> Can you tell me if the ESNUG articles are archived somewhere? Having
> access to this wealth of information on-line would be superb. Dare I
> say... the SolvIt/WAIS server?
>
> - Colin Jitlal
> Texas Instruments ASIC
Editor's Note: Right now, anyone who wants ESNUG archives can only get
them by mailing me a letter saying "Waaa! I want archives!" (I then
reply with the form & instructions to have the archives automatically
e-mailed to you.) At present, ESNUG archives are provided independently
of Synopsys, Inc. (But I'm currently talking with Synopsys about ESNUG
archives also being incorporated into SolvIt. I'll keep you informed
how it goes.)
- John Cooley
the ESNUG guy
( ESNUG 188 Item 1 ) ---------------------------------------------- [5/4/94]
Subject: (ESNUG 187 #2) Synopsys Doesn't Use FLEXLM Like Everyone Else!
> Now, when the first user's compile job is finished, you would expect the
> "Design_Compiler" token to be returned to the token pool for other users.
> Not in Synopsys. (FLEXLM does not automatically check licenses back
> in. Instead, the auto_timeout system goes around the network every 15 or
> 30 seconds and takes back any unused tokens. This is what Cadence,
> Viewlogic and Logic Modeling do.) Synopsys' implementation of FLEXLM does
> not support auto_timeout -- the user must manually giveup the token when
> he is done with it. Synopsys tells us they chose to do this for security
> reasons. It seems to me they just want to sell more licenses.
>
> Does anyone have any workarounds? Does anyone agree with me? Synopsys told
> us they took this feature out because many customers requested it. If I
> were Synopsys, I would have made it optional and under the control of the
> system administrator.
---- ---- ----
From: brien@acuson.com (Brien Anderson)
Hello John, With respect to this topic, I agree with the user.
Our past experience with Design Ware, we use the command remove_license
HDL_Compiler in our scripts to remove the HDL license when the Verilog
is read in. An auto feature for this would be nice.
- Brien Anderson
Acuson
---- ---- ----
From: dan_westerberg@wellfleet.com (Dan Westerberg)
John, I fully and completely agree with this user! With the exorbitant cost
of a Synopsys license it's imperative to squeeze every drop of productivity
from each and every license.
To use our Synopsys licenses more efficiently, we require that all compiles
be done in a batch-mode fashion. Interactive dc_shell sessions are only
tolerated after a user has checked with the entire user community and is
granted permission to lock-up a license for a while.
We use the Multiple Device Queueing System (MDQS) to ration and control access
to our licenses. MDQS is a generic queueing system originally written for
print spooling, but has been enhanced such that anything can service queues.
For example, we have defined "devices" that represent each of our Synopsys
licenses. These devices are actually shell-servers that pull a submitted
Synopsys job off from a queue and invoke a shell for that job to run under.
We have multiple queues defined that our serviced by the synopsys "devices".
Some queues are defined to be serviced in a serial fashion by a single device,
as well as queues that are service by the next available device. Queues also
are assigned a priority level which determines in what order the devices
service the various queues. Jobs can also be assigned priorities within
queues, so as to be able to force jobs to the front of a queue.
All in all, MDQS has proven quite effective and has allowed us to get a
maximum amount of work done with a minimum of licenses.
Another complaint I have with Synopsys is that if a license isn't available
dc_shell errors and exits. I would prefer to see dc_shell sit and poll,
waiting for a license to become available.
Synopsys' answer to this is that it's possible for me, the designer, to
perform this kind of license checking and polling in my scripts. I feel
it's a waste of my time and effort to recreate a low level function that
should already be provided by the licensing system.
Thanks, I feel a little better now... ;-)
- Dan Westerberg
Wellfleet Communications
P.S. - MDQS was developed at the U.S. Army Ballistic Research Laboratory and
as such is in the public domain. Should be available on anonymous FTP sites,
but I forget where I got my copy. I'm running version 2.16.
( ESNUG 188 Item 2 ) ---------------------------------------------- [5/4/94]
From: uunet!nvidia!fiedler (Larry Fiedler)
Subject: Getting Synopsys Man Pages Without Tying Up A Synopsys Licence
Here's a UNIX csh alias that I (and other ESNUG readers may) find useful:
alias synman man -M /home/synopsys_30b/doc/syn/man
where /home/synopsys_30b is one's Synopsys root directory.
I use this when writing synopsys shell scripts and don't want to dip into
dc_shell or design_analyzer to get command syntax or descriptions. (It
relies on the fact that Synopsys' on-line documentation is in man page
friendly formats.) Here's the alias in action:
>synman set_structure
Command Reference 2. Synopsys Commands set_structure
NAME
set_structure Determines if a design is structured
during optimization.
SYNTAX
...
I also suppose one could add it to their MANPATH environment variable instead.
- Larry Fiedler
NVidia
( ESNUG 188 Item 3 ) ---------------------------------------------- [5/4/94]
Subject: (ESNUG 182 #2) VHDL-Xilinx-Synopsys 3.0c Builds Very Large Designs
> A colleague here has run up against a strange VHDL-Xilinx-Synopsys problem.
> He's trying to synthesize three structures, each of which is 16 3-input
> AND gates OR'd together. Synopsys generates an 18-level deep OR chain
> which turns out to have an enormous propagation delay of ~120 ns after
> placement and routing! We tried everything we can think of to get Synopsys
> to minimize the logic to fewer levels (like three), with no improvement at
> all. Neither a Synopsys consultant nor a Xilinx Synopsys FAE could help.
--- --- ---
From: brad@hdls.COM (Brad Eltman)
John,
This ESNUG post really rang a bell for me. Wow it has been so many years in
Verilog that I saw this and golly it is still there in VHDL! The user's
problem lies in this chunk of his code:
> process(ints,int_cntl_hb,int_cntl_lb,temp0,temp1,temp2)
> variable t0,t1,t2: std_logic;
> begin
> t0 := '0';
> t1 := '0';
> t2 := '0';
> temp0 <= (ints and (not int_cntl_hb) and int_cntl_lb);
> temp1 <= (ints and int_cntl_hb and (not int_cntl_lb));
> temp2 <= (ints and int_cntl_hb and int_cntl_lb);
> for i in 0 to 15 loop
> t0 := t0 or temp0(i);
> t1 := t1 or temp1(i);
> t2 := t2 or temp2(i);
> end loop;
> int_out <= t2&t1&t0;
> end process;
The problem stems from that little "for" loop. When Synopsys reads in the
VHDL description and begins parsing and mapping to generic logic it unrolls
the loop into a chain of 15 OR gates (you only need 15 because the gate at
end has 2 inputs). Unfortunately there are no rules available to do a good
job of finding wider gates.
In Verilog we solved this problem with a function that does an OR reduce
across the 16 variables.
In VHDL (which we no longer use internally) we have a package called
hdls_or_reduce that does the equivalent. You can use attributes for the
range and make it general purpose. This will solve the OR gate chaining
problem.
- Brad Eltman
HDL Systems, Corp.
( ESNUG 188 Item 4 ) ---------------------------------------------- [5/4/94]
From: arthur@wrksys.enet.dec.com (Edward S. Arthur)
Subject: Unhappy With Two Verilog/Synopsys Gotchas
John,
We've had a flurry of problems crop up lately with Verilog HDL code which
simulates fine however the post-Synopsys output is not what we expected...
output [3:0] buf0;
:
reg [7:0] buf0;
// buf0 feeds another stage buf1 however only 4 bits of buf0
// leave the module - Synopsys removed all references and gates
// to buf0[7:4]!!
Verilog doesn't catch this; Verilint doesn't catch this; Synopsys doesn't
catch this.
My second issue is over specified casex statements:
casex(ThreeBit)
0x0: if (A)
:
000: if (B)
:
These two cases were merged as were any references to A and B. Again,
Verilog, Verilint and Synopsys failed to warn and the HDL simulated
properly. Any other "gotchas" roaming about?
(In fairness to Verilint their next release is supposed to catch both
of these problems.)
- Edward S. Arthur
Digital Equipment Corporation
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