From: bvitro@supermac.com (Bill Vitro)
Subject: A Future Synopsys Press Release? :)
John,
Here's a little humor based on a conversation I had with my ViewLogic
(or is that VIEWlogic, or maybe ViEwLoGiC...whatever) sales rep.
- Bill Vitro
SuperMac
For Immediate Release:
MOUNTAIN VIEW, CA., Jan 31, 1994 -- In another ground-breaking
announcement, Synopsys Inc.(NASDAQ: SYN), a Mountain View, CA
electronic design tool automation company has announced plans to
acquire Black & Decker Tools, Inc. (AMEX:BND), based in Normal, IL.,
for an estimated $12 Billion in cash and stock.
Dr. Aart De Geus, CEO, CFO and BMOC of Synopsys was quoted: "We intend
to be the one-stop shop for all the EDA communities tool needs. Never
before has there been a company able to provide such a complete set
of tools in this fashion. We are now able, with the acquisition of
Black & Decker, to provide the customer with a total top-down,
front-to-back and side-by-side design solution."
According to Fred Decker, CEO of Black & Decker, "Synopsys came in
and offered us wheelbarrows full of money. We're not talking 1's and
5's here. This was wheelbarrows full of 100s! We had no idea who
these guys were but they felt they'd corner the entire hardware
market if they bought us. For $12 Billion, we readily agreed!"
Dr. De Geus will be named BMOC of Black & Decker, and Fred Decker plans
to retire on a large island in the South Pacific.
( ESNUG 174 Item 1 ) ---------------------------------------------- [2/1/93]
Subject: (ESNUG 173 #2) 3.0c DC + High Map Effort = Crashing Workstations
>John, thought your readers might be interested in a problem I'm having using
>"Version v3.0c -- Nov 12, 1993" (which we just received and loaded).
>If I compile Verilog source with the design_compiler using '-map_effort
>high', after about 15 minutes the work station will trap to the boot prompt
>with the message "watchdog timeout"! This bug crashes my workstation!
--- --- --- ---
From: gwolsk@sei.com (Guntram Wolski)
This is going to be a tough one -- Sun and Synopsys are going to have to
work together on this. I bet that Synopsys is going to tell you: "If an
application crashes a workstation, the bug must be in the OS, since the OS
didn't catch the error. This is just a piece of software that tickled the
OS bug...." (Normally the program should be killed by the OS since it did
something illegal....).
There was a bug like this in SUNOS 4.1.1 and Synopsys that required you to
upgrade to 4.1.2.
- Guntram Wolski
Silicon Engineering, Inc.
--- --- --- ---
From: mark_indovina@pts.mot.com (Mark Indovina)
One of our sys-admin guys is in the process (I believe it was just shipped )
of configuring a Sparc10 with SunOS 4.1.3c. This is the latest release and
is supposed to have all 4.1.3a & 4.1.3b patches included.
FYI, the local synopsys AE has been here twice. After being somewhat
amazed that he could even crash the system, he has taken data and left to
run a test case at his office. I don't think he has filed a 'star' yet.
- Mark A. Indovina
Motorola
( ESNUG 174 Item 2 ) ---------------------------------------------- [2/1/93]
Subject: (ESNUG 173 #5) "Xilinx Synthesis with Synopsys"
> We are embarking on a project where we expect to do silicon compilation
> targetted to Xilinx FPGAs using Synopsys synthesis. Could readers please
> post on ESNUG in name or anonymously their experiences using Synopsys with
> Xilinx FPGAs?
From: david@subasic.sciatl.com (David Burleson)
John, we constantly use Synopsys to synthesize to Xilinx. Both as a final
target and as a means for testing ASICs. It is a proven path that works.
That's the good news.
There are two Synopsys products for synthesizing to Xilinx: Design Compiler
and FPGA Compiler. First I will talk about Design Compiler.
DC does not make use of all the nice features of Xilinx CLB structure. It
does not use the clock enables, carry lookahead logic, etc. So the logic
synthesized is not as efficient as it could be. This translates into large,
slow FPGAs.
There is a newer product called FPGA Compiler. It is supposed to be more
efficient at synthesizing to FPGAs. These gains are produced by using
"block" functions like adders and counter and by using more of the features
of the CLBs.
We spent a couple of weeks recently taking a design that had been compiled
with Design Compiler and recompiling (from the source) with FPGA compiler.
What we got after a lot of pain was an even larger, slower design!
Design Compiler is useful, as long as you can live with it's limitations.
In my opinion, I do not believe FPGA compiler is a working product yet.
> Did the compiler generate a functionally correct layout?
The compiler does not produce a layout, you need the Xilinx tools to place
and route the design. The compiler does produce a functionally correct
design (as long as you know how to write verilog or VHDL).
- David Burleson
Scientific Atlanta
( ESNUG 174 Item 3 ) ---------------------------------------------- [2/1/93]
Subject: (ESNUG 173 #1) "Synopsys IEEE VHDL Libraries Simulate Wrong"
>From: [ Synopsys Corporate Applications Engineering ]
>
>We have duplicated this problem reported ... it involves the "built-in"
>IEEE Packages used by the VHDL System Simulator.
>
>To summarize, it is possible that a customer may experience different
>simulation results when comparing simulation runs using the "built-in"
>IEEE packages versus the VHDL (external) source files for the IEEE packages.
>There is a defect in the "built-in" version of the IEEE packages.
>
>WORKAROUND:
>
>To workaround this problem, analyze and reference ("use") the VHDL source
>files for the IEEE packages instead of the built-in IEEE packages.
--- --- --- ---
From: "Mark A. Hilmantel" <hilmantl@rapnet.sanders.lockheed.com>
An additional "fix" Synopsys should make here is to remove all of their
packages from the IEEE library. The IEEE library should only be used for
packages which are IEEE standards. Packages from Synopsys should be in
another library (how about "/SYNOPSYS"?) :-) Synopsys packages in the
IEEE library cause problems when multiple vendor VHDL tools are used.
It also appears from the suggested workaround that Synopsys tools do not
allow the user to create a library called IEEE, but requires the use of the
(broken) built-in library. This too needs fixing.
- Mark A. Hilmantel
Lockheed Sanders
[ Editor's Note: I spoke with one user who wanted to anonymously point
out that if you don't use the built in IEEE VHDL libraries and instead
use the elaborated VHDL libries to get around this bug, your simulation
runs will be considerably slower. Since this bug only effects the
fairly weird VHDL functions (stuff like ABS and the modulus functions),
I'd advise checking your code for these weird functions. If you
don't use them, use the faster built in IEEE VHDL libraries. (I would
like to get a definative list of "weird" functions effected by this bug
to post in ESNUG so people could use it to check against their source
VHDL.) Anyone at Synopsys care to assist? (hint! hint!) ;^) - John ]
( ESNUG 174 Item 4 ) ---------------------------------------------- [2/1/93]
From: [ The Synopsys CAEs and The Synopsys Semiconductor Vendor Program ]
Subject: ( ESNUG 172 #5 ) "FPGA Compiler Bug 'set_pad_type' hates Xilinx"
In ESNUG posting 172, item 5, Saad Guedira commented that "the command
'set_pad_type' doesn't work with the Xilinx XC4000 library" for pullups
and pulldown resistors.
In the Synopsys environment, pullup and pulldown resistors along with the
associated input and output pads need to be described as multi-cell pads so
that they may be connected together. At the moment, the Xilinx supplied
libraries do not describe their pads and resistors in this manner. This
causes connection class violations in the Synopsys environment which
prevents pullup and pulldown resistors from being inferred or instantiated
from the Xilinx supplied libraries.
Xilinx is in the process of correcting this problem in their libraries,
and a new library is planned to be available in the Spring of 1994.
- [ Synopsys Corporate Applications Engineering ]
- [ Synopsys Semiconductor Vendor Program ]
( ESNUG 174 Item 5 ) ---------------------------------------------- [2/1/93]
From: kjhass@sandia.gov (Joe Hass)
Subject: Synopsys & Tanner Not Playing Nice Together
John-
We are trying to link our Synopsys tools with the layout software from
Tanner Research. We want to supply an EDIF netlist for Tanner's automatic
place-and-route, and we'd like to feed parasitic capacitance values from
the layout back in to synthesis. We're having some trouble with the EDIF
interface, so I thought I would pose the problem to ESNUG before we
reinvent the wheel...has anyone mated Synopsys and Tanner?
- Joe Hass
Sandia National Labs
( ESNUG 174 Item 6 ) ---------------------------------------------- [2/1/93]
From: andyle@adaptec.com (Andy Le x3241)
Subject: How to Infer R/S flip-flop in Synopsys
I would like to know if any Synopsys users had been able to infer R/S
flip-flop in Synopsys using Verilog or VHDL RTL code. (Prefer Verilog)
Please post the solution on ESNUG. Thanks...
- Andy Le
Adaptec
( ESNUG 174 Item 7 ) ---------------------------------------------- [2/1/93]
From: [ Being Forced Into Buying DC-Expert? ]
Subject: Latch Timing Issues
John, please post me anonymously.
We are seeing a problem with latch timing and dc-professional.
Synopsys is timing our latches, and reporting setup violations to the
falling edge of the clock. (Yet the Toshiba databook clearly specs setup
for an LD2 to the rising edge.) To make matters worse if we happen to run
on a machine with a dc-expert license, the compile invokes "time borrowing"
and masks the problem! We feel that timing setup to the wrong clock edge
is clearly a bug and users should not have to spend more money for a
dc-expert license that we do not need.
Does anyone have a money saving workaround so we're not...
- [ Being Forced Into Buying DC-Expert ]
[ Editor's Note: Reading this letter I'm not sure if there is a problem with
not having DC-Expert as much as an error in the Toshiba Synopsys libraries.
I don't know this for a fact -- just a gut hunch because one accidental
switch of "rising edge" to "falling edge" in the lib would do this. If you
have access to the Toshiba ".lib" source, you should look into this. - John ]
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