( ESNUG 139 Item 1 ) ----------------------------------------------- [8/6/93]
From: cjclark@intellitech.com (cjclark)
Subject: Requesting ESNUG Archives
> ESNUG 134: It Initializes in VHDL But Not After Synthesis
> ESNUG 136: (ESNUG 132 #1) "Working with MUXes using Verilog and VHDL"
> ESNUG 136: VHDL Compiler problems
>
> (If you don't have a copy of the ESNUG archives, send e-mail to
> "khaddock@intellitech.com" and Kareen will send them to you!)
John,
This generated several requests, but without the full info.
Don't forget to remind them that this is a moderated group and that
we are only sending the archives if they give the company name, etc.
in the following format:
NAME: Christopher J. Clark
COMPANY NAME: Intellitech Corp.
ADDRESS 1: 66 Route 25
ADDRESS 2:
ADDRESS 3:
CITY, STATE, ZIP: Meredith, NH 03253
BUS. PH: 603-279-6308
BUS. FX: 603-279-5135
EMAIL ADDRESS: cjclark@intellitech.com
ESNUG POSTS: 59,65-75
- CJ Clark
Intellitech
( ESNUG 139 Item 2 ) ----------------------------------------------- [8/6/93]
Subject: ( ESNUG 138 Item 2) "CMOS modelling & characterize"
>When I try to generate a loading constraint file using the "characterize"
>followed by "write_script" commands, the file generated contains statements
>of the form:
>
> "set_load -pin....." and
> "set_load -wire...."
>
>But this is not correct since I am using a CMOS technology; and for CMOS
>it is not supposed to split it into pin & wire loads. (Incidentally, the
>same script generated the correct statements in Synopsys 2.2b!)
From: jefff@mars.sps.mot.com (Jeff Freeman)
There is a typo in the documentation of 3.0a.
"set_load -wire_load" IS a valid command for the CMOS model.
- Jeff Freeman
Motorola
( ESNUG 139 Item 3 ) ----------------------------------------------- [8/6/93]
From: "Richard Abato" <rpa@vnet.IBM.COM>
Subject: Synopsys VHDL Simulator Bug!
We are using the Synopsys VHDL Simulator/Debugger Version 3.0a on an
IBM Risc System 6000. Sometimes when we attempt to do a print from the
waveform window we get the following message in a popup message box:
SYS_ERROR
Next_Signal_States backed up
In the message box is a button (If I remember correctly it says OK). If I
push this button everything hangs up and I must kill the waves process
from the operating system. Killing the simulator doesn't kill the waves
display and attempting to kill the waves window using either the waves
kill button or the window manager kill button doesn't work. If I don't
press the button it just sits doing nothing except using cpu time!
We usually only see this when we have a large number of waveforms
in the display.
Any ideas? One suggestion from Synopsys was that /tmp was getting filled
but I checked that the last time I got the message it was only 3% full.
- Rich Abato
International Business Machines
( ESNUG 139 Item 4 ) ----------------------------------------------- [8/6/93]
From: NANAVATI@RALVM29.VNET.IBM.COM
Subject: Funky Error During PLA to VHDL conversion
I read in a design expressed in PLA design format. I then set
vhdlout_equations = "TRUE"
I then tried to write out the design in vhdl format. I got an error message
saying........
Error: The current setting, 'CONV_PACK_bicarb.plaout', of
'vhdlout_package_naming_style' does not produce a valid
VHDL identifier. (VHDL-267)
Does anyone know what's going on ? I tried to figure it out from the design
compiler and VHDL compiler manuals but no such luck.
- Sameer Nanavati
International Business Machines
( ESNUG 139 Item 5 ) ----------------------------------------------- [8/6/93]
From: toma@romulus.cray.com (Thomas Arneberg)
Subject: Want Opinions on Synopsys Training
Hi, John. Would you happen to have any online info on Training Courses at
Synopsys that you could email me? I haven't called them yet, but past
experience with other vendors tells me that it may take a while to track
down someone there who can actually use email.
(Also, I was thinking that maybe you could pass on some objective
evaulations of their training classes.)
- Tom Arneberg
Cray Research
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