Editor's Note: Yup!, that's me in the Networking Section! ;^) - John
( Post 124 Item 1 ) --------------------------------------------------------
From: [ Another Anonymous ESNUG Subscriber! ]
Subject: A Xilinx/Synopsys/Viewlogic FPGA Story
John;
Here's a description of an FPGA design migrated to an ASIC using
Synopsys. Please edit my name out, as I wish to remain anonymous.
--------
Here's a story about Xilinx 4005 FPGAs, Viewlogic, Xilinx tools,
and Synopsys Design Compiler. I haven't used the FPGA compiler.
Whenever I mention Synopsys, I really mean the design compiler.
In the summer of 92, I designed a serial comm controller using a
Xilinx 4005. The spec called for 36 serial channels, and since that
was too much to fit in the 4005, I split it into three 4005, 12
channels in each.
I used Viewlogic for schematic entry and functional simulation,
then used Xilinx PPR, and as it turned out, I could not fit 12
channels into one 4005, so I went to eight while awaiting the 4006.
The xdelay tool in Xilinx gave a max frequency of 18Mhz, but after
a very difficult, complex and lengthy process, I was able to back
annotate the Viewlogic database to perform timing simulations, and
through that and lab testing, we found out that the part would not
run at more that 4 -5 MHz. So back again to surgery to half the
number of channels to four, and we got parts that ran at the
required speed.
In the fall of 92, we were able to obtain a beta version of the
Xilinx-Synopsys interface (XSI), I loaded that up on a Sparc2. What
I wanted to do was to edifout a netlist from Viewlogic, read that
into synopsys, and have synopsys optimize the circuit, write an
edif schematic view, read it back into viewlogic and there into
PPR. I thought that through that process I could possibly compact
the design to fit the 12 channel design into a 4006 with good
performance.
The results: Synopsys read the edif net list and displayed the
circuit but complained about parts not found. Investigating that
problem, I discovered that the symbols names in the synopsys
library were not the same as in the viewlogic library. Since I was
not going to try to modify the synopsys library, I decided to try
a test case of creating a new xilinx library for viewlogic with
names matching those in the synopsys library. So, after generating
a new edif netlist, reading it in synopsys, synopsys complained
again that the way I was using flip-flops with a clock enable was
not allowed, and since the xilinx 4000 library only support ffs
with clock enable (yes, there's a ff without a clock enable, but
with no reset or clear) there was no way around that problem. There
were a few other gotcha's but basically no go. In other respects,
the XSI product from xilinx is useless.
Synopsys 3.0 supports now writing xnf files, but there's no support
to read xnf files. But since the libraries are incompatible,
synopsys is of no help in trying to optimize a design that has been
generated through schematics; and in any case xilinx is trying to
discourage any design path that includes synopsys, since they want
to sell their xblocks tools.
So in early January 93, we had a working 4005 but with four channels
instead of 12. From all of the xilinx parts we could only use the
4005/4006, since these were the only two devices available in a 160
pin pqfp package (boards were already build), so upgrade to 4008/
4010 was not a possibility (available in 208 pqfp).
Then our only choice to migrate to the full functionality was
to translate the design into an ASIC. We decided to use an asic
vendor that promised a smooth migration path from the xnf file into
a device with no involvement from my part. They would translate the
xnf into their own netlist format, add internal scan (partial or
full), add the boundary-scan (jtag), and deliver parts. So in early
march, we gave them an xnf file, in early april we got back an edif
netlist to read back into viewlogic for test vector verification
before sign-off. Well, well, it took me about three days to be able
to read back the netlist generated by synopsys. Reading an edif
netlist into viewlogic is a two step process: first you generate
the wir files and second you generate the schematics, it was the
schematic generation process that was not completing due to
multiple errors. I was only able to fix these errors without going
back to the vendor, because I could bring up synopsys, have it read
the netlist and check the error, and then go back and hand edit the
edif netlist, not something I want to do everyday.
So we finally had schematics, a great achievement perhaps, but
still not out of the woods. The vendor had taken our xnf netlist
and fed it through Examplar and then synopsys to generate the
netlist with their symbols. Well, the result of xnf into examplar
and synopsys out was --- GARBAGE. Inputs became outputs, two input
or gates had one input tied hi, two input and gates had one input
tied lo. Oh, there were tens of similar gems. Result: unusable.
Since we do a lot of business with this vendor we screamed a lot,
but since we did not want to waste another month or two and be a
guinea pig, we decided to do the migration ourselves.
So starting from my original viewlogic schematic, I made a list of
all the xilinx primitives used in the design, and in a day created
equivalent sheets for these symbols using the vendor's library. In
other words, I still used the xilinx symbols for lets say a three
input and gate, but if you pushed into the and gate you would see
a three input and gate with the vendor's name and timing. I basically
added a level of hierarchy.
I then ran all of my test vectors, added scan, added boundary scan
and released the device to that vendor in about three weeks of work.
In conclusion, unless you start with an HDL description of the
FPGA, migrating a design through netlists into synopsys is a very
difficult and lengthy process, prone to break your heart and create
an unknown number of bugs.
- Anonymous
( Post 124 Item 2 ) --------------------------------------------------------
>Subject: (Post 120 Item 2) "Seeking Spare Gates Methodologies"
>
>I am looking for suggestions of different methods to implement a
>spare gates methodology in VHDL source that is Synopsys compatible: i.e.
>where the 'unused' gates are not optimized out.
>
>If you have a good VHDL-Synopsys spares methodology you are particularly
>proud of, I would like to hear about it.
From: [ An Anonymous Actel User ]
I think that what you are asking is similar to a problem that I ran
into. I was using Actel FPGA's. I has several inputs that I was not
yet using internally, but needed to be preserved as inputs because the
PC board was driving the pins (and the Actel default for unused pins
is output).
I couldn't get Synopsys to leave the unconnected input buffers in the
circuit. The main problem is that it would remove them while it was
reading the VHDL, not at optimization time. Thus the normal
dont_touch attribute didn't work. I called Synopsys and this is what
they sugguested: (Note: "I14" is the input buffer in question, and had
to be specifically instantiated because I am using v2.2 (pre-FPGA
compilier.)
--------------------------------
-- pragma dc_script_begin
-- dont_touch I14
-- pragma dc_script_end
--------------------------------
But if you look in the manual it specifically states that anything
done in pragmas, such as this, is applied after the reading is complete,
in other words, too late.
A little more reading, research, and experimentation lead me to the
following code:
ATTRIBUTE DONT_TOUCH : boolean;
ATTRIBUTE DONT_TOUCH of I14 : label is true;
This has been working just fine for me.
If you are trying to instantiate gates specifically as spares this
should work, if you are trying to somehow get the code to imply extra
logic functions you may need to experiment a little further.
-- An Anonymous Actel User
-- -- -- -- -- -- -- -- --
From: d_pinvidic@emulex.com (Dan Pinvidic)
We use a seperate module comprized of misc. gates with their inputs
connected to logic_O (or 1) internally and each gate output connects to
a port of the module. This module is instantiated at the top level of
your design.
- Dan Pinvidic
Emulex Corp.
Example:
module SEW_KIT(
dum29, dum30, dum31
);
output dum29;
output dum30;
output dum31;
wire LOGIC0;
wire LOGIC1;
NOR3_1 SEW29(LOGIC0,LOGIC0,LOGIC0,dum29);
NOR3_1 SEW30(LOGIC0,LOGIC0,LOGIC0,dum30);
NOR3_1 SEW31(LOGIC0,LOGIC0,LOGIC0,dum31);
F091 SEW32(.N01(LOGIC1),.N02(LOGIC0));
endmodule
/*****************************************/
// Typical gate implementation
module NOR3_1 ( A, B, C, X );
input A, B, C;
output X;
assign X = ~(A | B | C);
endmodule
( Post 124 Networking Section ) ---------------------------------------------
Boston area EDA & ASIC Design Specialist. Buzzword compatible in: Synopsys,
Verilog, ATPG, JTAG, scan, transmission lines, high speed design, ECL, GaAs
& sheep farming. - John Cooley (508) 429-4357, e-mail: jcooley@world.std.com
Synopsys support opening in CAE of Hitachi Micro Systems. Contact Tsu-Wei
Ku, Hitachi Micro Systems, Inc. 179 E. Tasman Dr. San Jose, CA 95134.
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