( Post 122 Item 1 ) --------------------------------------------------------
From: chow@carmel.amd.com (Peter Chow)
Subject: (Post 120 Item 5) FPGA Licensing and Scripts Bombing
The following is another script that you can have monitor the license:
amd_list_get_license = 0 > /dev/null
get_license HDL-Compiler
while (dc_shell_status != 1) {
if (amd_list_get_license == 0) {
sh echo "Getting HDL-Compiler license ..."
amd_list_get_license = 1 > /dev/null
}
get_license HDL-Compiler > /dev/null
}
read -f verilog design.v
remove_license HDL-Compiler
- Peter Chow, High Speed Network, Network Product Division,
Advanced Micro Devices Inc.
( Post 122 Item 2 ) --------------------------------------------------------
From: [ An Anonymous Synopsys User ]
Subject: (Post 121 Item 1) "A Solution to the Queuing Problem"
>It's a shame that Synopsys doesn't support some sort of "try to get this
>license, if fail, wait, try again" construct in dc_shell; though I expect
>they have a business interest in not supplying users with this handy feature
They do! It's the get_license command. The following simple dc_shell
script will loop until the FPGA-Compiler license has been acquired.
acquired = 0
while (acquired == 0) {
get_license FPGA-Compiler
if (dc_shell_status == 1) {
acquired = 1
}else{
sleep 30
}
}
Note: however that this only works for version 3.0. Previous versions
had a bug in the way that the get_license command set the dc_shell_status.
( Post 122 Item 3 ) --------------------------------------------------------
From: vlsisj!mrslate!ravi@uucp-gw-2.pa.dec.com (Ravi Donthi x5204)
Subject: (Post 117 Item 3) "Back annotation from Synopsys to Verilog"
Hi John,
This solution is for problem Item-3 in Post-117 from an anonymous user.
First, here's the original problem:
>I'd like to know if there are people out there have ever tried to generate
>the pre-layout SDF file from Synopsys 3.0a and then back annotate to the
>Verilog environment.
>
>According to my understanding, this can be done with the following steps:
>
>1. in Synopsys: write_timing -format sdf -output xxx.sdf -context verilog
>
>2. in Verilog: add the following lines to the system simulation level of the
> verilog source code:
>
> initial begin
> $timeformat(-9, 2, " ns", 20);
> $sdf_annotate("xxx.sdf", system,,, "MAXIMUM", "1.0:1.0:1.0", "FROM_MTM");
> end
>
>However, the verilog annotator failed to finish the annotation. I'm pretty
>sure that I used the correct scope because otherwise the annotator would
>complain about instance not found.
>
>Here's what I get from the run:
>
> Configuring for back-annotation...
>
> Reading SDF file and back-annotating timing data...
>
> WARNING - Hierarchy divider in SDF is being mapped to `.'
> SDFA ERROR - error annotating to MIPD
> SDFA ERROR - error encountered during timing annotation of instance top
> SDFA ERROR - error encountered during timing annotation - back-annotation
> terminated
Here I think the problem is not Synopsys, but Verilog. For back-annotating
MIPD (Module input port delays), the port receiving the delay has to be port
of a verilog primitive cell (for ex: buf, bufif0, and, nand etc...). Refer to
chapter 26-2 of Verilog reference manual for a list of these primitives.
Looks like in your case the cell description has some kind of behavioural
statment like "always@(...,port_name,...)" which gets accelerated during
simulation/compilation in verilog and is not backannotatable. To get a quick
fix for the cell you can do the following:
module xyz ( a, b , c, d ....);
input a, b ;
output c, d ;
buf ( a_buf, a);
always@ (a_buf)
.....
The idea is to use the name of the buffered port ( a_buf ) during the
entire description of the cell instead of port_name( a).
- Ravi Donthi, VLSI Tech. Inc. San Jose.
( Post 122 Item 4 ) --------------------------------------------------------
From: dilip@sv.gpsemi.com (Dilip Kumar)
Subject: Large plot (C, D or E size)
John:
I am looking for plotting large synthesized schematic from Synopsys.
Has anyone in ESNUG plotted a large design on a C, D or E size sheet?
If yes, what kind of plotter/software did the user use? Any attempt to
plot on a large hpgl plotter? Any utility to do so?
- Dilip Kumar
GEC Plessey Semiconductors
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