Editor's Note: This post consists primarily of users asking other users
for their experiences on specific topics. For those who to reply to
these requests, I'd like to ask you to "cc:jcooley@world.std.com" so this
info can be shared with other ESNUG readers. As always, I'll honor any
request for anonymity. Thank you for your time & effort. - John
( Post 120 Item 1 ) --------------------------------------------------------
From: [ A Design_Compiler User ]
Subject: Rev. 2.2 Design_Compiler Needs To Gobble Gates
Hi John. I have a problem with Design Compiler and I'd like to solicit
help from the ESNUG members. Please don't use my company name or my name.
I have had a problem getting Design Compiler to make a simple improvement
in a design when compiling. In our library there are many driver sizes and
the problem is that Design_Compiler will not replace a small drive "AND"
gate/Large buffer combination (for example) with a larger driver "AND" gate
without the extra buffer.
What Design Compiler does:
and3a0 buf1a1 (area = 11.5, delay = 1.0)
+----\
---|A \ |\
---|B Y|-----| >--- 4.2 std loads (gate) + 10 sl's (wire) = 14.2 sl
---|C / |/
+----/
What I want Design Compiler to do:
and3a1 (area = 8.5, delay = 0.7)
+----\
---|A \
---|B Y|----------- 4.2 std loads (gate) + 10 sl's (wire) = 14.2 sl
---|C /
+----/
1. There are no other fanouts on the output of the and3a0.
2. I'm using Synopsys v2.2b.
3. No timing constraints are placed on the design.
4. max_area 0 is set.
5. The and3a1 gate is smaller (26%) and faster (at least 23%).
6. The and3a1 gate meets all design rule constraints, including max_fanout.
7. This case happens when compiling a design mapped (with translate) from
another library to ours or when compiling to our library from Verilog HDL.
8. If the design is small enough (less than 100 gates), Design_Compiler does
make the preferred change. If the design is larger (greater than an amount
that is not clearly understood), Design_Compiler never makes the change.
9. I have tried all sorts of variation of options (effort, incremental
mapping, iterative compilation,...) without any luck.
10.Synopsys people concede that this is a problem and they were of little help.
Any suggestions?
1. Any hints on things to try in Design Compiler?
2. Has anyone experienced the same problem and simply written a gate gobbler
to deal with it?
3. Should I go through the pain of loading 3.0 (and converting the libraries)
to see if it works better?
- A Design_Compiler User
( Post 120 Item 2 ) --------------------------------------------------------
From: bezzant@cirrus.com (Dan Bezzant)
Subject: Seeking Spare Gates Methodologies
I am looking for suggestions of different methods to implement a
spare gates methodology in VHDL source that is Synopsys compatible: i.e.
where the 'unused' gates are not optimized out.
If you have a good VHDL-Synopsys spares methodology you are particularly
proud of, I would like to hear about it.
- Dan Bezzant
Cirrus Logic
( Post 120 Item 3 ) --------------------------------------------------------
From: c0695@marsha.sanders.lockheed.com (Mark J. Halberstein)
Subject: (Post 115 Item 3) "Can't Get Synopsys to Use Wider Gates
> We are trying to implement a synthesized look-up table, but the results from
> Synopsys contain an extremely high percentage of 2-input gates. Our vendor
> has found this to be unroutable. Is there a way to force Synopsys to use
> wide input gates (a PLA-like structure) without a 'don't use' on the 2-input
> gates?
After reading post 116, this may be beating a dead horse, but anyway...
Strictly speaking, the reason that Synopsys chooses 2 input gates rather
than wider gates for speed optimization is that they are theoretically
the optimum mapping of a function. The problem is that in the real world,
chips have to be laid out, and it turns out that today's layout tools,
working with today's channel-free architectures, have a problem with the
theoretically optimum logic mapping due to the large number of wires
produced. Of course, using wider gates would produce fewer wires,
although the number of logical layers may not be reduced, since (for
example) an 8 input nand cell would be built as 2 4 input nands, followed
by a 2 input nor, followed by a big inverter.
Solution: optimization process must be aware of real-life layout issues
in order to truly optimize a circuit. Synopsys is aware of this, and is
working with LSI Logic to merge layout and synthesis together somehow.
- Mark J. Halberstein
Nebula Corp.
[ Editor's Note: You may wish to read "Logic Synthesis Links With
Layout" in the April 5, 1993 issue of EE Times (pgs. 37-40) for a
detailed look at how Synopsys and some of its competitors are
trying to tackle the layout/synthesis problem. - John ]
( Post 120 Item 4 ) --------------------------------------------------------
From: cindy@zoran.hellnet.org (Cindy Eisner)
Subject: Seeking Altera & Synopsys Stories
1. does anyone have any experience with using synopsys for ALTERA fpga's?
2. anyone who has done an fpga of ANY kind with synopsys:
in retrospect, do think this was the way to go? or, more diplomatically:
if you had to do it all over, would you do it this way again?
what was the main advantage in using synopsys over the fpga vendor's
synthesis? was it just the advantage of using verilog or vhdl instead
of a separate language? if the vendor's synthesis system could read
verilog or vhdl at the rt-level, would you still use synopsys?
thanks,
- Cindy Eisner, Zoran
( Post 120 Item 5 ) --------------------------------------------------------
From: Lauren Baker <baker@ctron.com>
Subject: FPGA Licensing and Scripts Bombing
Is there any easy way to submit script jobs once licenses are free?
Basically we have 4 users fighting over 2 licenses and it would be
nice to have the job that gets refused to keep trying if it couldn't
get the licence when it tried for it. In particular, we are fighting
over FPGA licenses, so there is the added condition that initially
invoking dc_shell grabs a design_compiler license, which we don't want,
and then the script blows up since it may not be able to get a FPGA
license.
Does anyone have a script that monitors the licenses and then jumps
in and tries? Or is there a better way?
Thanks for any help.
- Lauren Baker, Ctron
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