SPRING CLEANING is coming to ESNUG! What this means is that if the ESNUG
post I'm sending you today is bounced back by your local mailer, I'm
deleting your name from the mailing list. The way to figure out if
you've been deleted is to ask yourself at the end of Thursday (tommorrow):
"Did I get ESNUG post 120?" -- if not, you'd better write me with your
correct e-mail address!
- John Cooley
ESNUG Moderator
( Post 119 Item 1 ) --------------------------------------------------------
Subject: Response to Part of Post 118
>Subject: (Post 117 Item 2) "Can't Have a Library Cell with Pin Name 'NS'"
>
>In the user's reported problem, his VHDL design uses "NS" as a pin name
>and that is a VHDL reserved word used to define time. You can verify this
>by looking in the VHDL LRM (1987) on pages 3-6 and 14-10.
- - - - - - - - - -
From: "Mark A. Hilmantel" <hilmantl@rapnet.sanders.lockheed.com>
NS is NOT a reserved word in VHDL. Pages 3-6 and 14-10 have nothing to
do with reserved words. The list of reserved words is on page 13-8 of
the LRM. NS is an identifier declared in the predefined package
STANDARD and is no different from any user-defined identifier.
The scope and visibility rules (LRM chapter 10) allow an identifier to
be declared more than once, and specify how such homographs may be
resolved. In particular, the last paragraph on page 10-4 seems to
indicate that within the immediate scope of a declaration of a port
named NS, that declaration should hide the direct visibility of the
physical unit NS declared in package STANDARD. Within their respective
scopes, the different declarations can be made visible by selection.
- Mark Hilmantel, Lockheed Sanders, Inc.
- - - - - - - - - -
From: [ "An Anonymous Language Lawyer" ]
>In the user's reported problem, his VHDL design uses "NS" as a pin name and
>that is a VHDL reserved word used to define time. You can verify this by
>looking in the VHDL LRM (1987) on pages 3-6 and 14-10.
yes NS is declared in VHDL as a unit of time, but it is not a reserved word,
these are listed on page 13-8 of the LRM. It is perfectly legal within VHDL to
name a port,signal,variable,constant (etc.) NS (thus hiding the definition of
that unit of time).
>Unfortunately VHDL Compiler did not flag that it has encountered a VHDL
>conflicting name during the read of the user's design. NOTE: Design Compiler/
>VHDL Compiler will not write out cell/pin names that conflict with the VHDL
>standard.
The error was not in the VHDL Compiler, perhaps some other tool depends upon
the declaration of NS not being hidden?
- an Anonymous Language Lawyer
( Post 119 Item 2 ) --------------------------------------------------------
From : Kevin Chung, Synopsys Inc. (kchung@synopsys.com)
Subject: V3.0a "read -f vhdl" Fatal : Internal system errors
The Synopsys Hotline has seen a couple of fatals involving "read -f vhdl".
If you are a site that is licensed for VHDL Compiler and VHDL System
Simulator AND the both synthesis and simulation tools have been loaded on
top of each other (both tool sets installed in the same directory tree),
PLEASE read on.
In some calls to the Synopsys Hotline, Fatal Internal System errors that
ocurred right after "read -f vhdl" have been reported which were caused by
a bad error message in the "dc.err" file. This file contains the error
messages used by various Synopsys tools.
The error code for "HDL-178" in the "dc.err" file should read:
"The variable in the sensitivity list %d will be ignored."
NOT:
"The variable in the sensitivity list %s will be ignored."
This problem is caused when the simulation tape is loaded on top of the
synthesis tape. This problem, STAR 11087, has been fixed in v3.0b.
Please post any questions on this particular issue back on ESNUG and
I'll respond in the same manner.
- Kevin Chung, Synopsys, Inc.
( Post 119 Item 3 ) --------------------------------------------------------
From: sgolson@trilobyte.com (Steve Golson)
Subject: Useful script for Synopsys 3.0
Synopsys 3.0 has new commands that allow you to edit the netlist of a design
loaded into Design Compiler. These commands include create_cell, create_port,
create_net, and connect_net.
Here is a script that uses these commands to create a new design containing
one of each type of cell in a given library. Read your library into memory
and then include this script. The new design is called "allcells".
/*
** allcells.ss
**
** This script creates a new design containing one cell of each type
** in a given library. This is useful for testing new libraries.
*/
/* change this to whatever library you want */
thelib = "class"
/* create a new design */
remove_design allcells
create_design allcells
current_design = allcells
/* initialize the port names and instance names */
portnum = 0
unum = 0
/* find all the cells in the library */
foreach(cell, find(lib_cell, thelib + "/*")) {
/* instance name */
instance_name = U + unum
unum = unum + 1
/* create a cell in the current design */
create_cell instance_name cell
/* find all the pins on the library cell */
foreach(thepin, find(lib_pin, cell + "/*")) {
port_name = "p_" + portnum
net_name = "net" + portnum
portnum = portnum + 1
pin_name = cell + "/" + thepin
/* find the direction of the pin */
dirlist = get_attribute(pin_name, pin_direction)
/* convert the direction from a list to a value */
if (dirlist == {in}) {
direction = "in"
} else if (dirlist == {out}) {
direction = "out"
} else {
direction = "inout"
}
instance_pin = instance_name + "/" + thepin
/* create a port in the current design */
create_port port_name -dir direction
/* and a net */
create_net net_name
/* now wire up the port and the pin */
connect_net net_name { instance_pin port_name }
}
}
/* end of script allcells.ss */
- Steve Golson, Trilobyte Systems
( Post 119 Networking Section) ---------------------------------------------
AMD Sunnyvale, CA., MTS Design Engr with min 5 yrs exp. in VLSI DFT, HDL based
design (Synopsys/Verilog). FAX: (408)235-8636 or E-mail: judith.onton@amd.com
|
|
