I'm happy to see that we're now beginning to see direct response to some
of the problems we're seeing on ESNUG. Please, if you have a reply to
a particular issue that a Synopsys employee is responding to on ESNUG,
PLEASE send that response to ESNUG! (The developers at Synopsys don't
have the time to deal with a flood of individual e-mails -- but they are
interested in occassionaly responding customers on ESNUG because it helps
hundreds of us at the same time.)
- John Cooley
ESNUG Moderator
( Post 118 Item 1 ) --------------------------------------------------------
From: Kevin Chung, Synopsys Inc. (kchung@synopsys.com)
Subject: (Post 117 Item 2) "Can't Have a Library Cell with Pin Name 'NS'"
This in regards to a problem as user was having with reserved words in
Library Compiler. I have broken up this "application note" into two parts:
1) How to use reserved words in Library Compiler.
2) More details on the user's problem.
- - - - - - - - - - - - -
Part 1: Using Reserved Words as Pin or Cell names in Library Compiler
I tried an experiment here with v3.0a and the problem that was reported
with Library Compiler and reserved words. While I don't have a list
of reserved words for Library Compiler, I have seen this problem before and
there is a workaround.
NOTE: Library Compiler is more tolerant of "Library Compiler" keywords as pin
or cell names in v3.0 than earlier releases, It is "smarter" than Library
Compiler from a couple years ago due to an enhancment to make it more "context
sensitive". In my tests to try to get Library Compiler to fail on a Library
Compiler keyword, I was not able to get it to do so. You can use the workaround
below if you do run into a keyword problem in Library Compiler.
Here is the workaround:
Create the library cell as usual, but in those cases where you are using
a reserved word as a pin or cell name, put double quotes around the name.
You only need to do this when you are declaring the pin or cell names, NOT in
the function descriptions on the output pins.
Here is an example library. Assume that the word 'RESERVED' is a keyword that
Library Compiler will not allow you to use as a cell or pin name.
Library :
library(EXAMPLE) {
cell(AN2) {
area : 2;
pin("RESERVED") {
direction : input;
capacitance : 1;
}
pin(B) {
direction : input;
capacitance : 1;
}
pin(Z) {
direction : output;
function : "RESERVED B";
timing() {
intrinsic_rise : 0.48;
intrinsic_fall : 0.77;
rise_resistance : 0.1443;
fall_resistance : 0.0523;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "RESERVED";
}
timing() {
intrinsic_rise : 0.48;
intrinsic_fall : 0.77;
rise_resistance : 0.1443;
fall_resistance : 0.0523;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "B";
}
}
}
}
- - - - - - - - - - - - -
Problem #2: User's problem with a Pin named NS
The problem that was reported by a user in ESNUG Post 117 was reported as a
problem in Library Compiler regarding pins on cells which were named NS.
The user had reported this problem to the Synopsys Hotline and I looked at the
testcase he had sent.
It turns out that Library Compiler and Design Compiler have no problem with
pins on cells named "NS". What the user did not say was that he was reading
in a VHDL design that was referencing that cell.
Error: Can't find input port 'NS' on reference to 'FOO' in 'test'. (LINK-1)
This message above could mean one of the following has occured during
a "link" command:
1) The cell description in the library and cell and the design has differently
named pins -- this could be due to spelling OR case (Design Compiler is case
sensitive).
2) Design Compiler was not able to resolve the pin name because the design
uses a language dependent keyword.
In the user's reported problem, his VHDL design uses "NS" as a pin name and
that is a VHDL reserved word used to define time. You can verify this by
looking in the VHDL LRM (1987) on pages 3-6 and 14-10.
Unfortunately VHDL Compiler did not flag that it has encountered a VHDL
conflicting name during the read of the user's design. NOTE: Design Compiler/
VHDL Compiler will not write out cell/pin names that conflict with the VHDL
standard.
To see this, a Verilog design and the same design written out as
a VHDL netlist is given below. Note that the pin "NS" in the Verilog design
has been renamed to "NSb" to conform with the VHDL standard. Design Compiler
and VHDL Compiler have been set up to automatically realize that NSb is
actually "NS" after the read.
[my.v Verilog Example]
module my(k,l,x) ;
input k,l ;
output x ;
FOO U1(.NS(k),.A(l),.Q(x));
endmodule
[my.vhd VHDL Example]
library IEEE;
use IEEE.std_logic_1164.all;
entity my is
port( k, l : in std_logic; x : out std_logic);
end my;
architecture SYN_verilog of my is
component FOO
port( A, NSb : in std_logic; Q : out std_logic);
end component;
begin
U1 : FOO port map( A => l, NSb => k, Q => x);
end SYN_verilog;
The solution that I would suggest to avoid the problem in reading in VHDL
designs that use cells with VHDL reserved words would be for the library
supplier/developer to consider changing their cell naming convention to be
VHDL compliant. A possibel workaround would be to change the library and
designs to be VHDL compliant and write a script or program to change the names
to the original non-compliant names when going to the other user tools.
If you have any questions regarding information in this ESNUG Post,
please post to ESNUG and I'll try my best to respond.
-Kevin Chung, Synopsys, Inc.
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