Sorry for being off line for a full week; I was at OVI and SNUG. I'll do
a write-up of what went on in later posts. It was nice to finally meet some
of the people I've been exchanging e-mailing with for over a year now!
- John Cooley
ESNUG Moderator
( Post 116 Item 1 ) --------------------------------------------------------
Subject: (Post 115 Item 3) "Can't Get Synopsys to Use Wider Gates
> From: knight@acuson.com (Jon Knight)
>
> We are trying to implement a synthesized look-up table, but the results from
> Synopsys contain an extremely high percentage of 2-input gates. Our vendor
> has found this to be unroutable. Is there a way to force Synopsys to use
> wide input gates (a PLA-like structure) without a 'don't use' on the 2-input
> gates?
- - - - - - - - - - - - -
From: gboyer@comanche.ess.harris.com (Glenn Boyer)
I have been experiencing the same problem with synopsys. I have been trying to
create a 2 to 3 level address decoder. Synopsys seems to like 5 to 6 levels.
I have found that the flatten option does create a 2 level AND-OR logic
equation. (This was done by compiling with -no_map and writing the new
equations out in VHDL). However, it seems that when Synopsys tries to map
it to gates that it begins to make poor choices. The best luck that I had
was by restricting the gates down to AND, OR, NOR and NAND. This is how
I got it to 5 to 6 levels.
Using 8 input gates an extremely large equation could be mapped with two
levels of AND's and two levels of OR's. I would also like to know why
synopsys cannot come to such a simple conclusion.
Glenn Boyer, Palm Bay
- - - - - - - - - - - - -
From: cindy@zoran.hellnet.org (Cindy Eisner)
jon, look at the synopsys library for the solution. if synopsys is using lots
of two-input gates, maybe the timing for these gates is better, or the area is
smaller. to convince synopsys that less gates is better, make sure you are
using a severe wire-load model. since less gates is usually less wire,
you can use a severe wire-load model to tell synopsys that wire is
expensive both in timing (capacitance) and area.
Cindy Eisner
Zoran Microelectronics LTD
- - - - - - - - - - - - -
From: brad@hdls.COM (Brad Eltman)
This problem is in the way that your source verilog or vhdl is structured.
We have been working with this problem for years, in fact were the first to
point it out to Synopsys in V1.0alpha.
What we do is to specify wide operators in the source, this steers the
mapping and MIS II to wider gates before optimization. Once wide gates are
used the cost function will see that they are better, however once these
wide gates are decomposed the cost function has no rules it can see to put
them back together.
To generate wide gates in verilog is easy, use reduction operators over large
pieces of the vector. This will map to wide gates straight away.
Brad Eltman
HDL Systems
( Post 116 Item 2 ) --------------------------------------------------------
From: [ Someone at SNUG ]
Subject: Getting Synch Resets Working Correctly v3.0a-10052 Addendum #7
John,
Good meeting you at SNUG. You said you hadn't heard about this one, so I'm
posting. Some of our engineers took the Synopsys 3.0 update course, and
learned this. About a week later, Synopsys sent out a document called
"v3.0a and v3.0a-10052 Synthesis Release Note Addendum #7"
It says to get synch resets working correctly, add BOTH:
"compile_preserve_sync_resets = true"
"sync_reset_no_tie_offs = 1" // that's a 'one', not an 'L'!
The same release note identifies a bug that occurs if all 3 of the
following are true:
1) design is in Verilog
2) a single "read" command loads multiple modules of a design
(in one or more files).
3) A module in the design, other than the first read in, contains
an addition operator with a constant operand. The constant
must be even, and have a different bit width than the other
operand.
I'd rather you didn't use my name, company, etc...
( Post 116 Item 3 ) --------------------------------------------------------
From: ronny@zycad.com (Ron Karpel)
Subject: VHDL Code That Causes Synopsys Analyzer To Core Dump
I don't know if you take VSS bug as well as synthesis. But if you do,
this one may save people some time.
The following VHDL code causes the analyzer to dump core. There is an
error in one of the assignments, but it should not cause a core dump.
VHDL CODE
------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- only to use arithmetic Functions like +, -
use ieee.std_logic_unsigned.all; -- for conversion to integers if you need
entity pifDataPath is
port(
RdAddrSelH : in std_logic
);
end pifDataPath;
architecture behavior of pifDataPatH is
subtype PROCIF_ADDRESS_BUS_RANGE is integer range 28 downto 2;
subtype Lo_Address_Bus_Range is integer range 23 downto 0;
subtype Hi_Address_Bus_Range is integer range 26 downto 24;
signal BufAddr : std_logic_vector(PROCIF_ADDRESS_BUS_RANGE);
signal WbAddrLatch : std_logic_vector(Lo_Address_BUS_RANGE);
signal RbAddrLatch : std_logic_vector(Lo_Address_BUS_RANGE);
signal HiAddrLatch : std_logic_vector(Hi_Address_Bus_Range);
begin
-- Address Select between read and write buffers
BufAddr(Hi_Address_Bus_Range) <= HiAddrLatch;
-- next line has an error
BufAddr(Lo_Address_Bus_Range) <= RbAddrLatch when RdAddrSelH='1' else
WbAddrLatch;
end behavior;
Ron Karpel
Zycad
( Post 116 Networking Section ) ---------------------------------------------
VHDL Technology Group (Bethlehem, PA): (a) Sr. Prjct Leader: Architect, Desgn
& Build next generation synthesis related CAE tools. 5+ yrs exper. (b) Engr:
Develop VHDL simulation and synthesis models. email: "vhdl!wdb@uunet.uu.net"
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