Sorry that I've been out of touch lately -- I have been spending quite some
time getting ready for the "Bankruptcy" tutorial at the OVI conference and
lambing season. I've been hearing a lot of stories from you guys!
Many thanks to the people at Intellitech who have now come up with a way
where you can get back ESNUG posts via e-mail. I personally like this
because it takes a "Could you resend me post XXX" load off of me. Thanks!
- John Cooley
ESNUG Moderator
( Post 113 Item 1 ) --------------------------------------------------------
Subject: Retrieving ESNUG Archives For E-mail People
From: khaddock@intellitech.com (Kareen Haddock)
Hi John,
This is the procedure for retrieving ESNUG archives via internet:
via internet e-mail send to "khaddock@intellitech.com" the following
(there will still be call back verification as with the BBS):
NAME:
COMPANY NAME:
ADDRESS 1:
ADDRESS 2:
ADDRESS 3:
CITY, STATE, ZIP:
BUS. PH:
BUS. FX:
EMAIL ADDRESS:
ESNUG POSTS:
example,
NAME: Christopher J. Clark
COMPANY NAME: Intellitech Corp.
ADDRESS 1: 66 Route 25
ADDRESS 2:
ADDRESS 3:
CITY, STATE, ZIP: Meredith, NH 03253
BUS. PH: 603-279-6308
BUS. FX: 603-279-5135
EMAIL ADDRESS: cjclark@intellitech.com
ESNUG POSTS: 59,65-75
I will send the posts as one large text file that you can cut
into seperate posts if you wish.
Sorry about all the info needed, but we still have been requested to
perform call back verification which we'll do via phone or fax. Please
only send your requests to khaddock@intellitech.com
(not cjclark@intellitech.com)
- Kareen Haddock
Intellitech Corporation
Current list of posts, John, please send posts 40-54 and 56
ESNUG.55 Re: Post 52 Item 2
ESNUG.56
ESNUG.57 problem optimizing of floating inputs (Post 52 item 1)
ESNUG.58 signals which do not always have known values,Cadence to Synopsys Interface
ESNUG.59 Re: Post 56 Item 1 Topic 4-Unknown propagation
ESNUG.60 Re: Post 59 Item 1
ESNUG.61 missing posts
ESNUG.62 Re: Post 58 Item 1
ESNUG.63 Re: Post 62 Item 1
ESNUG.64 Re: Post 62 Item 1 & Post 63 Item 2
ESNUG.65 fray regarding synopsys and unknowns
ESNUG.66 Mentor workstation,Continuing the fray about Synopsys and unknowns
ESNUG.67 Re: Post 65,Re: Post 66 Item 2,Employment network survey
ESNUG.68 flat timing report
ESNUG.69 mux-model,x-handling,Re: post 68 timing reports,Networking Section Survey Results
ESNUG.70 Re: Post 67 Item 2,Networking Section
ESNUG.71 unknowns feeding into state machines,Cadnece's Composer schematic capture,Synopsys schematic capture
ESNUG.72 Re: Post 71 Item 1,Re: Post 71 Item 2
ESNUG.73 VHDL records w/ more than 2 levels and arrays,Networking Section
ESNUG.74 duplicate timing arcs in 3.0 beta1 Library Compiler
ESNUG.75 Re: Post 64,Question for ESNUG group
ESNUG.76 mapping flip-flops
ESNUG.77 Re: Post 75 Item 2,Re: Post 76 Item 1
ESNUG.78 muxes (Post 75 Item 2),paranthesis bug,Posting 65 (Synopsys use of unknowns and inverse pairs)
ESNUG.79 Synopsys accepting Illegal VHDL Constructs,Re: Post 78 Item 3
ESNUG.80 Synopsys & Vantage's VHDL Incompatabilities
ESNUG.81 A Better VHDL Random Number Generator,memory space
ESNUG.82 Open Verilog International's Call for Papers,RE: Synopsys does not understand invalid gate input states
ESNUG.83 Scan & Motorola's CMOS H4C Synopsys Library & a Bug!
ESNUG.84 Net Shorts in Synopsys EDIF Outputs
ESNUG.85 paranthesis bug (Post 78 Item 2),vhdl_strict variable (Post 81 Item 2)
ESNUG.86 synopsys tri-state bug,DC 2.2b Case sensitivity in records
ESNUG.87 Non-informative Timing Reports Through Hierarchy,Networking Section
ESNUG.88 problem optimizing of floating inputs (Post 57 Item 1)
ESNUG.89 Outputs not used for internal feedback
ESNUG.90 Re: Post 89 Item 1,Synopsys' Poor Choice of Asynchronously set/reset Flip-Flops,Networking Section
ESNUG.91 How "characterize" Command Really Works
ESNUG.92 Post 92 "group" command trouble, Sum of products case statement
ESNUG.93 More Sum of Products, Mixing Cadence & Synopsys along with routing
ESNUG.94 More Mixing Cadence & Synopsys along with routing
ESNUG.95 How To Use A User-Defined Library, Not All Fanouts Are The Same!
ESNUG.96 Timing Arcs & Timing Reports, User-Defined Library
ESNUG.97 Simulation/Synthesis Differing, HPGL Output, Synopsys to GDT
ESNUG.98 Post 98 Confusion On What Does What In Compiling
ESNUG.99 Post 99 Synopsys VHDL & Actel FPGAs (Part 2 of 2)
ESNUG.100 Synopsys VHDL & Actel FPGAs (Part 1 of 2)
ESNUG.101 Synopsys & Actel FPGA Project Paper
ESNUG.102 Edif fix awk script
ESNUG.103 3.0a library compiler chokes depending on whitespace
ESNUG.104 Backspace/Delete Keys Problem with 3.0a on SUN Workstations
ESNUG.105 Synopsys Follow-Up on Post 103, plotting, partitioning
ESNUG.106 Edifout variables for direct Synopsys to Cadat interface
ESNUG.107 Compile/characterize, Postscript Plotting, synchronous resets
ESNUG.108 Plotting ? P105, Synchronous reset, Inferring Muxed-D Flip-Flops
ESNUG.109 More Synchronous Reset Issues
ESNUG.110 More Synch Reset, more Inferring Muxed-D Flip-Flops
ESNUG.111 Latches & Clocked State Machines,FPGA compiler,Math library,Verilog Test Compiler Controlling Bi-Directs Question
ESNUG.112 Retrieving Archives & Access For Non E-mail People,ESNUG 111 Item #2,Using XVision & Synopsys
( Post 113 Item 2 ) --------------------------------------------------------
From: "Bradshaw, Lee" <LBradshaw@engineer.clemsonsc.NCR.COM>
Subject: Post 112 "Anyone Using XVision?"
> This behavior is very sporadic and not reproducible.
>
> My question: "Is anyone else using XVision along with Synopsys?"
>
> By the way, we are using Novell LAN WorkPlace for DOS (ver 3.5 & 4.0)
>
> Frank Malloy
> Tredyffrin, PA
It took us several months to find a system (network and X server) that was
stable on the PC. We tried Novell LAN WorkPlace for DOS, Beame & Whiteside,
Wollongong Pathway, FTP, XVision, and XAge in many combinations before
finding a system that was really stable (didn't crash the PC) and didn't
drop X windows.
We are currently using Chameleon NFS from Netmanage (408) 973-7171 and
eXceed-W from Hummingbird Communications (416) 470-1203. These programs are
great. They are very stable and FAST.
We are using several types of NCR PC's with Super VGA (1024 x 768 x 256
colors) or NCR graphics boards(1280 x 1024 x 256colors) as X-servers. 3Com
3C523 EtherLink/MC ethernet boards provide our network connections.
IPX/link from Netmanage lets us run Novell Netware and TCP/IP within
Windows.
The only known problem occurs when using the MultiLan driver from Chameleon.
Sometimes new applications will not start (report out of memory) even when
there are plenty of system resources and memory. This problem was supposed
to be fixed in the latest version, but it is still there. There are several
ways to work around the problem. Send e-mail if you have any questions.
lee.bradshaw@clemsonsc.ncr.com
chris.raeuber@clemsonsc.ncr.com
( Post 113 Item 3 ) --------------------------------------------------------
From: [ Let's Spare Someone Else The Pain ]
Subject: Synopsys Crash and Bug List
John-
Please don't use my name or company, but we've compiled a list of
Synopsys 3.0 VHDL design compiler bugs that have hit us. Hopefully
we can spare someone else more pain and agony. :^)
1. Using slices or bits of vectors in process sensitivty lists.
example:
process (a, b, c(0)) -- the c(0) will crash design_compiler
-- or design_analyzer.
Workaround: infer a new name for c(0).
example:
c_temp_0 <= c(0);
process (a, b, c_temp_0)
2. Using more than 1 latch enable to infer a latch.
example:
process(reset, data, g1, g2)
begin
if(reset='1') then
q <= '0'
elsif (g1='1' and g2='1') then -- will crash on this
q <= data ;
end if;
end process;
Instead, use the following:
g3 <= g1 and g2;
process (reset, data, g1, g2)
begin
if (reset='1') then
q <= '0';
elsif (g3='1') then
q <= data;
end if;
end process;
3. Using unconstrained ports to entities
example:
entity E is
port ( a : in std_logic_vector, -- will crash on this
b : in std_logic,
4. Synopsys bug: When you use the Synopsys packages STD_LOGIC_UNSIGNED or
STD_LOGIC_SIGNED and within the same file you also have a vectore
comparison that uses a slice of a vector. Already reported to Synopsys;
this does not crash but complains with a type mismatch error.
example:
...
use ieee.std_logic_unsigned.all;
...
...
if (a(3 downto 0) = "1111") then -- a type mismatch occurs
-- with the "=" operator
...
If you create a new variable "b" that is the length of the
vector slice and assign "a" to it and then use "b" in the
vector comparison the code will work.
use ieee.std_logic_unsigned.all;
...
signal b : std_logic_vector(3 downto 0) ;
...
b <= a(3 downto 0) ;
...
if (b = "1111") then -- this will work
5. When using component with generic map you must either map all generics
(in instantiation) or none (use all default values). If you try to generic
map only some of the values the Design Compiler will suicide.
6. If you create_clock with a very large period using the dialog box in Design
Analyzer the tool will write a create_clock command using scientific
notation for the -period (i.e. "1e+06"). The Design Compiler is not able to
parse this, and will return the error:
"can't find object 'e+06' in design" ...
( Post 113 Item 4 ) --------------------------------------------------------
From: johns@emavp22.webo.dg.com (John Spillane)
Subject: Seeking Queuing Software
John - I am looking for some publicly available queuing software
for running many Synopsys jobs in sequence, so I don't have to
pay THEM more money. Does anyone in ESNUG have any utilities, or
even just names of utilities??
John Spillane
Data General Corp.
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