A Special thanks goes to CJ Clark for creating this secure archive
site plus "access for non E-mail people" site for ESNUG! (I wanted
to have a secure archive site because my intention with ESNUG is to
NOT have this information going straight to Synopsys competitors.
It just doesn't sit well with me ethically having ESNUG go to an
e-mail address like, say, "joe@cadence.com"...) Anyway, thanks for
your help CJ!
- John Cooley
ESNUG Founder & Moderator
( Post 112 Item 1 ) ---------------------------------------------------------
Subject: Retrieving ESNUG Archives & ESNUG Access For Non E-mail People
From: cjclark@intellitech.com (cjclark)
Hi John,
This is the procedure for retrieving ESNUG archives:
Using some type of communications software (Procomm, Qmodem, etc) dial
the Intellitech BBS at 603-279-4177 (supports 14000-1200 baud, v.32,
v.32bis,v.42, v.42bis). Login in as NEW (for new user). New users must
answer the questionaire provided for validation. (For security reasons,
to avoid kooks, etc. all users are call-back validated.) ESNUG users
should state the reason for access as "ESNUG". Once validated a ESNUG
user can call back and access both the FILES area and the MAIL area.
Help is supplied on the board at any time by entering "?".
The files area is accessed by typing "FILES". This will bring the user
to the default area which is the /PUBLIC area. To Enter the SYNOPSYS
area, type a "L" for "Log to New Area", and type "/synopsys". You will
then be prompted for the password (currently "!4KDENCE"). Once in the
directory a listing may be obtained by typing "D" for "directory" and then
*.* for instance. A file may be downloaded (via ZMODEM, XMODEM, YMODEM,
and KERMIT) by using the "SEND" command. You must then start your
receive communications protocol on your local machine.
Users that don't have Internet access may join/participate in ESNUG
by accessing the MAIL area. To send quesitons to ESNUG, type MAIL
to enter the E-MAIL area. Then type "SEND" and enter john's address
as "jcooley@world.std.com". Users will be limited at this time to just
sending internet mail to ESNUG, although, exceptions probably could
be made if you had some other legitimate purpose and made a request.
Until we get the past posts before 92 this is the current listing for
the synopsys area:
ESNUG.92 Post 92 "group" command trouble, Sum of products case statement
ESNUG.93 More Sum of Products, Mixing Cadence & Synopsys along with routing
ESNUG.94 More Mixing Cadence & Synopsys along with routing
ESNUG.95 How To Use A User-Defined Library, Not All Fanouts Are The Same!
ESNUG.96 Timing Arcs & Timing Reports, User-Defined Library
ESNUG.97 Simulation/Synthesis Differing, HPGL Output, Synopsys to GDT
DEC92.ZIP ESNUG Post 92 to Post 97
ESNUG.98 Post 98 Confusion On What Does What In Compiling
ESNUG.99 Post 99 Synopsys VHDL & Actel FPGAs (Part 2 of 2)
ESNUG.100 Synopsys VHDL & Actel FPGAs (Part 1 of 2)
ESNUG.101 Synopsys & Actel FPGA Project Paper
ESNUG.102 Edif fix awk script
ESNUG.103 3.0a library compiler chokes depending on whitespace
ESNUG.104 Backspace/Delete Keys Problem with 3.0a on SUN Workstations
ESNUG.105 Synopsys Follow-Up on Post 103, plotting, partitioning
ESNUG.106 Edifout variables for direct Synopsys to Cadat interface
ESNUG.107 Compile/characterize, Postscript Plotting, synchronous resets
JAN93.ZIP ESNUG Post 98-107 All the January Postings
ESNUG.108 Plotting ? P105, Synchronous reset, Inferring Muxed-D Flip-Flops
ESNUG.109 More Synchronous Reset Issues
ESNUG.110 Even More Synchronous Reset Issues
- CJ Clark
Intellitech Corporation
( Post 112 Item 2 ) ---------------------------------------------------------
From: hotline@synopsys.com ( Synopsys Customer Support )
Subject: ESNUG 111 Item #2 "FPGA compiler problem" plus Another Problem
>We are trying to use the FPGA compiler with Xilinx, and are stuck
>because the xnf created contains FMAP declarations which are not
>completely specified (not all inputs used). The problem occurs when
>you run the Xilinx place and route tools (ppr 1.3), and it errors out
>due to these FMAP declarations.
>The suggested work around is to generate the xnf without FMAP mapping,
>but this pretty much defeats the purpose of using the FPGA Compiler,
>because you are then at the mercy of the mapper from Xilinx, you have
>to build a separate constraint file for the Xilinx tools and you lose
>alot of the top-down design flow. The fix is going to be in the next
>release of the ppr, but that isn't due until October.
Here is the solution for Synopsys FPGA Compiler customers using Xilinx that
are hitting this problem posted on ESNUG. Use the "boundary_optimization"
switch when optimizing the design in the Synopsys environment. This is the
best solution to the problem as the XNF written out by FPGA Compiler will
successfully run through ppr verison 1.3, while still retaining your FMAP
and HMAP declarations.
Using the "boundary_optimization" switch will in no way degrade your quality
of results. This has been documented in the applications note for Xilinx.
If you have not received a copy of this applications note, and are a FPGA
Compiler user, please contact your local Synopsys FAE.
Since the focus of this posting discusses using Synopsys FPGA Compiler and
Xilinx, it is appropriate to mention another potential problem that may occur
when using FPGA Compiler. You may see the following error message when you
run Xilinx's ppr version 1.3 software when it is run on a XNF netlist
generated from FPGA Compiler:
"Failed to map logic as directed by F/HMAP '[inst]' sourcing net '[net]'.
The F/HMAP instance has the CLOSED attribute (MAP=PLC or MAP=PUC)
which requires complete specification of the logic group by the nets
attached to the instance. Check that the logic is completely defined
and that the logic will fit in a single function generator."
This is due to a bug in version 1.3 of ppr. There are two ways around this
bug: 1) Generate XNF withoug FMAP/HMAP, OR 2) Request the special bug-fix
release from Xilinx that fixes this problem (see below).
Xilinx is shipping a special release of DS502 to all Synopsys FPGA Compiler
customers who request it. This special release fixes bugs found in version
1.3 of ppr that are related to using ppr with Synopsys FPGA Compiler.
For further information on how to receive this special release, please
contact Matthew Taylor of Xilinx at (408) 879-5355.
Synopsys Customer Support
Synopsys, Inc.
( Post 112 Item 3 ) ---------------------------------------------------------
From: TRENGD!FJM@TRENGA.tredydev.unisys.com ( Frank Malloy )
Subject: Using XVision and Synopsys
We are using the Synopsys tools set on an HP750, but accessing it on
PCs running XVision, allowing the PC to act as an X server. XVision is
a software product of UniPress Software. This lets us run Design
Analyzer, the Simulator, and everything from our desks.
This usually works very well (graphics look great on VGA), but we have
been getting many intermittent hangs of the PC while using Design
Analyzer. The windows don't refresh (say, during a VHDL compile or a
highlight critical path) and the PC has to be rebooted. The Synopsys
session, however, continues running, but we lose our communications with
it. This behavior is very sporadic and not reproducible.
My question: "Is anyone else using XVision along with Synopsys?"
By the way, we are using Novell LAN WorkPlace for DOS (ver 3.5 & 4.0)
Frank Malloy
Tredyffrin, PA
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