The following ESNUG subscription form was too funny for me not
to post.
- John Cooley
ESNUG Moderator
To: jcooley@world.std.com
From: Loball@cup.portal.com
Subject: Re: Joining ESNUG
Yes! Sign me up! Immediately, if possible! come on, come on, what's the
hold up? Aren't done yet? Well...................
Ahhhhhhhhh, that's better. Thanks! I'm sure everything will work out fine
now. I'm even beginning to believe in the Synopsys Fairy[tm]. You know the
one - Leave a pile of Verilog code under your keyboard at night, and in the
morning you wake up to find a completed gate array.
Later,
Billy
( Post 106 Item 1 ) ----------------------------------------------------------
From: uunet!uranus!splinter!flieder (Jeff Flieder)
Subject: Re: ESNUG Post 105
John,
In Post 105 Item 5, Mike Fitz wrote about a problem with resource
sharing in a large design. It sounds to me like he didn't uniquify the
design before doing the final mapping. The problem occurs because
there is a cell called comp in two different blocks and when they are
both read in and optimized, there is still only one comparator when in
fact there should be two seperate comparators, one for each state
machine. I believe if he runs uniquify prior to the final
re-compilation, the problem will go away.
Jeff Flieder, Senior Engineer, I.C. CAD Development
Ford Microelectronics, Inc. Colorado Springs, CO 80921-3698
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From: epakch@epa.ericsson.se (Kenny Chow - T/HGH)
Subject: Re: ESNUG Post 105
Mikefitz,
I don't know you are using Synopsys 2.2b or 2.2a. There was a 'bug' in 2.2a in
handling synthetic cells but it was fixed in 2.2b. This may not be your
exact problem but it is still worth mentioning. It is not a formal 'bug'
reported to Synopsys in 2.2a. It is only my painful observation.
When Synopsys encounter a comparator or arithmatic operation in the HDL code,
it generate a synthetic cell with a name suffix as serial number, say
'rpl_add_1' for a ripple adder the first time. The second time same function
is invoke, it generate 'rpl_add_2'. Problem arise if 2 modules are compiled
in different Synopsys session, or if you 'remove_design' after compiling the
1st and before compiling the 2nd. The problem is 'rpl_add_1' does not exist
in the memory any more when you compile the 2nd module which use the same
function, then it use the same name 'rpl_add_1' again. In that case, the
second copy of the 'rpl_add_1' generated and optimized will overwrite the
1st copy on the disk when you save the 2nd module. This happened in 2.2a.
The work around I have is either keep all modules in the memory, or 'uniquify'
them before saving it for the 1st module.
In 2.2b, they append the module name in which the synthetic cell was invoked
to be the synthetic cell name and it solve the problem. I hope this will not
come back in 3.0.
Kenny Chow, T/HGH APZ Hardware Design
Ericsson Australia Pty. Ltd.
( Post 106 Item 2 ) ----------------------------------------------------------
From: hayashi@isl.rdc.toshiba.co.jp (Hiroo Hayashi)
Subject: Bugs Beginners Find
jcooley writes: "Have you found any bugs in your running Synopsys?"
I've not yet. I started to use Synopsys last month.
I'm now annoying about some strange dc_shell behaviors. For example,
a value has unnecessary type.
"set_load 10 all_inputs()"
works fine, but
"set_load 10 all_clocks()"
doesn't.
And
"set_load 10 {"clock"}"
works fine, but
"FOO = all_clocks() /* returns {"clock"} */"
"set_load 10 FOO"
doesn't.
But "This isn't a BUG, It's a FEATURE!" :-)
Hiroo Hayashi,
Communication and Information Systems Research Labs.
Research and Development Center, TOSHIBA Corp., Japan
( Post 106 Item 3 ) ----------------------------------------------------------
From: sgolson@trilobyte.com (Steve Golson)
Subject: Tips on Synopsys under OpenWindows
Synopsys normally runs under the Motif window manager, and page 2-4 of
the System Installation and Configuration Guide tells how to install Motif
on a SPARC system.
If you want to run Synopsys under OpenWindows then you don't need to do the
Motif install. However to get the Synopsys fonts and colors you must copy
$SYNOPSYS/admin/setup/Design_analyzer into your own ~/.Xdefaults file,
or into the system-wide $OPENWINHOME/lib/Xdefaults file. Copying the defaults
into /usr/lib/X11/app-defaults/Design_analyzer as explained on page 1-17 only
works if you are running Motif.
Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@trilobyte.com
( Post 106 Item 4 ) ----------------------------------------------------------
From: [ someone who wishes to remain anonymous ]
Subject: Edifout variables for direct Synopsys to Cadat interface
John,
Below are the edifout variables we set to allow a direct Synopsys to
Cadat edif file transfer. This was useful because we didn't have
to translate to Cadat from our Mentor database, that flow has a 16
character name limit, and the Synopsys to Cadat flow doesn't.
/*Use to write edifout from Synopsys that can be read directly into Cadat*/
edifout_target_system = "mentor"
edifout_array_range_naming_style = "%s(%d:%d)"
edifout_array_member_style = "%s(%d)"
edifout_array_member_naming_style = "%s(%d)"
edifout_external = "true"
edifout_ground_name = "VSS"
edifout_ground_net_name = "VSS"
edifout_ground_net_property_name = "INIT"
edifout_ground_net_property_value = "0SF"
edifout_ground_pin_name = "GROUND_PIN"
edifout_instance_property_name = ""
edifout_instantiate_ports = "true"
edifout_merge_libraries = "false"
edifout_netlist_only = "true"
edifout_no_array = "true"
edifout_pin_direction_in_value = "in"
edifout_pin_direction_inout_value = "inout"
edifout_pin_direction_out_value = "out"
edifout_pin_direction_property_name = "PINTYPE"
edifout_pin_name_property_name = ""
edifout_portinstance_disabled_property_name = ""
edifout_portinstance_disabled_property_value = ""
edifout_portinstance_property_name = ""
edifout_power_and_ground_representation = "net"
edifout_power_name = "VDD"
edifout_power_net_name = "VDD"
edifout_power_net_property_name = "INIT"
edifout_power_net_property_value = "1SF"
edifout_power_pin_name = "POWER_PIN"
edifout_pretty_print = "false"
edifout_skip_port_implementations = "false"
edifout_translate_origin = "center"
( Post 106 Networking Section ) ----------------------------------------------
LEVEL ONE COMMUNICATIONS has contract for experienced VHDL/Synopsys
ASIC designer, approx 3-6 months. Wanted ASAP. rays@level1.com (Ray Sluzewicz)
Opening in AMD for a Sr Design Engineer to dsgn LAN cntrllr. HDL & synthesis
experience a must, LAN knowledgement a plus. Contact larry.sheu@amd.com
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