( Post 102 Item 1 ) --------------------------------------------------------
From: kagar@dtc.Kodak.COM (Keith Agar)
Subject: Edif fix awk script
John,
This is a response to problems described in Peter's write-up of his
experiences using Synopsys VHDL and Actel FPGA's ( ESNUG Posts 99 & 100.)
Below is the EDIF fix awk script that MUST be run on an edifout file from
Synopsys v22b before ESIread will work. This script was written
by Matt Wandschneider of Synopsys.
Keith Agar
Eastman Kodak Co.
716/726-7684
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#! /bin/awk -f
# Name this file edif_fix22b and make it executable.
# Use as: edif_fix22b input_edif_file > output_edif_file
# This awk script works around a problem with Design Compiler version
# 2.2 and ESIread from Mentor. Sometimes Design Compiler's schematic
# generator uses multiple off-sheet connectors, of the same function,
# on the same page. For example, on a particular page, you might have
# an input port A feeding an output off-sheet connector A. On the same
# page you might also have an input off-sheet connector A. ESIread does
# not allow this type of schematic. Because there is currently no way
# to prevent the schematic generator from generating a schematic page
# having the situation described above, it is necessary to post process
# the EDIF schematic. This script removes an off-sheet input connector
# which is on the same page as a off-sheet output connector. Also, it
# makes sure that no multiple off-sheet output connectors exist on the
# same page. Finally, it makes sure that the port and off-sheet symbols
# have different instance names.
# Before running this script, edit the variables iosc and oosc
# below to reflect the EDIF names used by Design Compiler to represent
# the Mentor input off-sheet connector and output off-sheet connector.
# After this change, run the script with the EDIF schematic from
# Design Compiler as input. Redirect the output of the script to a
# new filename. Use this new file as input to ESIread.
BEGIN {
iosc = "OFFPAG_46_IN"
oosc = "OFFPAG_46_OUT"
in_page = 0
in_portImplementation = 0
in_portImplementation_name = 0
in_instance = 0
in_rename = 0
name_count = 0
in_cellRef = 0
instance_position = 0
temp = 0
portImplementation_number = 0
process_portImplementations = 0
portImplementations_processed = 0
}
# The following section counts parentheses (indicating EDIF constructs)
# and triggers the capture of EDIF names and constructs directly
# associated with the implementations of ports and osc's on a specific page
{
for(j = 1; j <= NF; j++){
line[j] = $j
# The next line extracts the open parentheses from each word
k = split(line[j],word1,"(")
open_edif_constructs += (k - 1)
for(l = 1; l <= k; l++){
if(word1[l] != ""){
# The next line extracts the close parentheses from each word
m = split(word1[l],word2,")")
open_edif_constructs -= (m - 1)
for(n = 1; n <= m; n++){
if(word2[n] != ""){
# Identify the parentheses count for this page and reset variables for
# the new page
if(word2[n] == "page"){
in_page = open_edif_constructs - 1
portImplementations_processed = 0
}
# Grab the port implementation name
if(in_portImplementation != 0 && in_portImplementation_name != 0){
portImplementation_name[portImplementation_number] = word2[n]
in_portImplementation_name = 0
}
# Prepare to grap port implementation name and entire construct
if(in_page != 0 && word2[n] == "portImplementation"){
in_portImplementation = open_edif_constructs
in_portImplementation_name = 1
portImplementation_number += 1
}
# Grab the cell reference name
if(in_portImplementation != 0 && in_cellRef != 0){
cellRef[portImplementation_number] = word2[n]
in_cellRef = 0
}
# Prepare to grab the cell reference name
if(in_portImplementation != 0 && word2[n] == "cellRef"){
in_cellRef = 1
}
# Grab the renamed instance name
if(in_rename != 0){
name_count += 1
if(name_count == 2){
instance[portImplementation_number] = word2[n]
in_rename = 0
name_count = 0
in_instance = 0
}
}
# Prepare to grab the renamed instance name
if(in_instance != 0 && word2[n] == "rename"){
in_rename = 1
in_instance = 0
}
# Grab the instance name
if(in_instance != 0 && word2[n] != "rename"){
instance[portImplementation_number] = word2[n]
in_instance = 0
}
# Prepare to grab instance name or enter rename construct
if(in_portImplementation != 0 && word2[n] == "instance"){
in_instance = 1
}
# Prepare to process port implementation constructs
if(portImplementations_processed == 0 && in_portImplementation == 0 && word2[n] == "instance"){
process_portImplementations = 1
}
}
}
}
}
}
}
# The following section processes the port implementation constructs
# to remove input off-page connectors which are on the same page as
# ports or output off-page connectors. An output off-page connector
# is removed if it duplicates another output off-page connector on the
# same page. Finally, port and off-page connector instance names are
# made unique if they are not already.
{
if(process_portImplementations == 1){
for(i = 1; i <= portImplementation_number; i++){
for(j = i + 1; j <= portImplementation_number; j++){
# If port implementation names are the same, delete the input off-page
# connector or duplicate off-page connector
if(portImplementation_name[i] == portImplementation_name[j]){
if(cellRef[i] == iosc && cellRef[j] == iosc){
portImplementation[j] = ""
portImplementation_name[j] = ""
instance[j] = ""
cellRef[j] = ""
}
if(cellRef[i] == iosc && cellRef[j] != iosc){
portImplementation[i] = ""
portImplementation_name[i] = ""
instance[i] = ""
cellRef[i] = ""
}
if(cellRef[i] != iosc && cellRef[j] == iosc){
portImplementation[j] = ""
portImplementation_name[j] = ""
instance[j] = ""
cellRef[j] = ""
}
if(cellRef[i] == oosc && cellRef[j] == oosc){
portImplementation[j] = ""
portImplementation_name[j] = ""
instance[j] = ""
cellRef[j] = ""
}
}
# If the connector instance names are the same, change the off-page
# connector's instance name
if(instance[i] == instance[j]){
if(cellRef[i] == iosc || cellRef[i] == oosc){
instance_position = index(portImplementation[i],"instance")
temp = substr(portImplementation[i],instance_position)
instance_position = instance_position + index(temp,instance[i]) + length(instance[i]) - 2
if(index(instance[i],"\"") != 0){
portImplementation[i] = substr(portImplementation[i],1,instance_position - 1) "_osc" substr(portImplementation[i],instance_position)
}
else{
portImplementation[i] = substr(portImplementation[i],1,instance_position) "_osc" substr(portImplementation[i],instance_position + 1)
}
}
if(cellRef[j] == iosc || cellRef[j] == oosc){
instance_position = index(portImplementation[j],"instance")
temp = substr(portImplementation[j],instance_position)
instance_position = instance_position + index(temp,instance[j]) + length(instance[j]) - 2
if(index(instance[j],"\"") != 0){
portImplementation[j] = substr(portImplementation[j],1,instance_position - 1) "_osc" substr(portImplementation[j],instance_position)
}
else{
portImplementation[j] = substr(portImplementation[j],1,instance_position) "_osc" substr(portImplementation[j],instance_position + 1)
}
}
}
}
}
# Print the processed port implementation constructs
for(i = 1; i <= portImplementation_number; i++){
if(portImplementation[i] != "")
print portImplementation[i]
portImplementation[i] = ""
}
# Reset variables for the next port implementation section
process_portImplementations = 0
portImplementations_processed = 1
}
}
# If the current line is not part of a port implementation, print the
# line with no processing. If the current line is part of the port
# implementation, append the current line to the current port implementation
# being captured.
{
if(in_portImplementation == 0){
print $0
}
else{
if(portImplementation[portImplementation_number] != "")
portImplementation[portImplementation_number] = portImplementation[portImplementation_number] "\n" $0
else
portImplementation[portImplementation_number] = portImplementation[portImplementation_number] $0
}
}
# If the end of a page has been reached, reset variables for the next page
{
if(open_edif_constructs <= in_page){
in_page = 0
portImplementation_number = 0
}
}
# If the end of a port implementation has been reached, reset variables
# for the next port implementation construct
{
if(open_edif_constructs < in_portImplementation){
in_portImplementation = 0
}
}
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