( Post 101 Item 1 ) ----------------------------------------------------
From: gderti@dtc.Kodak.COM (Gzim Derti)
Subject: Re: ESNUG Post 99 &100 - Synopsys & Actel FPGA Project Paper
John,
We here at Kodak ran into the same sort of problems. Some of our solutions are
as follows :
1) Concerning flip-flops with negative edge clocks we altered the Actel library
to use only flip-flops with positive edge clocks by placing dont_touch *and*
dont_use into the library files.
2) Concerning the clock tree for Actel when compiling use both
dont_touch <clock name> *and* dont_touch_network <clock_name>.
The same holds true for the reset network in the design.
We had problems with this when instantiating I/O buffers into the design,
a way around this problem we found was to keep the I/O buffers at their
own level of hierarchy i.e. above the top level entity in an hierarchical
design. If this wasn't done Synopsys would buffer the reset line even
though we had performed a dont_touch and dont_touch_network as stated
above.
3) Concerning the naming of buses in Synopsys for edif transfer into the
Mentor design environment we ran into no problems with using the "[]"
in the normal naming of busses from Synopsys to Mentor to the ACTEL
environment so as far as the problem concerning that we used the
normal Synopsys setups and it worked fine.
We did however have the problem of designs when saved as edif not being
able to be read by the Mentor esiread command. The only work around was
finally given to us by someone at Synopsys who was able to write for us
a Unix awk script which would post process the Synopsys edif file fix
the problem and then Mentor could read the file in. This problem had to
do with multiple INTRA page connectors on the same net on the same page
of a design. i.e. if the signal junk goes off page at two places on a
sheet due to Synopsys schematic generation then Synopsys places an INTRA
page connector at both ends of the net, which if done in Mentor NETED
works fine, but when trying to be read by esiread it would pretty much
throw-up on us.
Well that's about all I have for now. Thanks for the ESNUG messages I think
that it is really nice to know that we here at Kodak aren't the only ones
to have found these problems. That's what it always sounded like when
we would call the Synopsys hotline. By the by - as for a time frame on
when we worked out these problems it was during the end of 1991 and the
beginning of 1992 from about October to March. So if your problems came
after this then once again the Synopsys hotline has no clue as to what
it is doing.......(like that's something new)
Thanks for listening.
Gzim Derti
(say Zim Dair-tee)
(aren't parents grand)
( Post 101 Item 2 ) ----------------------------------------------------
From: Terrence.Bygate@ColumbiaSC.NCR.COM
Subject: Re: ESNUG Post 99 &100 - Synopsys & Actel FPGA Project Paper
> Illegal characters
>
> Synopsys uses square brackets [] for members of a bus, and this
> can not be changed for the individual bus members. Since the
> Mentor interface could not handle busses, individual bus members
> had to be used. Unfortunately, square brackets are illegal in
> Actel designs. When contacted, Synopsys proposed to use a new
> feature called "Name whacker", a rule-driven character
> substitution tool. Keeping it simple and stupid, we used vi to
> change the brackets in the mentor do file to underscores.
>
We have had similar problems with case sensitivity of the library names
and with the use of brackets by Synopsys.
With regards to Synopsys using brackets, after generating the do file
with the V7 Mentor Interface, we ran the do file through a Unix sed script.
For brackets associated with net names, ports, etc., we substituted the
bracket with an appropriate parenthesis. For brackets associated with
instances such as a f/f, we substituted an underscore for the bracket.
The above took a few trials to get it to work properly with Mentor.
The advantages of substituting brackets with a mix of parenthesis and
underscores, were two fold:
- the Mentor symbol for the synthesized logic could use a 'bused' name.
- when simulating the design under Mentor, we could use buses when
simulating the synthesized design without grouping the individual
signal names.
Terrence A. Bygate
Multiprocessor Systems Business Unit
NCR Corporation
( Post 101 Item 3 ) ----------------------------------------------------
From: jmh@sunpix.East.Sun.COM (Justin Heinecke - Sun NC Development Center)
To: psi@wd.estec.esa.nl
Subject: Synopsys & Actel - Post 99 & 100
Peter,
I read with great interest your report summarizing the difficulties
in going from VHDL to ACTEL via Synopsys, and I have some comments.
We have produced several designs in Verilog, and used Synopsys to
go to a number of targets, including an LSI asic and an Actel ACT1
device.
I discovered (as you did) that Synopsys likes to put buffers into
the clock net, without apparent regard for the drive strength of the
clock input buffer. We fixed this by putting a "dont_touch" on the
clock net. This also worked on the reset net, but we opted for the
buffers in this case.
As I recall, the first release of ACT1 library for Synopsys was
completely useless, but the second release worked fine. And, yes,
the documentation was terse. It helped to have several target vendors,
and sort of read between the lines where any one vendor was vague.
I saved the Synopsys desing in EDIF, and used an Actel supplied
utility "edn2adl" to translate the design to Actel's .adl format.
From there everything went smoothly.
However, none of the Actel parts have yet been plugged into a proto-
type board; I'm interested in the details of the bug in the Actel
library for Synopsys.
Thanks for the report.
justin heinecke
( Post 101 Item 4 ) ----------------------------------------------------
From: mahmood@compass-da.com (Mossaddeq Mahmood)
To: psi@wd.estec.esa.nl
Subject: Re: ESNUG Post 99 and 100 Synopsys VHDL and Actel FPGAs
Hello Peter:
I read your article entitled:
Synopsys VHDL & Actel FPGAs
It was interesting to know the total experience of synthesis
rather than fragmented information.
I greatly appreciate your contribution.
I hope other ESNUG readers who can provide a total experience of using
synthesis tools (Synopsys or other vendors) can contribute to ESNUG.
Best Regards.
Mossaddeq Mahmood
Compass Design
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