Dear ESNUG readers,
Enclosed is part two of a two part paper I requested from
Peter Sinander of the European Space Agency Technology Centre
discussing his experiences with Synopsys VHDL and Actel chips.
The idea behind this type of ESNUG post is to occassionaly
have articles that discuss an entire project experience using
Synopsys tools. Please tell me what you think of this type of
ESNUG post plus, as always, whatever comments you have concerning
this paper itself.
- John Cooley
ESNUG Moderator
( Post 100 Item 1 ) ---------------------------------------------------------
From: psi@wd.estec.esa.nl (Peter Sinander)
Subject: Synopsys VHDL & Actel FPGAs (Part 2 of 2)
[ Part 2 continued ]
Illegal characters
Synopsys uses square brackets [] for members of a bus, and this
can not be changed for the individual bus members. Since the
Mentor interface could not handle busses, individual bus members
had to be used. Unfortunately, square brackets are illegal in
Actel designs. When contacted, Synopsys proposed to use a new
feature called "Name whacker", a rule-driven character
substitution tool. Keeping it simple and stupid, we used vi to
change the brackets in the mentor do file to underscores.
Summary
Synopsys is interesting for fast prototyping, ASIC validation,
test equipment etc., since it offers a short design cycle at the
RT-level, even if it requires manual patching as described above.
In these cases, the area penalty can be dealt with by partitioning
the design into several FPGAs. Considering the area overhead, it
is questionable to use the current version for products in volume
production.
Actel definitely need to provide proper documentation for the
Synopsys library. This should also address workarounds for the
limitations and problems in the current Synopsys version.
Synopsys cannot be blamed for the poor synthesis results, after
all the algorithms was developed for ASICs. Algorithms tailored to
FPGAs have been announced for other synthesis tools, which are
claimed to give good results for FPGAs. The large overhead cannot
be accepted for new versions, and Synopsys needs to address this
in the next release.
Another point is not to trust simulation models generated from the
synthesis library, unless approved by the ASIC manufacturer. Being
new libraries, it is likely that errors will exist; we have
already seen several examples of this.
The support people has generally been friendly and tried to help.
Most of the information is patches that more or less successfully
solve the immediate problems, and it is often difficult to know if
the problems are going to be solved in the long term, i.e. in the
next release. Hopefully the tool developers *ARE* made aware of
the problems. The answer will come with the next release.
Peter Sinander European Space Agency Technology Centre
ESTEC WDN e-mail: psi@wd.estec.esa.nl
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